channv50.h (1747B)
1/* SPDX-License-Identifier: MIT */ 2#ifndef __NV50_FIFO_CHAN_H__ 3#define __NV50_FIFO_CHAN_H__ 4#define nv50_fifo_chan(p) container_of((p), struct nv50_fifo_chan, base) 5#include "chan.h" 6#include "nv50.h" 7 8struct nv50_fifo_chan { 9 struct nv50_fifo *fifo; 10 struct nvkm_fifo_chan base; 11 12 struct nvkm_gpuobj *ramfc; 13 struct nvkm_gpuobj *cache; 14 struct nvkm_gpuobj *eng; 15 struct nvkm_gpuobj *pgd; 16 struct nvkm_ramht *ramht; 17 18#define NV50_FIFO_ENGN_SW 0 19#define NV50_FIFO_ENGN_GR 1 20#define NV50_FIFO_ENGN_MPEG 2 21#define NV50_FIFO_ENGN_DMA 3 22 23#define G84_FIFO_ENGN_SW 0 24#define G84_FIFO_ENGN_GR 1 25#define G84_FIFO_ENGN_MPEG 2 26#define G84_FIFO_ENGN_MSPPP 2 27#define G84_FIFO_ENGN_ME 3 28#define G84_FIFO_ENGN_CE0 3 29#define G84_FIFO_ENGN_VP 4 30#define G84_FIFO_ENGN_MSPDEC 4 31#define G84_FIFO_ENGN_CIPHER 5 32#define G84_FIFO_ENGN_SEC 5 33#define G84_FIFO_ENGN_VIC 5 34#define G84_FIFO_ENGN_BSP 6 35#define G84_FIFO_ENGN_MSVLD 6 36#define G84_FIFO_ENGN_DMA 7 37 struct nvkm_gpuobj *engn[NVKM_FIFO_ENGN_NR]; 38}; 39 40int nv50_fifo_chan_ctor(struct nv50_fifo *, u64 vmm, u64 push, 41 const struct nvkm_oclass *, struct nv50_fifo_chan *); 42void *nv50_fifo_chan_dtor(struct nvkm_fifo_chan *); 43void nv50_fifo_chan_fini(struct nvkm_fifo_chan *); 44struct nvkm_gpuobj **nv50_fifo_chan_engine(struct nv50_fifo_chan *, struct nvkm_engine *); 45void nv50_fifo_chan_engine_dtor(struct nvkm_fifo_chan *, struct nvkm_engine *); 46void nv50_fifo_chan_object_dtor(struct nvkm_fifo_chan *, int); 47 48int g84_fifo_chan_ctor(struct nv50_fifo *, u64 vmm, u64 push, 49 const struct nvkm_oclass *, struct nv50_fifo_chan *); 50 51extern const struct nvkm_fifo_chan_oclass nv50_fifo_gpfifo_oclass; 52extern const struct nvkm_fifo_chan_oclass g84_fifo_gpfifo_oclass; 53#endif