dmanv04.c (7237B)
1/* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24#include "channv04.h" 25#include "regsnv04.h" 26 27#include <core/client.h> 28#include <core/ramht.h> 29#include <subdev/instmem.h> 30 31#include <nvif/class.h> 32#include <nvif/cl006b.h> 33#include <nvif/unpack.h> 34 35void 36nv04_fifo_dma_object_dtor(struct nvkm_fifo_chan *base, int cookie) 37{ 38 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); 39 struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem; 40 41 mutex_lock(&chan->fifo->base.mutex); 42 nvkm_ramht_remove(imem->ramht, cookie); 43 mutex_unlock(&chan->fifo->base.mutex); 44} 45 46static int 47nv04_fifo_dma_object_ctor(struct nvkm_fifo_chan *base, 48 struct nvkm_object *object) 49{ 50 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); 51 struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem; 52 u32 context = 0x80000000 | chan->base.chid << 24; 53 u32 handle = object->handle; 54 int hash; 55 56 switch (object->engine->subdev.type) { 57 case NVKM_ENGINE_DMAOBJ: 58 case NVKM_ENGINE_SW : context |= 0x00000000; break; 59 case NVKM_ENGINE_GR : context |= 0x00010000; break; 60 case NVKM_ENGINE_MPEG : context |= 0x00020000; break; 61 default: 62 WARN_ON(1); 63 return -EINVAL; 64 } 65 66 mutex_lock(&chan->fifo->base.mutex); 67 hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4, 68 handle, context); 69 mutex_unlock(&chan->fifo->base.mutex); 70 return hash; 71} 72 73void 74nv04_fifo_dma_fini(struct nvkm_fifo_chan *base) 75{ 76 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); 77 struct nv04_fifo *fifo = chan->fifo; 78 struct nvkm_device *device = fifo->base.engine.subdev.device; 79 struct nvkm_memory *fctx = device->imem->ramfc; 80 const struct nv04_fifo_ramfc *c; 81 unsigned long flags; 82 u32 mask = fifo->base.nr - 1; 83 u32 data = chan->ramfc; 84 u32 chid; 85 86 /* prevent fifo context switches */ 87 spin_lock_irqsave(&fifo->base.lock, flags); 88 nvkm_wr32(device, NV03_PFIFO_CACHES, 0); 89 90 /* if this channel is active, replace it with a null context */ 91 chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & mask; 92 if (chid == chan->base.chid) { 93 nvkm_mask(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0); 94 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0); 95 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); 96 97 c = fifo->ramfc; 98 nvkm_kmap(fctx); 99 do { 100 u32 rm = ((1ULL << c->bits) - 1) << c->regs; 101 u32 cm = ((1ULL << c->bits) - 1) << c->ctxs; 102 u32 rv = (nvkm_rd32(device, c->regp) & rm) >> c->regs; 103 u32 cv = (nvkm_ro32(fctx, c->ctxp + data) & ~cm); 104 nvkm_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs)); 105 } while ((++c)->bits); 106 nvkm_done(fctx); 107 108 c = fifo->ramfc; 109 do { 110 nvkm_wr32(device, c->regp, 0x00000000); 111 } while ((++c)->bits); 112 113 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, 0); 114 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUT, 0); 115 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, mask); 116 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); 117 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 118 } 119 120 /* restore normal operation, after disabling dma mode */ 121 nvkm_mask(device, NV04_PFIFO_MODE, 1 << chan->base.chid, 0); 122 nvkm_wr32(device, NV03_PFIFO_CACHES, 1); 123 spin_unlock_irqrestore(&fifo->base.lock, flags); 124} 125 126void 127nv04_fifo_dma_init(struct nvkm_fifo_chan *base) 128{ 129 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); 130 struct nv04_fifo *fifo = chan->fifo; 131 struct nvkm_device *device = fifo->base.engine.subdev.device; 132 u32 mask = 1 << chan->base.chid; 133 unsigned long flags; 134 spin_lock_irqsave(&fifo->base.lock, flags); 135 nvkm_mask(device, NV04_PFIFO_MODE, mask, mask); 136 spin_unlock_irqrestore(&fifo->base.lock, flags); 137} 138 139void * 140nv04_fifo_dma_dtor(struct nvkm_fifo_chan *base) 141{ 142 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); 143 struct nv04_fifo *fifo = chan->fifo; 144 struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; 145 const struct nv04_fifo_ramfc *c = fifo->ramfc; 146 147 nvkm_kmap(imem->ramfc); 148 do { 149 nvkm_wo32(imem->ramfc, chan->ramfc + c->ctxp, 0x00000000); 150 } while ((++c)->bits); 151 nvkm_done(imem->ramfc); 152 return chan; 153} 154 155const struct nvkm_fifo_chan_func 156nv04_fifo_dma_func = { 157 .dtor = nv04_fifo_dma_dtor, 158 .init = nv04_fifo_dma_init, 159 .fini = nv04_fifo_dma_fini, 160 .object_ctor = nv04_fifo_dma_object_ctor, 161 .object_dtor = nv04_fifo_dma_object_dtor, 162}; 163 164static int 165nv04_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, 166 void *data, u32 size, struct nvkm_object **pobject) 167{ 168 struct nvkm_object *parent = oclass->parent; 169 union { 170 struct nv03_channel_dma_v0 v0; 171 } *args = data; 172 struct nv04_fifo *fifo = nv04_fifo(base); 173 struct nv04_fifo_chan *chan = NULL; 174 struct nvkm_device *device = fifo->base.engine.subdev.device; 175 struct nvkm_instmem *imem = device->imem; 176 int ret = -ENOSYS; 177 178 nvif_ioctl(parent, "create channel dma size %d\n", size); 179 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { 180 nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " 181 "offset %08x\n", args->v0.version, 182 args->v0.pushbuf, args->v0.offset); 183 if (!args->v0.pushbuf) 184 return -EINVAL; 185 } else 186 return ret; 187 188 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) 189 return -ENOMEM; 190 *pobject = &chan->base.object; 191 192 ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base, 193 0x1000, 0x1000, false, 0, args->v0.pushbuf, 194 BIT(NV04_FIFO_ENGN_SW) | 195 BIT(NV04_FIFO_ENGN_GR) | 196 BIT(NV04_FIFO_ENGN_DMA), 197 0, 0x800000, 0x10000, oclass, &chan->base); 198 chan->fifo = fifo; 199 if (ret) 200 return ret; 201 202 args->v0.chid = chan->base.chid; 203 chan->ramfc = chan->base.chid * 32; 204 205 nvkm_kmap(imem->ramfc); 206 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); 207 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); 208 nvkm_wo32(imem->ramfc, chan->ramfc + 0x08, chan->base.push->addr >> 4); 209 nvkm_wo32(imem->ramfc, chan->ramfc + 0x10, 210 NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | 211 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | 212#ifdef __BIG_ENDIAN 213 NV_PFIFO_CACHE1_BIG_ENDIAN | 214#endif 215 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); 216 nvkm_done(imem->ramfc); 217 return 0; 218} 219 220const struct nvkm_fifo_chan_oclass 221nv04_fifo_dma_oclass = { 222 .base.oclass = NV03_CHANNEL_DMA, 223 .base.minver = 0, 224 .base.maxver = 0, 225 .ctor = nv04_fifo_dma_new, 226};