dmanv10.c (3307B)
1/* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24#include "channv04.h" 25#include "regsnv04.h" 26 27#include <core/client.h> 28#include <core/gpuobj.h> 29#include <subdev/instmem.h> 30 31#include <nvif/class.h> 32#include <nvif/cl006b.h> 33#include <nvif/unpack.h> 34 35static int 36nv10_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, 37 void *data, u32 size, struct nvkm_object **pobject) 38{ 39 struct nvkm_object *parent = oclass->parent; 40 union { 41 struct nv03_channel_dma_v0 v0; 42 } *args = data; 43 struct nv04_fifo *fifo = nv04_fifo(base); 44 struct nv04_fifo_chan *chan = NULL; 45 struct nvkm_device *device = fifo->base.engine.subdev.device; 46 struct nvkm_instmem *imem = device->imem; 47 int ret = -ENOSYS; 48 49 nvif_ioctl(parent, "create channel dma size %d\n", size); 50 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { 51 nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " 52 "offset %08x\n", args->v0.version, 53 args->v0.pushbuf, args->v0.offset); 54 if (!args->v0.pushbuf) 55 return -EINVAL; 56 } else 57 return ret; 58 59 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) 60 return -ENOMEM; 61 *pobject = &chan->base.object; 62 63 ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base, 64 0x1000, 0x1000, false, 0, args->v0.pushbuf, 65 BIT(NV04_FIFO_ENGN_SW) | 66 BIT(NV04_FIFO_ENGN_GR) | 67 BIT(NV04_FIFO_ENGN_DMA), 68 0, 0x800000, 0x10000, oclass, &chan->base); 69 chan->fifo = fifo; 70 if (ret) 71 return ret; 72 73 args->v0.chid = chan->base.chid; 74 chan->ramfc = chan->base.chid * 32; 75 76 nvkm_kmap(imem->ramfc); 77 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); 78 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); 79 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); 80 nvkm_wo32(imem->ramfc, chan->ramfc + 0x14, 81 NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | 82 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | 83#ifdef __BIG_ENDIAN 84 NV_PFIFO_CACHE1_BIG_ENDIAN | 85#endif 86 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); 87 nvkm_done(imem->ramfc); 88 return 0; 89} 90 91const struct nvkm_fifo_chan_oclass 92nv10_fifo_dma_oclass = { 93 .base.oclass = NV10_CHANNEL_DMA, 94 .base.minver = 0, 95 .base.maxver = 0, 96 .ctor = nv10_fifo_dma_new, 97};