cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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gp100.c (3421B)


      1/*
      2 * Copyright 2016 Red Hat Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: Ben Skeggs
     23 */
     24#include "gk104.h"
     25#include "changk104.h"
     26
     27#include <subdev/fault.h>
     28
     29#include <nvif/class.h>
     30
     31const struct nvkm_enum
     32gp100_fifo_fault_engine[] = {
     33	{ 0x01, "DISPLAY" },
     34	{ 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
     35	{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
     36	{ 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
     37	{ 0x06, "HOST0", NULL, NVKM_ENGINE_FIFO },
     38	{ 0x07, "HOST1", NULL, NVKM_ENGINE_FIFO },
     39	{ 0x08, "HOST2", NULL, NVKM_ENGINE_FIFO },
     40	{ 0x09, "HOST3", NULL, NVKM_ENGINE_FIFO },
     41	{ 0x0a, "HOST4", NULL, NVKM_ENGINE_FIFO },
     42	{ 0x0b, "HOST5", NULL, NVKM_ENGINE_FIFO },
     43	{ 0x0c, "HOST6", NULL, NVKM_ENGINE_FIFO },
     44	{ 0x0d, "HOST7", NULL, NVKM_ENGINE_FIFO },
     45	{ 0x0e, "HOST8", NULL, NVKM_ENGINE_FIFO },
     46	{ 0x0f, "HOST9", NULL, NVKM_ENGINE_FIFO },
     47	{ 0x10, "HOST10", NULL, NVKM_ENGINE_FIFO },
     48	{ 0x13, "PERF" },
     49	{ 0x17, "PMU" },
     50	{ 0x18, "PTP" },
     51	{ 0x1f, "PHYSICAL" },
     52	{}
     53};
     54
     55void
     56gp100_fifo_intr_fault(struct nvkm_fifo *fifo, int unit)
     57{
     58	struct nvkm_device *device = fifo->engine.subdev.device;
     59	u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
     60	u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
     61	u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
     62	u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10));
     63	struct nvkm_fault_data info;
     64
     65	info.inst   =  (u64)inst << 12;
     66	info.addr   = ((u64)vahi << 32) | valo;
     67	info.time   = 0;
     68	info.engine = unit;
     69	info.valid  = 1;
     70	info.gpc    = (type & 0x1f000000) >> 24;
     71	info.hub    = (type & 0x00100000) >> 20;
     72	info.access = (type & 0x00070000) >> 16;
     73	info.client = (type & 0x00007f00) >> 8;
     74	info.reason = (type & 0x0000001f);
     75
     76	nvkm_fifo_fault(fifo, &info);
     77}
     78
     79static const struct gk104_fifo_func
     80gp100_fifo = {
     81	.intr.fault = gp100_fifo_intr_fault,
     82	.pbdma = &gm200_fifo_pbdma,
     83	.fault.access = gk104_fifo_fault_access,
     84	.fault.engine = gp100_fifo_fault_engine,
     85	.fault.reason = gk104_fifo_fault_reason,
     86	.fault.hubclient = gk104_fifo_fault_hubclient,
     87	.fault.gpcclient = gk104_fifo_fault_gpcclient,
     88	.runlist = &gm107_fifo_runlist,
     89	.chan = {{0,0,PASCAL_CHANNEL_GPFIFO_A}, gk104_fifo_gpfifo_new },
     90	.cgrp_force = true,
     91};
     92
     93int
     94gp100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
     95	       struct nvkm_fifo **pfifo)
     96{
     97	return gk104_fifo_new_(&gp100_fifo, device, type, inst, 4096, pfifo);
     98}