cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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gp104.c (3887B)


      1/*
      2 * Copyright 2018 Red Hat Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 */
     22#include "gf100.h"
     23#include "ctxgf100.h"
     24
     25#include <nvif/class.h>
     26
     27static const struct gf100_gr_func
     28gp104_gr = {
     29	.oneinit_tiles = gm200_gr_oneinit_tiles,
     30	.oneinit_sm_id = gm200_gr_oneinit_sm_id,
     31	.init = gf100_gr_init,
     32	.init_gpc_mmu = gm200_gr_init_gpc_mmu,
     33	.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
     34	.init_zcull = gf117_gr_init_zcull,
     35	.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
     36	.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
     37	.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
     38	.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
     39	.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
     40	.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
     41	.init_419cc0 = gf100_gr_init_419cc0,
     42	.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
     43	.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
     44	.init_504430 = gm107_gr_init_504430,
     45	.init_shader_exceptions = gp100_gr_init_shader_exceptions,
     46	.trap_mp = gf100_gr_trap_mp,
     47	.rops = gm200_gr_rops,
     48	.gpc_nr = 6,
     49	.tpc_nr = 5,
     50	.ppc_nr = 3,
     51	.grctx = &gp104_grctx,
     52	.zbc = &gp102_gr_zbc,
     53	.sclass = {
     54		{ -1, -1, FERMI_TWOD_A },
     55		{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
     56		{ -1, -1, PASCAL_B, &gf100_fermi },
     57		{ -1, -1, PASCAL_COMPUTE_B },
     58		{}
     59	}
     60};
     61
     62MODULE_FIRMWARE("nvidia/gp104/gr/fecs_bl.bin");
     63MODULE_FIRMWARE("nvidia/gp104/gr/fecs_inst.bin");
     64MODULE_FIRMWARE("nvidia/gp104/gr/fecs_data.bin");
     65MODULE_FIRMWARE("nvidia/gp104/gr/fecs_sig.bin");
     66MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_bl.bin");
     67MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_inst.bin");
     68MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_data.bin");
     69MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_sig.bin");
     70MODULE_FIRMWARE("nvidia/gp104/gr/sw_ctx.bin");
     71MODULE_FIRMWARE("nvidia/gp104/gr/sw_nonctx.bin");
     72MODULE_FIRMWARE("nvidia/gp104/gr/sw_bundle_init.bin");
     73MODULE_FIRMWARE("nvidia/gp104/gr/sw_method_init.bin");
     74
     75MODULE_FIRMWARE("nvidia/gp106/gr/fecs_bl.bin");
     76MODULE_FIRMWARE("nvidia/gp106/gr/fecs_inst.bin");
     77MODULE_FIRMWARE("nvidia/gp106/gr/fecs_data.bin");
     78MODULE_FIRMWARE("nvidia/gp106/gr/fecs_sig.bin");
     79MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_bl.bin");
     80MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_inst.bin");
     81MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_data.bin");
     82MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_sig.bin");
     83MODULE_FIRMWARE("nvidia/gp106/gr/sw_ctx.bin");
     84MODULE_FIRMWARE("nvidia/gp106/gr/sw_nonctx.bin");
     85MODULE_FIRMWARE("nvidia/gp106/gr/sw_bundle_init.bin");
     86MODULE_FIRMWARE("nvidia/gp106/gr/sw_method_init.bin");
     87
     88static const struct gf100_gr_fwif
     89gp104_gr_fwif[] = {
     90	{  0, gm200_gr_load, &gp104_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr },
     91	{ -1, gm200_gr_nofw },
     92	{}
     93};
     94
     95int
     96gp104_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
     97{
     98	return gf100_gr_new_(gp104_gr_fwif, device, type, inst, pgr);
     99}