gv100.c (5112B)
1/* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22#include "gf100.h" 23#include "ctxgf100.h" 24 25#include <nvif/class.h> 26 27static void 28gv100_gr_trap_sm(struct gf100_gr *gr, int gpc, int tpc, int sm) 29{ 30 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 31 struct nvkm_device *device = subdev->device; 32 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x730 + (sm * 0x80))); 33 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x734 + (sm * 0x80))); 34 const struct nvkm_enum *warp; 35 char glob[128]; 36 37 nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr); 38 warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff); 39 40 nvkm_error(subdev, "GPC%i/TPC%i/SM%d trap: " 41 "global %08x [%s] warp %04x [%s]\n", 42 gpc, tpc, sm, gerr, glob, werr, warp ? warp->name : ""); 43 44 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x730 + sm * 0x80), 0x00000000); 45 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x734 + sm * 0x80), gerr); 46} 47 48void 49gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) 50{ 51 gv100_gr_trap_sm(gr, gpc, tpc, 0); 52 gv100_gr_trap_sm(gr, gpc, tpc, 1); 53} 54 55static void 56gv100_gr_init_4188a4(struct gf100_gr *gr) 57{ 58 struct nvkm_device *device = gr->base.engine.subdev.device; 59 nvkm_mask(device, 0x4188a4, 0x03000000, 0x03000000); 60} 61 62void 63gv100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) 64{ 65 struct nvkm_device *device = gr->base.engine.subdev.device; 66 int sm; 67 for (sm = 0; sm < 0x100; sm += 0x80) { 68 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x728 + sm), 0x0085eb64); 69 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x610), 0x00000001); 70 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x72c + sm), 0x00000004); 71 } 72} 73 74void 75gv100_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc) 76{ 77 struct nvkm_device *device = gr->base.engine.subdev.device; 78 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0x403f0000); 79} 80 81void 82gv100_gr_init_419bd8(struct gf100_gr *gr) 83{ 84 struct nvkm_device *device = gr->base.engine.subdev.device; 85 nvkm_mask(device, 0x419bd8, 0x00000700, 0x00000000); 86} 87 88static const struct gf100_gr_func 89gv100_gr = { 90 .oneinit_tiles = gm200_gr_oneinit_tiles, 91 .oneinit_sm_id = gm200_gr_oneinit_sm_id, 92 .init = gf100_gr_init, 93 .init_419bd8 = gv100_gr_init_419bd8, 94 .init_gpc_mmu = gm200_gr_init_gpc_mmu, 95 .init_vsc_stream_master = gk104_gr_init_vsc_stream_master, 96 .init_zcull = gf117_gr_init_zcull, 97 .init_num_active_ltcs = gm200_gr_init_num_active_ltcs, 98 .init_rop_active_fbps = gp100_gr_init_rop_active_fbps, 99 .init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask, 100 .init_fecs_exceptions = gp100_gr_init_fecs_exceptions, 101 .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2, 102 .init_sked_hww_esr = gk104_gr_init_sked_hww_esr, 103 .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, 104 .init_504430 = gv100_gr_init_504430, 105 .init_shader_exceptions = gv100_gr_init_shader_exceptions, 106 .init_4188a4 = gv100_gr_init_4188a4, 107 .trap_mp = gv100_gr_trap_mp, 108 .rops = gm200_gr_rops, 109 .gpc_nr = 6, 110 .tpc_nr = 5, 111 .ppc_nr = 3, 112 .grctx = &gv100_grctx, 113 .zbc = &gp102_gr_zbc, 114 .sclass = { 115 { -1, -1, FERMI_TWOD_A }, 116 { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, 117 { -1, -1, VOLTA_A, &gf100_fermi }, 118 { -1, -1, VOLTA_COMPUTE_A }, 119 {} 120 } 121}; 122 123MODULE_FIRMWARE("nvidia/gv100/gr/fecs_bl.bin"); 124MODULE_FIRMWARE("nvidia/gv100/gr/fecs_inst.bin"); 125MODULE_FIRMWARE("nvidia/gv100/gr/fecs_data.bin"); 126MODULE_FIRMWARE("nvidia/gv100/gr/fecs_sig.bin"); 127MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_bl.bin"); 128MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_inst.bin"); 129MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_data.bin"); 130MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_sig.bin"); 131MODULE_FIRMWARE("nvidia/gv100/gr/sw_ctx.bin"); 132MODULE_FIRMWARE("nvidia/gv100/gr/sw_nonctx.bin"); 133MODULE_FIRMWARE("nvidia/gv100/gr/sw_bundle_init.bin"); 134MODULE_FIRMWARE("nvidia/gv100/gr/sw_method_init.bin"); 135 136static const struct gf100_gr_fwif 137gv100_gr_fwif[] = { 138 { 0, gm200_gr_load, &gv100_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr }, 139 { -1, gm200_gr_nofw }, 140 {} 141}; 142 143int 144gv100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) 145{ 146 return gf100_gr_new_(gv100_gr_fwif, device, type, inst, pgr); 147}