cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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gm107.c (2180B)

      1/*
      2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
     20 * DEALINGS IN THE SOFTWARE.
     21 */
     22#include "priv.h"
     23
     24static const struct nvkm_falcon_func
     25gm107_nvdec_flcn = {
     26	.debug = 0xd00,
     27	.fbif = 0x600,
     28	.load_imem = nvkm_falcon_v1_load_imem,
     29	.load_dmem = nvkm_falcon_v1_load_dmem,
     30	.read_dmem = nvkm_falcon_v1_read_dmem,
     31	.bind_context = nvkm_falcon_v1_bind_context,
     32	.wait_for_halt = nvkm_falcon_v1_wait_for_halt,
     33	.clear_interrupt = nvkm_falcon_v1_clear_interrupt,
     34	.set_start_addr = nvkm_falcon_v1_set_start_addr,
     35	.start = nvkm_falcon_v1_start,
     36	.enable = nvkm_falcon_v1_enable,
     37	.disable = nvkm_falcon_v1_disable,
     38};
     39
     40static const struct nvkm_nvdec_func
     41gm107_nvdec = {
     42	.flcn = &gm107_nvdec_flcn,
     43};
     44
     45static int
     46gm107_nvdec_nofw(struct nvkm_nvdec *nvdec, int ver,
     47		 const struct nvkm_nvdec_fwif *fwif)
     48{
     49	return 0;
     50}
     51
     52static const struct nvkm_nvdec_fwif
     53gm107_nvdec_fwif[] = {
     54	{ -1, gm107_nvdec_nofw, &gm107_nvdec },
     55	{}
     56};
     57
     58int
     59gm107_nvdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
     60		struct nvkm_nvdec **pnvdec)
     61{
     62	return nvkm_nvdec_new_(gm107_nvdec_fwif, device, type, inst, pnvdec);
     63}