cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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regsnv04.h (1003B)


      1/* SPDX-License-Identifier: MIT */
      2#ifndef __NVKM_FB_REGS_04_H__
      3#define __NVKM_FB_REGS_04_H__
      4
      5#define NV04_PFB_BOOT_0						0x00100000
      6#	define NV04_PFB_BOOT_0_RAM_AMOUNT			0x00000003
      7#	define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB			0x00000000
      8#	define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB			0x00000001
      9#	define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB			0x00000002
     10#	define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB			0x00000003
     11#	define NV04_PFB_BOOT_0_RAM_WIDTH_128			0x00000004
     12#	define NV04_PFB_BOOT_0_RAM_TYPE				0x00000028
     13#	define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT		0x00000000
     14#	define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT		0x00000008
     15#	define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK	0x00000010
     16#	define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT		0x00000018
     17#	define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT		0x00000020
     18#	define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16		0x00000028
     19#	define NV04_PFB_BOOT_0_UMA_ENABLE			0x00000100
     20#	define NV04_PFB_BOOT_0_UMA_SIZE				0x0000f000
     21#define NV04_PFB_CFG0						0x00100200
     22
     23#endif