cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

sddr2.c (2735B)

      1/*
      2 * Copyright 2014 Roy Spliet
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: Roy Spliet <rspliet@eclipso.eu>
     23 *          Ben Skeggs
     24 */
     25#include "priv.h"
     26#include "ram.h"
     27
     28struct ramxlat {
     29	int id;
     30	u8 enc;
     31};
     32
     33static inline int
     34ramxlat(const struct ramxlat *xlat, int id)
     35{
     36	while (xlat->id >= 0) {
     37		if (xlat->id == id)
     38			return xlat->enc;
     39		xlat++;
     40	}
     41	return -EINVAL;
     42}
     43
     44static const struct ramxlat
     45ramddr2_cl[] = {
     46	{ 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 },
     47	/* The following are available in some, but not all DDR2 docs */
     48	{ 7, 7 },
     49	{ -1 }
     50};
     51
     52static const struct ramxlat
     53ramddr2_wr[] = {
     54	{ 2, 1 }, { 3, 2 }, { 4, 3 }, { 5, 4 }, { 6, 5 },
     55	/* The following are available in some, but not all DDR2 docs */
     56	{ 7, 6 },
     57	{ -1 }
     58};
     59
     60int
     61nvkm_sddr2_calc(struct nvkm_ram *ram)
     62{
     63	int CL, WR, DLL = 0, ODT = 0;
     64
     65	switch (ram->next->bios.timing_ver) {
     66	case 0x10:
     67		CL  = ram->next->bios.timing_10_CL;
     68		WR  = ram->next->bios.timing_10_WR;
     69		DLL = !ram->next->bios.ramcfg_DLLoff;
     70		ODT = ram->next->bios.timing_10_ODT & 3;
     71		break;
     72	case 0x20:
     73		CL  = (ram->next->bios.timing[1] & 0x0000001f);
     74		WR  = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
     75		break;
     76	default:
     77		return -ENOSYS;
     78	}
     79
     80	if (ram->next->bios.timing_ver == 0x20 ||
     81	    ram->next->bios.ramcfg_timing == 0xff) {
     82		ODT =  (ram->mr[1] & 0x004) >> 2 |
     83		       (ram->mr[1] & 0x040) >> 5;
     84	}
     85
     86	CL  = ramxlat(ramddr2_cl, CL);
     87	WR  = ramxlat(ramddr2_wr, WR);
     88	if (CL < 0 || WR < 0)
     89		return -EINVAL;
     90
     91	ram->mr[0] &= ~0xf70;
     92	ram->mr[0] |= (WR & 0x07) << 9;
     93	ram->mr[0] |= (CL & 0x07) << 4;
     94
     95	ram->mr[1] &= ~0x045;
     96	ram->mr[1] |= (ODT & 0x1) << 2;
     97	ram->mr[1] |= (ODT & 0x2) << 5;
     98	ram->mr[1] |= !DLL;
     99	return 0;
    100}