cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

g94.c (2643B)

      1/*
      2 * Copyright 2012 Red Hat Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: Ben Skeggs
     23 */
     24#include "priv.h"
     25
     26void
     27g94_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo)
     28{
     29	struct nvkm_device *device = gpio->subdev.device;
     30	u32 intr0 = nvkm_rd32(device, 0x00e054);
     31	u32 intr1 = nvkm_rd32(device, 0x00e074);
     32	u32 stat0 = nvkm_rd32(device, 0x00e050) & intr0;
     33	u32 stat1 = nvkm_rd32(device, 0x00e070) & intr1;
     34	*lo = (stat1 & 0xffff0000) | (stat0 >> 16);
     35	*hi = (stat1 << 16) | (stat0 & 0x0000ffff);
     36	nvkm_wr32(device, 0x00e054, intr0);
     37	nvkm_wr32(device, 0x00e074, intr1);
     38}
     39
     40void
     41g94_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)
     42{
     43	struct nvkm_device *device = gpio->subdev.device;
     44	u32 inte0 = nvkm_rd32(device, 0x00e050);
     45	u32 inte1 = nvkm_rd32(device, 0x00e070);
     46	if (type & NVKM_GPIO_LO)
     47		inte0 = (inte0 & ~(mask << 16)) | (data << 16);
     48	if (type & NVKM_GPIO_HI)
     49		inte0 = (inte0 & ~(mask & 0xffff)) | (data & 0xffff);
     50	mask >>= 16;
     51	data >>= 16;
     52	if (type & NVKM_GPIO_LO)
     53		inte1 = (inte1 & ~(mask << 16)) | (data << 16);
     54	if (type & NVKM_GPIO_HI)
     55		inte1 = (inte1 & ~mask) | data;
     56	nvkm_wr32(device, 0x00e050, inte0);
     57	nvkm_wr32(device, 0x00e070, inte1);
     58}
     59
     60static const struct nvkm_gpio_func
     61g94_gpio = {
     62	.lines = 32,
     63	.intr_stat = g94_gpio_intr_stat,
     64	.intr_mask = g94_gpio_intr_mask,
     65	.drive = nv50_gpio_drive,
     66	.sense = nv50_gpio_sense,
     67	.reset = nv50_gpio_reset,
     68};
     69
     70int
     71g94_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
     72	     struct nvkm_gpio **pgpio)
     73{
     74	return nvkm_gpio_new_(&g94_gpio, device, type, inst, pgpio);
     75}