cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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gt215.c (2544B)

      1/*
      2 * Copyright 2016 Red Hat Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: Ben Skeggs
     23 */
     24#include "priv.h"
     25
     26static const struct nvkm_mc_map
     27gt215_mc_reset[] = {
     28	{ 0x04008000, NVKM_ENGINE_MSVLD },
     29	{ 0x01020000, NVKM_ENGINE_MSPDEC },
     30	{ 0x00802000, NVKM_ENGINE_CE, 0 },
     31	{ 0x00400002, NVKM_ENGINE_MSPPP },
     32	{ 0x00201000, NVKM_ENGINE_GR },
     33	{ 0x00000100, NVKM_ENGINE_FIFO },
     34	{}
     35};
     36
     37static const struct nvkm_mc_map
     38gt215_mc_intr[] = {
     39	{ 0x04000000, NVKM_ENGINE_DISP },
     40	{ 0x00400000, NVKM_ENGINE_CE, 0 },
     41	{ 0x00020000, NVKM_ENGINE_MSPDEC },
     42	{ 0x00008000, NVKM_ENGINE_MSVLD },
     43	{ 0x00001000, NVKM_ENGINE_GR },
     44	{ 0x00000100, NVKM_ENGINE_FIFO },
     45	{ 0x00000001, NVKM_ENGINE_MSPPP },
     46	{ 0x00429101, NVKM_SUBDEV_FB },
     47	{ 0x10000000, NVKM_SUBDEV_BUS },
     48	{ 0x00200000, NVKM_SUBDEV_GPIO },
     49	{ 0x00200000, NVKM_SUBDEV_I2C },
     50	{ 0x00100000, NVKM_SUBDEV_TIMER },
     51	{ 0x00080000, NVKM_SUBDEV_THERM },
     52	{ 0x00040000, NVKM_SUBDEV_PMU },
     53	{},
     54};
     55
     56static void
     57gt215_mc_intr_mask(struct nvkm_mc *mc, u32 mask, u32 stat)
     58{
     59	nvkm_mask(mc->subdev.device, 0x000640, mask, stat);
     60}
     61
     62static const struct nvkm_mc_func
     63gt215_mc = {
     64	.init = nv50_mc_init,
     65	.intr = gt215_mc_intr,
     66	.intr_unarm = nv04_mc_intr_unarm,
     67	.intr_rearm = nv04_mc_intr_rearm,
     68	.intr_mask = gt215_mc_intr_mask,
     69	.intr_stat = nv04_mc_intr_stat,
     70	.reset = gt215_mc_reset,
     71};
     72
     73int
     74gt215_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
     75{
     76	return nvkm_mc_new_(&gt215_mc, device, type, inst, pmc);
     77}