cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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tu102.c (2002B)

      1/*
      2 * Copyright 2018 Red Hat Inc.
      3 * Copyright 2019 NVIDIA Corporation.
      4 *
      5 * Permission is hereby granted, free of charge, to any person obtaining a
      6 * copy of this software and associated documentation files (the "Software"),
      7 * to deal in the Software without restriction, including without limitation
      8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      9 * and/or sell copies of the Software, and to permit persons to whom the
     10 * Software is furnished to do so, subject to the following conditions:
     11 *
     12 * The above copyright notice and this permission notice shall be included in
     13 * all copies or substantial portions of the Software.
     14 *
     15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     21 * OTHER DEALINGS IN THE SOFTWARE.
     22 */
     23#include "mem.h"
     24#include "vmm.h"
     25
     26#include <core/option.h>
     27
     28#include <nvif/class.h>
     29
     30static const u8 *
     31tu102_mmu_kind(struct nvkm_mmu *mmu, int *count, u8 *invalid)
     32{
     33	static const u8
     34	kind[16] = {
     35		0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* 0x00 */
     36		0x06, 0x06, 0x02, 0x01, 0x03, 0x04, 0x05, 0x07,
     37	};
     38	*count = ARRAY_SIZE(kind);
     39	*invalid = 0x07;
     40	return kind;
     41}
     42
     43static const struct nvkm_mmu_func
     44tu102_mmu = {
     45	.dma_bits = 47,
     46	.mmu = {{ -1, -1, NVIF_CLASS_MMU_GF100}},
     47	.mem = {{ -1,  0, NVIF_CLASS_MEM_GF100}, gf100_mem_new, gf100_mem_map },
     48	.vmm = {{ -1,  0, NVIF_CLASS_VMM_GP100}, tu102_vmm_new },
     49	.kind = tu102_mmu_kind,
     50	.kind_sys = true,
     51};
     52
     53int
     54tu102_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
     55	      struct nvkm_mmu **pmmu)
     56{
     57	return nvkm_mmu_new_(&tu102_mmu, device, type, inst, pmmu);
     58}