cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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g92.c (1959B)


      1/*
      2 * Copyright 2015 Red Hat Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: Ben Skeggs <bskeggs@redhat.com>
     23 */
     24#include "priv.h"
     25
     26int
     27g92_pcie_version_supported(struct nvkm_pci *pci)
     28{
     29	if ((nvkm_pci_rd32(pci, 0x460) & 0x200) == 0x200)
     30		return 2;
     31	return 1;
     32}
     33
     34static const struct nvkm_pci_func
     35g92_pci_func = {
     36	.init = g84_pci_init,
     37	.rd32 = nv40_pci_rd32,
     38	.wr08 = nv40_pci_wr08,
     39	.wr32 = nv40_pci_wr32,
     40	.msi_rearm = nv46_pci_msi_rearm,
     41
     42	.pcie.init = g84_pcie_init,
     43	.pcie.set_link = g84_pcie_set_link,
     44
     45	.pcie.max_speed = g84_pcie_max_speed,
     46	.pcie.cur_speed = g84_pcie_cur_speed,
     47
     48	.pcie.set_version = g84_pcie_set_version,
     49	.pcie.version = g84_pcie_version,
     50	.pcie.version_supported = g92_pcie_version_supported,
     51};
     52
     53int
     54g92_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
     55	    struct nvkm_pci **ppci)
     56{
     57	return nvkm_pci_new_(&g92_pci_func, device, type, inst, ppci);
     58}