cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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priv.h (2044B)

      1/* SPDX-License-Identifier: MIT */
      2#ifndef __NVKM_PCI_PRIV_H__
      3#define __NVKM_PCI_PRIV_H__
      4#define nvkm_pci(p) container_of((p), struct nvkm_pci, subdev)
      5#include <subdev/pci.h>
      6
      7int nvkm_pci_new_(const struct nvkm_pci_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
      8		  struct nvkm_pci **);
      9
     10struct nvkm_pci_func {
     11	void (*init)(struct nvkm_pci *);
     12	u32 (*rd32)(struct nvkm_pci *, u16 addr);
     13	void (*wr08)(struct nvkm_pci *, u16 addr, u8 data);
     14	void (*wr32)(struct nvkm_pci *, u16 addr, u32 data);
     15	void (*msi_rearm)(struct nvkm_pci *);
     16
     17	struct {
     18		int (*init)(struct nvkm_pci *);
     19		int (*set_link)(struct nvkm_pci *, enum nvkm_pcie_speed, u8);
     20
     21		enum nvkm_pcie_speed (*max_speed)(struct nvkm_pci *);
     22		enum nvkm_pcie_speed (*cur_speed)(struct nvkm_pci *);
     23
     24		void (*set_version)(struct nvkm_pci *, u8);
     25		int (*version)(struct nvkm_pci *);
     26		int (*version_supported)(struct nvkm_pci *);
     27	} pcie;
     28};
     29
     30u32 nv40_pci_rd32(struct nvkm_pci *, u16);
     31void nv40_pci_wr08(struct nvkm_pci *, u16, u8);
     32void nv40_pci_wr32(struct nvkm_pci *, u16, u32);
     33void nv40_pci_msi_rearm(struct nvkm_pci *);
     34
     35void nv46_pci_msi_rearm(struct nvkm_pci *);
     36
     37void g84_pci_init(struct nvkm_pci *pci);
     38
     39/* pcie functions */
     40void g84_pcie_set_version(struct nvkm_pci *, u8);
     41int g84_pcie_version(struct nvkm_pci *);
     42void g84_pcie_set_link_speed(struct nvkm_pci *, enum nvkm_pcie_speed);
     43enum nvkm_pcie_speed g84_pcie_cur_speed(struct nvkm_pci *);
     44enum nvkm_pcie_speed g84_pcie_max_speed(struct nvkm_pci *);
     45int g84_pcie_init(struct nvkm_pci *);
     46int g84_pcie_set_link(struct nvkm_pci *, enum nvkm_pcie_speed, u8);
     47
     48int g92_pcie_version_supported(struct nvkm_pci *);
     49
     50void gf100_pcie_set_version(struct nvkm_pci *, u8);
     51int gf100_pcie_version(struct nvkm_pci *);
     52void gf100_pcie_set_cap_speed(struct nvkm_pci *, bool);
     53int gf100_pcie_cap_speed(struct nvkm_pci *);
     54int gf100_pcie_init(struct nvkm_pci *);
     55int gf100_pcie_set_link(struct nvkm_pci *, enum nvkm_pcie_speed, u8);
     56
     57int nvkm_pcie_oneinit(struct nvkm_pci *);
     58int nvkm_pcie_init(struct nvkm_pci *);
     59#endif