cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

gk20a.c (2664B)

      1/*
      2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
     20 * DEALINGS IN THE SOFTWARE.
     21 */
     22#include <subdev/privring.h>
     23#include <subdev/timer.h>
     24
     25static void
     26gk20a_privring_init_privring_ring(struct nvkm_subdev *privring)
     27{
     28	struct nvkm_device *device = privring->device;
     29	nvkm_mask(device, 0x137250, 0x3f, 0);
     30
     31	nvkm_mask(device, 0x000200, 0x20, 0);
     32	udelay(20);
     33	nvkm_mask(device, 0x000200, 0x20, 0x20);
     34
     35	nvkm_wr32(device, 0x12004c, 0x4);
     36	nvkm_wr32(device, 0x122204, 0x2);
     37	nvkm_rd32(device, 0x122204);
     38
     39	/*
     40	 * Bug: increase clock timeout to avoid operation failure at high
     41	 * gpcclk rate.
     42	 */
     43	nvkm_wr32(device, 0x122354, 0x800);
     44	nvkm_wr32(device, 0x128328, 0x800);
     45	nvkm_wr32(device, 0x124320, 0x800);
     46}
     47
     48static void
     49gk20a_privring_intr(struct nvkm_subdev *privring)
     50{
     51	struct nvkm_device *device = privring->device;
     52	u32 status0 = nvkm_rd32(device, 0x120058);
     53
     54	if (status0 & 0x7) {
     55		nvkm_debug(privring, "resetting privring ring\n");
     56		gk20a_privring_init_privring_ring(privring);
     57	}
     58
     59	/* Acknowledge interrupt */
     60	nvkm_mask(device, 0x12004c, 0x2, 0x2);
     61	nvkm_msec(device, 2000,
     62		if (!(nvkm_rd32(device, 0x12004c) & 0x0000003f))
     63			break;
     64	);
     65}
     66
     67static int
     68gk20a_privring_init(struct nvkm_subdev *privring)
     69{
     70	gk20a_privring_init_privring_ring(privring);
     71	return 0;
     72}
     73
     74static const struct nvkm_subdev_func
     75gk20a_privring = {
     76	.init = gk20a_privring_init,
     77	.intr = gk20a_privring_intr,
     78};
     79
     80int
     81gk20a_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
     82		   struct nvkm_subdev **pprivring)
     83{
     84	return nvkm_subdev_new_(&gk20a_privring, device, type, inst, pprivring);
     85}