btcd.h (8140B)
1/* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24#ifndef _BTCD_H_ 25#define _BTCD_H_ 26 27/* pm registers */ 28 29#define GENERAL_PWRMGT 0x63c 30# define GLOBAL_PWRMGT_EN (1 << 0) 31# define STATIC_PM_EN (1 << 1) 32# define THERMAL_PROTECTION_DIS (1 << 2) 33# define THERMAL_PROTECTION_TYPE (1 << 3) 34# define ENABLE_GEN2PCIE (1 << 4) 35# define ENABLE_GEN2XSP (1 << 5) 36# define SW_SMIO_INDEX(x) ((x) << 6) 37# define SW_SMIO_INDEX_MASK (3 << 6) 38# define SW_SMIO_INDEX_SHIFT 6 39# define LOW_VOLT_D2_ACPI (1 << 8) 40# define LOW_VOLT_D3_ACPI (1 << 9) 41# define VOLT_PWRMGT_EN (1 << 10) 42# define BACKBIAS_PAD_EN (1 << 18) 43# define BACKBIAS_VALUE (1 << 19) 44# define DYN_SPREAD_SPECTRUM_EN (1 << 23) 45# define AC_DC_SW (1 << 24) 46 47#define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c 48# define CURRENT_PROFILE_INDEX_MASK (0xf << 4) 49# define CURRENT_PROFILE_INDEX_SHIFT 4 50 51#define CG_BIF_REQ_AND_RSP 0x7f4 52#define CG_CLIENT_REQ(x) ((x) << 0) 53#define CG_CLIENT_REQ_MASK (0xff << 0) 54#define CG_CLIENT_REQ_SHIFT 0 55#define CG_CLIENT_RESP(x) ((x) << 8) 56#define CG_CLIENT_RESP_MASK (0xff << 8) 57#define CG_CLIENT_RESP_SHIFT 8 58#define CLIENT_CG_REQ(x) ((x) << 16) 59#define CLIENT_CG_REQ_MASK (0xff << 16) 60#define CLIENT_CG_REQ_SHIFT 16 61#define CLIENT_CG_RESP(x) ((x) << 24) 62#define CLIENT_CG_RESP_MASK (0xff << 24) 63#define CLIENT_CG_RESP_SHIFT 24 64 65#define SCLK_PSKIP_CNTL 0x8c0 66#define PSKIP_ON_ALLOW_STOP_HI(x) ((x) << 16) 67#define PSKIP_ON_ALLOW_STOP_HI_MASK (0xff << 16) 68#define PSKIP_ON_ALLOW_STOP_HI_SHIFT 16 69 70#define CG_ULV_CONTROL 0x8c8 71#define CG_ULV_PARAMETER 0x8cc 72 73#define MC_ARB_DRAM_TIMING 0x2774 74#define MC_ARB_DRAM_TIMING2 0x2778 75 76#define MC_ARB_RFSH_RATE 0x27b0 77#define POWERMODE0(x) ((x) << 0) 78#define POWERMODE0_MASK (0xff << 0) 79#define POWERMODE0_SHIFT 0 80#define POWERMODE1(x) ((x) << 8) 81#define POWERMODE1_MASK (0xff << 8) 82#define POWERMODE1_SHIFT 8 83#define POWERMODE2(x) ((x) << 16) 84#define POWERMODE2_MASK (0xff << 16) 85#define POWERMODE2_SHIFT 16 86#define POWERMODE3(x) ((x) << 24) 87#define POWERMODE3_MASK (0xff << 24) 88#define POWERMODE3_SHIFT 24 89 90#define MC_ARB_BURST_TIME 0x2808 91#define STATE0(x) ((x) << 0) 92#define STATE0_MASK (0x1f << 0) 93#define STATE0_SHIFT 0 94#define STATE1(x) ((x) << 5) 95#define STATE1_MASK (0x1f << 5) 96#define STATE1_SHIFT 5 97#define STATE2(x) ((x) << 10) 98#define STATE2_MASK (0x1f << 10) 99#define STATE2_SHIFT 10 100#define STATE3(x) ((x) << 15) 101#define STATE3_MASK (0x1f << 15) 102#define STATE3_SHIFT 15 103 104#define MC_SEQ_RAS_TIMING 0x28a0 105#define MC_SEQ_CAS_TIMING 0x28a4 106#define MC_SEQ_MISC_TIMING 0x28a8 107#define MC_SEQ_MISC_TIMING2 0x28ac 108 109#define MC_SEQ_RD_CTL_D0 0x28b4 110#define MC_SEQ_RD_CTL_D1 0x28b8 111#define MC_SEQ_WR_CTL_D0 0x28bc 112#define MC_SEQ_WR_CTL_D1 0x28c0 113 114#define MC_PMG_AUTO_CFG 0x28d4 115 116#define MC_SEQ_STATUS_M 0x29f4 117# define PMG_PWRSTATE (1 << 16) 118 119#define MC_SEQ_MISC0 0x2a00 120#define MC_SEQ_MISC0_GDDR5_SHIFT 28 121#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 122#define MC_SEQ_MISC0_GDDR5_VALUE 5 123#define MC_SEQ_MISC1 0x2a04 124#define MC_SEQ_RESERVE_M 0x2a08 125#define MC_PMG_CMD_EMRS 0x2a0c 126 127#define MC_SEQ_MISC3 0x2a2c 128 129#define MC_SEQ_MISC5 0x2a54 130#define MC_SEQ_MISC6 0x2a58 131 132#define MC_SEQ_MISC7 0x2a64 133 134#define MC_SEQ_CG 0x2a68 135#define CG_SEQ_REQ(x) ((x) << 0) 136#define CG_SEQ_REQ_MASK (0xff << 0) 137#define CG_SEQ_REQ_SHIFT 0 138#define CG_SEQ_RESP(x) ((x) << 8) 139#define CG_SEQ_RESP_MASK (0xff << 8) 140#define CG_SEQ_RESP_SHIFT 8 141#define SEQ_CG_REQ(x) ((x) << 16) 142#define SEQ_CG_REQ_MASK (0xff << 16) 143#define SEQ_CG_REQ_SHIFT 16 144#define SEQ_CG_RESP(x) ((x) << 24) 145#define SEQ_CG_RESP_MASK (0xff << 24) 146#define SEQ_CG_RESP_SHIFT 24 147#define MC_SEQ_RAS_TIMING_LP 0x2a6c 148#define MC_SEQ_CAS_TIMING_LP 0x2a70 149#define MC_SEQ_MISC_TIMING_LP 0x2a74 150#define MC_SEQ_MISC_TIMING2_LP 0x2a78 151#define MC_SEQ_WR_CTL_D0_LP 0x2a7c 152#define MC_SEQ_WR_CTL_D1_LP 0x2a80 153#define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 154#define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 155 156#define MC_PMG_CMD_MRS 0x2aac 157 158#define MC_SEQ_RD_CTL_D0_LP 0x2b1c 159#define MC_SEQ_RD_CTL_D1_LP 0x2b20 160 161#define MC_PMG_CMD_MRS1 0x2b44 162#define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 163 164#define LB_SYNC_RESET_SEL 0x6b28 165#define LB_SYNC_RESET_SEL_MASK (3 << 0) 166#define LB_SYNC_RESET_SEL_SHIFT 0 167 168/* PCIE link stuff */ 169#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 170# define LC_GEN2_EN_STRAP (1 << 0) 171# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 172# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 173# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 174# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 175# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 176# define LC_CURRENT_DATA_RATE (1 << 11) 177# define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) 178# define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) 179# define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 180# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 181# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 182# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 183# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 184 185#endif