cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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evergreen_blit_shaders.h (7216B)


      1/*
      2 * Copyright 2009 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice (including the next
     12 * paragraph) shall be included in all copies or substantial portions of the
     13 * Software.
     14 *
     15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
     19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
     21 * DEALINGS IN THE SOFTWARE.
     22 *
     23 * Authors:
     24 *     Alex Deucher <alexander.deucher@amd.com>
     25 */
     26
     27#ifndef EVERGREEN_BLIT_SHADERS_H
     28#define EVERGREEN_BLIT_SHADERS_H
     29
     30/*
     31 * evergreen cards need to use the 3D engine to blit data which requires
     32 * quite a bit of hw state setup.  Rather than pull the whole 3D driver
     33 * (which normally generates the 3D state) into the DRM, we opt to use
     34 * statically generated state tables.  The register state and shaders
     35 * were hand generated to support blitting functionality.  See the 3D
     36 * driver or documentation for descriptions of the registers and
     37 * shader instructions.
     38 */
     39
     40static const u32 evergreen_default_state[] = {
     41	0xc0016900,
     42	0x0000023b,
     43	0x00000000, /* SQ_LDS_ALLOC_PS */
     44
     45	0xc0066900,
     46	0x00000240,
     47	0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
     48	0x00000000,
     49	0x00000000,
     50	0x00000000,
     51	0x00000000,
     52	0x00000000,
     53
     54	0xc0046900,
     55	0x00000247,
     56	0x00000000, /* SQ_GS_VERT_ITEMSIZE */
     57	0x00000000,
     58	0x00000000,
     59	0x00000000,
     60
     61	0xc0026900,
     62	0x00000010,
     63	0x00000000, /* DB_Z_INFO */
     64	0x00000000, /* DB_STENCIL_INFO */
     65
     66	0xc0016900,
     67	0x00000200,
     68	0x00000000, /* DB_DEPTH_CONTROL */
     69
     70	0xc0066900,
     71	0x00000000,
     72	0x00000060, /* DB_RENDER_CONTROL */
     73	0x00000000, /* DB_COUNT_CONTROL */
     74	0x00000000, /* DB_DEPTH_VIEW */
     75	0x0000002a, /* DB_RENDER_OVERRIDE */
     76	0x00000000, /* DB_RENDER_OVERRIDE2 */
     77	0x00000000, /* DB_HTILE_DATA_BASE */
     78
     79	0xc0026900,
     80	0x0000000a,
     81	0x00000000, /* DB_STENCIL_CLEAR */
     82	0x00000000, /* DB_DEPTH_CLEAR */
     83
     84	0xc0016900,
     85	0x000002dc,
     86	0x0000aa00, /* DB_ALPHA_TO_MASK */
     87
     88	0xc0016900,
     89	0x00000080,
     90	0x00000000, /* PA_SC_WINDOW_OFFSET */
     91
     92	0xc00d6900,
     93	0x00000083,
     94	0x0000ffff, /* PA_SC_CLIPRECT_RULE */
     95	0x00000000, /* PA_SC_CLIPRECT_0_TL */
     96	0x20002000, /* PA_SC_CLIPRECT_0_BR */
     97	0x00000000,
     98	0x20002000,
     99	0x00000000,
    100	0x20002000,
    101	0x00000000,
    102	0x20002000,
    103	0xaaaaaaaa, /* PA_SC_EDGERULE */
    104	0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
    105	0x0000000f, /* CB_TARGET_MASK */
    106	0x0000000f, /* CB_SHADER_MASK */
    107
    108	0xc0226900,
    109	0x00000094,
    110	0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
    111	0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
    112	0x80000000,
    113	0x20002000,
    114	0x80000000,
    115	0x20002000,
    116	0x80000000,
    117	0x20002000,
    118	0x80000000,
    119	0x20002000,
    120	0x80000000,
    121	0x20002000,
    122	0x80000000,
    123	0x20002000,
    124	0x80000000,
    125	0x20002000,
    126	0x80000000,
    127	0x20002000,
    128	0x80000000,
    129	0x20002000,
    130	0x80000000,
    131	0x20002000,
    132	0x80000000,
    133	0x20002000,
    134	0x80000000,
    135	0x20002000,
    136	0x80000000,
    137	0x20002000,
    138	0x80000000,
    139	0x20002000,
    140	0x80000000,
    141	0x20002000,
    142	0x00000000, /* PA_SC_VPORT_ZMIN_0 */
    143	0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
    144
    145	0xc0016900,
    146	0x000000d4,
    147	0x00000000, /* SX_MISC */
    148
    149	0xc0026900,
    150	0x00000292,
    151	0x00000000, /* PA_SC_MODE_CNTL_0 */
    152	0x00000000, /* PA_SC_MODE_CNTL_1 */
    153
    154	0xc0106900,
    155	0x00000300,
    156	0x00000000, /* PA_SC_LINE_CNTL */
    157	0x00000000, /* PA_SC_AA_CONFIG */
    158	0x00000005, /* PA_SU_VTX_CNTL */
    159	0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
    160	0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
    161	0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
    162	0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
    163	0x00000000, /* PA_SC_AA_SAMPLE_LOCS_0 */
    164	0x00000000, /*  */
    165	0x00000000, /*  */
    166	0x00000000, /*  */
    167	0x00000000, /*  */
    168	0x00000000, /*  */
    169	0x00000000, /*  */
    170	0x00000000, /* PA_SC_AA_SAMPLE_LOCS_7 */
    171	0xffffffff, /* PA_SC_AA_MASK */
    172
    173	0xc00d6900,
    174	0x00000202,
    175	0x00cc0010, /* CB_COLOR_CONTROL */
    176	0x00000210, /* DB_SHADER_CONTROL */
    177	0x00010000, /* PA_CL_CLIP_CNTL */
    178	0x00000004, /* PA_SU_SC_MODE_CNTL */
    179	0x00000100, /* PA_CL_VTE_CNTL */
    180	0x00000000, /* PA_CL_VS_OUT_CNTL */
    181	0x00000000, /* PA_CL_NANINF_CNTL */
    182	0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
    183	0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
    184	0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
    185	0x00000000, /*  */
    186	0x00000000, /*  */
    187	0x00000000, /* SQ_DYN_GPR_RESOURCE_LIMIT_1 */
    188
    189	0xc0066900,
    190	0x000002de,
    191	0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
    192	0x00000000, /*  */
    193	0x00000000, /*  */
    194	0x00000000, /*  */
    195	0x00000000, /*  */
    196	0x00000000, /*  */
    197
    198	0xc0016900,
    199	0x00000229,
    200	0x00000000, /* SQ_PGM_START_FS */
    201
    202	0xc0016900,
    203	0x0000022a,
    204	0x00000000, /* SQ_PGM_RESOURCES_FS */
    205
    206	0xc0096900,
    207	0x00000100,
    208	0x00ffffff, /* VGT_MAX_VTX_INDX */
    209	0x00000000, /*  */
    210	0x00000000, /*  */
    211	0x00000000, /*  */
    212	0x00000000, /* SX_ALPHA_TEST_CONTROL */
    213	0x00000000, /* CB_BLEND_RED */
    214	0x00000000, /* CB_BLEND_GREEN */
    215	0x00000000, /* CB_BLEND_BLUE */
    216	0x00000000, /* CB_BLEND_ALPHA */
    217
    218	0xc0026900,
    219	0x000002a8,
    220	0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
    221	0x00000000, /*  */
    222
    223	0xc0026900,
    224	0x000002ad,
    225	0x00000000, /* VGT_REUSE_OFF */
    226	0x00000000, /*  */
    227
    228	0xc0116900,
    229	0x00000280,
    230	0x00000000, /* PA_SU_POINT_SIZE */
    231	0x00000000, /* PA_SU_POINT_MINMAX */
    232	0x00000008, /* PA_SU_LINE_CNTL */
    233	0x00000000, /* PA_SC_LINE_STIPPLE */
    234	0x00000000, /* VGT_OUTPUT_PATH_CNTL */
    235	0x00000000, /* VGT_HOS_CNTL */
    236	0x00000000, /*  */
    237	0x00000000, /*  */
    238	0x00000000, /*  */
    239	0x00000000, /*  */
    240	0x00000000, /*  */
    241	0x00000000, /*  */
    242	0x00000000, /*  */
    243	0x00000000, /*  */
    244	0x00000000, /*  */
    245	0x00000000, /*  */
    246	0x00000000, /* VGT_GS_MODE */
    247
    248	0xc0016900,
    249	0x000002a1,
    250	0x00000000, /* VGT_PRIMITIVEID_EN */
    251
    252	0xc0016900,
    253	0x000002a5,
    254	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
    255
    256	0xc0016900,
    257	0x000002d5,
    258	0x00000000, /* VGT_SHADER_STAGES_EN */
    259
    260	0xc0026900,
    261	0x000002e5,
    262	0x00000000, /* VGT_STRMOUT_CONFIG */
    263	0x00000000, /*  */
    264
    265	0xc0016900,
    266	0x000001e0,
    267	0x00000000, /* CB_BLEND0_CONTROL */
    268
    269	0xc0016900,
    270	0x000001b1,
    271	0x00000000, /* SPI_VS_OUT_CONFIG */
    272
    273	0xc0016900,
    274	0x00000187,
    275	0x00000000, /* SPI_VS_OUT_ID_0 */
    276
    277	0xc0016900,
    278	0x00000191,
    279	0x00000100, /* SPI_PS_INPUT_CNTL_0 */
    280
    281	0xc00b6900,
    282	0x000001b3,
    283	0x20000001, /* SPI_PS_IN_CONTROL_0 */
    284	0x00000000, /* SPI_PS_IN_CONTROL_1 */
    285	0x00000000, /* SPI_INTERP_CONTROL_0 */
    286	0x00000000, /* SPI_INPUT_Z */
    287	0x00000000, /* SPI_FOG_CNTL */
    288	0x00100000, /* SPI_BARYC_CNTL */
    289	0x00000000, /* SPI_PS_IN_CONTROL_2 */
    290	0x00000000, /*  */
    291	0x00000000, /*  */
    292	0x00000000, /*  */
    293	0x00000000, /*  */
    294
    295	0xc0026900,
    296	0x00000316,
    297	0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
    298	0x00000010, /*  */
    299};
    300
    301static const u32 evergreen_default_size = ARRAY_SIZE(evergreen_default_state);
    302
    303#endif