evergreen_reg.h (17399B)
1/* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24#ifndef __EVERGREEN_REG_H__ 25#define __EVERGREEN_REG_H__ 26 27/* trinity */ 28#define TN_SMC_IND_INDEX_0 0x200 29#define TN_SMC_IND_DATA_0 0x204 30 31/* evergreen */ 32#define EVERGREEN_PIF_PHY0_INDEX 0x8 33#define EVERGREEN_PIF_PHY0_DATA 0xc 34#define EVERGREEN_PIF_PHY1_INDEX 0x10 35#define EVERGREEN_PIF_PHY1_DATA 0x14 36#define EVERGREEN_MM_INDEX_HI 0x18 37 38#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310 39#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324 40#define EVERGREEN_D3VGA_CONTROL 0x3e0 41#define EVERGREEN_D4VGA_CONTROL 0x3e4 42#define EVERGREEN_D5VGA_CONTROL 0x3e8 43#define EVERGREEN_D6VGA_CONTROL 0x3ec 44 45#define EVERGREEN_P1PLL_SS_CNTL 0x414 46#define EVERGREEN_P2PLL_SS_CNTL 0x454 47# define EVERGREEN_PxPLL_SS_EN (1 << 12) 48 49#define EVERGREEN_AUDIO_PLL1_MUL 0x5b0 50#define EVERGREEN_AUDIO_PLL1_DIV 0x5b4 51#define EVERGREEN_AUDIO_PLL1_UNK 0x5bc 52 53#define EVERGREEN_CG_IND_ADDR 0x8f8 54#define EVERGREEN_CG_IND_DATA 0x8fc 55 56#define EVERGREEN_AUDIO_ENABLE 0x5e78 57#define EVERGREEN_AUDIO_VENDOR_ID 0x5ec0 58 59/* GRPH blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */ 60#define EVERGREEN_GRPH_ENABLE 0x6800 61#define EVERGREEN_GRPH_CONTROL 0x6804 62# define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0) 63# define EVERGREEN_GRPH_DEPTH_8BPP 0 64# define EVERGREEN_GRPH_DEPTH_16BPP 1 65# define EVERGREEN_GRPH_DEPTH_32BPP 2 66# define EVERGREEN_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) 67# define EVERGREEN_ADDR_SURF_2_BANK 0 68# define EVERGREEN_ADDR_SURF_4_BANK 1 69# define EVERGREEN_ADDR_SURF_8_BANK 2 70# define EVERGREEN_ADDR_SURF_16_BANK 3 71# define EVERGREEN_GRPH_Z(x) (((x) & 0x3) << 4) 72# define EVERGREEN_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) 73# define EVERGREEN_ADDR_SURF_BANK_WIDTH_1 0 74# define EVERGREEN_ADDR_SURF_BANK_WIDTH_2 1 75# define EVERGREEN_ADDR_SURF_BANK_WIDTH_4 2 76# define EVERGREEN_ADDR_SURF_BANK_WIDTH_8 3 77# define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8) 78/* 8 BPP */ 79# define EVERGREEN_GRPH_FORMAT_INDEXED 0 80/* 16 BPP */ 81# define EVERGREEN_GRPH_FORMAT_ARGB1555 0 82# define EVERGREEN_GRPH_FORMAT_ARGB565 1 83# define EVERGREEN_GRPH_FORMAT_ARGB4444 2 84# define EVERGREEN_GRPH_FORMAT_AI88 3 85# define EVERGREEN_GRPH_FORMAT_MONO16 4 86# define EVERGREEN_GRPH_FORMAT_BGRA5551 5 87/* 32 BPP */ 88# define EVERGREEN_GRPH_FORMAT_ARGB8888 0 89# define EVERGREEN_GRPH_FORMAT_ARGB2101010 1 90# define EVERGREEN_GRPH_FORMAT_32BPP_DIG 2 91# define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010 3 92# define EVERGREEN_GRPH_FORMAT_BGRA1010102 4 93# define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5 94# define EVERGREEN_GRPH_FORMAT_RGB111110 6 95# define EVERGREEN_GRPH_FORMAT_BGR101111 7 96# define EVERGREEN_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) 97# define EVERGREEN_ADDR_SURF_BANK_HEIGHT_1 0 98# define EVERGREEN_ADDR_SURF_BANK_HEIGHT_2 1 99# define EVERGREEN_ADDR_SURF_BANK_HEIGHT_4 2 100# define EVERGREEN_ADDR_SURF_BANK_HEIGHT_8 3 101# define EVERGREEN_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13) 102# define EVERGREEN_ADDR_SURF_TILE_SPLIT_64B 0 103# define EVERGREEN_ADDR_SURF_TILE_SPLIT_128B 1 104# define EVERGREEN_ADDR_SURF_TILE_SPLIT_256B 2 105# define EVERGREEN_ADDR_SURF_TILE_SPLIT_512B 3 106# define EVERGREEN_ADDR_SURF_TILE_SPLIT_1KB 4 107# define EVERGREEN_ADDR_SURF_TILE_SPLIT_2KB 5 108# define EVERGREEN_ADDR_SURF_TILE_SPLIT_4KB 6 109# define EVERGREEN_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18) 110# define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1 0 111# define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2 1 112# define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4 2 113# define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8 3 114# define EVERGREEN_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) 115# define EVERGREEN_GRPH_ARRAY_LINEAR_GENERAL 0 116# define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED 1 117# define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1 2 118# define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1 4 119#define EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL 0x6808 120# define EVERGREEN_LUT_10BIT_BYPASS_EN (1 << 8) 121#define EVERGREEN_GRPH_SWAP_CONTROL 0x680c 122# define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) 123# define EVERGREEN_GRPH_ENDIAN_NONE 0 124# define EVERGREEN_GRPH_ENDIAN_8IN16 1 125# define EVERGREEN_GRPH_ENDIAN_8IN32 2 126# define EVERGREEN_GRPH_ENDIAN_8IN64 3 127# define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) 128# define EVERGREEN_GRPH_RED_SEL_R 0 129# define EVERGREEN_GRPH_RED_SEL_G 1 130# define EVERGREEN_GRPH_RED_SEL_B 2 131# define EVERGREEN_GRPH_RED_SEL_A 3 132# define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) 133# define EVERGREEN_GRPH_GREEN_SEL_G 0 134# define EVERGREEN_GRPH_GREEN_SEL_B 1 135# define EVERGREEN_GRPH_GREEN_SEL_A 2 136# define EVERGREEN_GRPH_GREEN_SEL_R 3 137# define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) 138# define EVERGREEN_GRPH_BLUE_SEL_B 0 139# define EVERGREEN_GRPH_BLUE_SEL_A 1 140# define EVERGREEN_GRPH_BLUE_SEL_R 2 141# define EVERGREEN_GRPH_BLUE_SEL_G 3 142# define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) 143# define EVERGREEN_GRPH_ALPHA_SEL_A 0 144# define EVERGREEN_GRPH_ALPHA_SEL_R 1 145# define EVERGREEN_GRPH_ALPHA_SEL_G 2 146# define EVERGREEN_GRPH_ALPHA_SEL_B 3 147#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x6810 148#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x6814 149# define EVERGREEN_GRPH_DFQ_ENABLE (1 << 0) 150# define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK 0xffffff00 151#define EVERGREEN_GRPH_PITCH 0x6818 152#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x681c 153#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x6820 154#define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x6824 155#define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x6828 156#define EVERGREEN_GRPH_X_START 0x682c 157#define EVERGREEN_GRPH_Y_START 0x6830 158#define EVERGREEN_GRPH_X_END 0x6834 159#define EVERGREEN_GRPH_Y_END 0x6838 160#define EVERGREEN_GRPH_UPDATE 0x6844 161# define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2) 162# define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16) 163#define EVERGREEN_GRPH_FLIP_CONTROL 0x6848 164# define EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0) 165 166/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ 167#define EVERGREEN_CUR_CONTROL 0x6998 168# define EVERGREEN_CURSOR_EN (1 << 0) 169# define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8) 170# define EVERGREEN_CURSOR_MONO 0 171# define EVERGREEN_CURSOR_24_1 1 172# define EVERGREEN_CURSOR_24_8_PRE_MULT 2 173# define EVERGREEN_CURSOR_24_8_UNPRE_MULT 3 174# define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16) 175# define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20) 176# define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) 177# define EVERGREEN_CURSOR_URGENT_ALWAYS 0 178# define EVERGREEN_CURSOR_URGENT_1_8 1 179# define EVERGREEN_CURSOR_URGENT_1_4 2 180# define EVERGREEN_CURSOR_URGENT_3_8 3 181# define EVERGREEN_CURSOR_URGENT_1_2 4 182#define EVERGREEN_CUR_SURFACE_ADDRESS 0x699c 183# define EVERGREEN_CUR_SURFACE_ADDRESS_MASK 0xfffff000 184#define EVERGREEN_CUR_SIZE 0x69a0 185#define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x69a4 186#define EVERGREEN_CUR_POSITION 0x69a8 187#define EVERGREEN_CUR_HOT_SPOT 0x69ac 188#define EVERGREEN_CUR_COLOR1 0x69b0 189#define EVERGREEN_CUR_COLOR2 0x69b4 190#define EVERGREEN_CUR_UPDATE 0x69b8 191# define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0) 192# define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1) 193# define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16) 194# define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) 195 196/* LUT blocks at 0x69e0, 0x75e0, 0x101e0, 0x10de0, 0x119e0, 0x125e0 */ 197#define EVERGREEN_DC_LUT_RW_MODE 0x69e0 198#define EVERGREEN_DC_LUT_RW_INDEX 0x69e4 199#define EVERGREEN_DC_LUT_SEQ_COLOR 0x69e8 200#define EVERGREEN_DC_LUT_PWL_DATA 0x69ec 201#define EVERGREEN_DC_LUT_30_COLOR 0x69f0 202#define EVERGREEN_DC_LUT_VGA_ACCESS_ENABLE 0x69f4 203#define EVERGREEN_DC_LUT_WRITE_EN_MASK 0x69f8 204#define EVERGREEN_DC_LUT_AUTOFILL 0x69fc 205#define EVERGREEN_DC_LUT_CONTROL 0x6a00 206#define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE 0x6a04 207#define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN 0x6a08 208#define EVERGREEN_DC_LUT_BLACK_OFFSET_RED 0x6a0c 209#define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE 0x6a10 210#define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN 0x6a14 211#define EVERGREEN_DC_LUT_WHITE_OFFSET_RED 0x6a18 212 213#define EVERGREEN_DATA_FORMAT 0x6b00 214# define EVERGREEN_INTERLEAVE_EN (1 << 0) 215#define EVERGREEN_DESKTOP_HEIGHT 0x6b04 216#define EVERGREEN_VLINE_START_END 0x6b08 217#define EVERGREEN_VLINE_STATUS 0x6bb8 218# define EVERGREEN_VLINE_STAT (1 << 12) 219 220#define EVERGREEN_VIEWPORT_START 0x6d70 221#define EVERGREEN_VIEWPORT_SIZE 0x6d74 222 223/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ 224#define EVERGREEN_CRTC0_REGISTER_OFFSET (0x6df0 - 0x6df0) 225#define EVERGREEN_CRTC1_REGISTER_OFFSET (0x79f0 - 0x6df0) 226#define EVERGREEN_CRTC2_REGISTER_OFFSET (0x105f0 - 0x6df0) 227#define EVERGREEN_CRTC3_REGISTER_OFFSET (0x111f0 - 0x6df0) 228#define EVERGREEN_CRTC4_REGISTER_OFFSET (0x11df0 - 0x6df0) 229#define EVERGREEN_CRTC5_REGISTER_OFFSET (0x129f0 - 0x6df0) 230 231/* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */ 232#define EVERGREEN_CRTC_V_BLANK_START_END 0x6e34 233#define EVERGREEN_CRTC_CONTROL 0x6e70 234# define EVERGREEN_CRTC_MASTER_EN (1 << 0) 235# define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24) 236#define EVERGREEN_CRTC_BLANK_CONTROL 0x6e74 237# define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8) 238#define EVERGREEN_CRTC_STATUS 0x6e8c 239# define EVERGREEN_CRTC_V_BLANK (1 << 0) 240#define EVERGREEN_CRTC_STATUS_POSITION 0x6e90 241#define EVERGREEN_CRTC_STATUS_HV_COUNT 0x6ea0 242#define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4 243#define EVERGREEN_MASTER_UPDATE_LOCK 0x6ef4 244#define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8 245 246#define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0 247#define EVERGREEN_DC_GPIO_HPD_A 0x64b4 248#define EVERGREEN_DC_GPIO_HPD_EN 0x64b8 249#define EVERGREEN_DC_GPIO_HPD_Y 0x64bc 250 251/* HDMI blocks at 0x7030, 0x7c30, 0x10830, 0x11430, 0x12030, 0x12c30 */ 252#define EVERGREEN_HDMI_BASE 0x7030 253/*DIG block*/ 254#define NI_DIG0_REGISTER_OFFSET (0x7000 - 0x7000) 255#define NI_DIG1_REGISTER_OFFSET (0x7C00 - 0x7000) 256#define NI_DIG2_REGISTER_OFFSET (0x10800 - 0x7000) 257#define NI_DIG3_REGISTER_OFFSET (0x11400 - 0x7000) 258#define NI_DIG4_REGISTER_OFFSET (0x12000 - 0x7000) 259#define NI_DIG5_REGISTER_OFFSET (0x12C00 - 0x7000) 260 261 262#define NI_DIG_FE_CNTL 0x7000 263# define NI_DIG_FE_CNTL_SOURCE_SELECT(x) ((x) & 0x3) 264# define NI_DIG_FE_CNTL_SYMCLK_FE_ON (1<<24) 265 266 267#define NI_DIG_BE_CNTL 0x7140 268# define NI_DIG_BE_CNTL_FE_SOURCE_SELECT(x) (((x) >> 8 ) & 0x3F) 269# define NI_DIG_FE_CNTL_MODE(x) (((x) >> 16) & 0x7 ) 270 271#define NI_DIG_BE_EN_CNTL 0x7144 272# define NI_DIG_BE_EN_CNTL_ENABLE (1 << 0) 273# define NI_DIG_BE_EN_CNTL_SYMBCLK_ON (1 << 8) 274# define NI_DIG_BE_DPSST 0 275 276/* Display Port block */ 277#define EVERGREEN_DP0_REGISTER_OFFSET (0x730C - 0x730C) 278#define EVERGREEN_DP1_REGISTER_OFFSET (0x7F0C - 0x730C) 279#define EVERGREEN_DP2_REGISTER_OFFSET (0x10B0C - 0x730C) 280#define EVERGREEN_DP3_REGISTER_OFFSET (0x1170C - 0x730C) 281#define EVERGREEN_DP4_REGISTER_OFFSET (0x1230C - 0x730C) 282#define EVERGREEN_DP5_REGISTER_OFFSET (0x12F0C - 0x730C) 283 284 285#define EVERGREEN_DP_VID_STREAM_CNTL 0x730C 286# define EVERGREEN_DP_VID_STREAM_CNTL_ENABLE (1 << 0) 287# define EVERGREEN_DP_VID_STREAM_STATUS (1 <<16) 288#define EVERGREEN_DP_STEER_FIFO 0x7310 289# define EVERGREEN_DP_STEER_FIFO_RESET (1 << 0) 290#define EVERGREEN_DP_SEC_CNTL 0x7280 291# define EVERGREEN_DP_SEC_STREAM_ENABLE (1 << 0) 292# define EVERGREEN_DP_SEC_ASP_ENABLE (1 << 4) 293# define EVERGREEN_DP_SEC_ATP_ENABLE (1 << 8) 294# define EVERGREEN_DP_SEC_AIP_ENABLE (1 << 12) 295# define EVERGREEN_DP_SEC_GSP_ENABLE (1 << 20) 296# define EVERGREEN_DP_SEC_AVI_ENABLE (1 << 24) 297# define EVERGREEN_DP_SEC_MPG_ENABLE (1 << 28) 298#define EVERGREEN_DP_SEC_TIMESTAMP 0x72a4 299# define EVERGREEN_DP_SEC_TIMESTAMP_MODE(x) (((x) & 0x3) << 0) 300#define EVERGREEN_DP_SEC_AUD_N 0x7294 301# define EVERGREEN_DP_SEC_N_BASE_MULTIPLE(x) (((x) & 0xf) << 24) 302# define EVERGREEN_DP_SEC_SS_EN (1 << 28) 303 304/*DCIO_UNIPHY block*/ 305#define NI_DCIO_UNIPHY0_UNIPHY_TX_CONTROL1 (0x6600 -0x6600) 306#define NI_DCIO_UNIPHY1_UNIPHY_TX_CONTROL1 (0x6640 -0x6600) 307#define NI_DCIO_UNIPHY2_UNIPHY_TX_CONTROL1 (0x6680 - 0x6600) 308#define NI_DCIO_UNIPHY3_UNIPHY_TX_CONTROL1 (0x66C0 - 0x6600) 309#define NI_DCIO_UNIPHY4_UNIPHY_TX_CONTROL1 (0x6700 - 0x6600) 310#define NI_DCIO_UNIPHY5_UNIPHY_TX_CONTROL1 (0x6740 - 0x6600) 311 312#define NI_DCIO_UNIPHY0_PLL_CONTROL1 0x6618 313# define NI_DCIO_UNIPHY0_PLL_CONTROL1_ENABLE (1 << 0) 314 315#endif