cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

r200 (4317B)


      1r200 0x3294
      20x1434 SRC_Y_X
      30x1438 DST_Y_X
      40x143C DST_HEIGHT_WIDTH
      50x146C DP_GUI_MASTER_CNTL
      60x1474 BRUSH_Y_X
      70x1478 DP_BRUSH_BKGD_CLR
      80x147C DP_BRUSH_FRGD_CLR
      90x1480 BRUSH_DATA0
     100x1484 BRUSH_DATA1
     110x1598 DST_WIDTH_HEIGHT
     120x15C0 CLR_CMP_CNTL
     130x15C4 CLR_CMP_CLR_SRC
     140x15C8 CLR_CMP_CLR_DST
     150x15CC CLR_CMP_MSK
     160x15D8 DP_SRC_FRGD_CLR
     170x15DC DP_SRC_BKGD_CLR
     180x1600 DST_LINE_START
     190x1604 DST_LINE_END
     200x1608 DST_LINE_PATCOUNT
     210x16C0 DP_CNTL
     220x16CC DP_WRITE_MSK
     230x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
     240x16E8 DEFAULT_SC_BOTTOM_RIGHT
     250x16EC SC_TOP_LEFT
     260x16F0 SC_BOTTOM_RIGHT
     270x16F4 SRC_SC_BOTTOM_RIGHT
     280x1714 DSTCACHE_CTLSTAT
     290x1720 WAIT_UNTIL
     300x172C RBBM_GUICNTL
     310x1c14 PP_MISC
     320x1c18 PP_FOG_COLOR
     330x1c1c RE_SOLID_COLOR
     340x1c20 RB3D_BLENDCNTL
     350x1c4c SE_CNTL
     360x1c50 RE_CNTL
     370x1cc8 RE_STIPPLE_ADDR
     380x1ccc RE_STIPPLE_DATA
     390x1cd0 RE_LINE_PATTERN
     400x1cd4 RE_LINE_STATE
     410x1cd8 RE_SCISSOR_TL_0
     420x1cdc RE_SCISSOR_BR_0
     430x1ce0 RE_SCISSOR_TL_1
     440x1ce4 RE_SCISSOR_BR_1
     450x1ce8 RE_SCISSOR_TL_2
     460x1cec RE_SCISSOR_BR_2
     470x1d60 RB3D_DEPTHXY_OFFSET
     480x1d7c RB3D_STENCILREFMASK
     490x1d80 RB3D_ROPCNTL
     500x1d84 RB3D_PLANEMASK
     510x1d98 VAP_VPORT_XSCALE
     520x1d9c VAP_VPORT_XOFFSET
     530x1da0 VAP_VPORT_YSCALE
     540x1da4 VAP_VPORT_YOFFSET
     550x1da8 VAP_VPORT_ZSCALE
     560x1dac VAP_VPORT_ZOFFSET
     570x1db0 SE_ZBIAS_FACTOR
     580x1db4 SE_ZBIAS_CONSTANT
     590x1db8 SE_LINE_WIDTH
     600x2080 SE_VAP_CNTL
     610x2090 SE_TCL_OUTPUT_VTX_FMT_0
     620x2094 SE_TCL_OUTPUT_VTX_FMT_1
     630x20b0 SE_VTE_CNTL
     640x2140 SE_CNTL_STATUS
     650x2180 SE_VTX_STATE_CNTL
     660x2200 SE_TCL_VECTOR_INDX_REG
     670x2204 SE_TCL_VECTOR_DATA_REG
     680x2208 SE_TCL_SCALAR_INDX_REG
     690x220c SE_TCL_SCALAR_DATA_REG
     700x2230 SE_TCL_MATRIX_SEL_0
     710x2234 SE_TCL_MATRIX_SEL_1
     720x2238 SE_TCL_MATRIX_SEL_2
     730x223c SE_TCL_MATRIX_SEL_3
     740x2240 SE_TCL_MATRIX_SEL_4
     750x2250 SE_TCL_OUTPUT_VTX_COMP_SEL
     760x2254 SE_TCL_INPUT_VTX_VECTOR_ADDR_0
     770x2258 SE_TCL_INPUT_VTX_VECTOR_ADDR_1
     780x225c SE_TCL_INPUT_VTX_VECTOR_ADDR_2
     790x2260 SE_TCL_INPUT_VTX_VECTOR_ADDR_3
     800x2268 SE_TCL_LIGHT_MODEL_CTL_0
     810x226c SE_TCL_LIGHT_MODEL_CTL_1
     820x2270 SE_TCL_PER_LIGHT_CTL_0
     830x2274 SE_TCL_PER_LIGHT_CTL_1
     840x2278 SE_TCL_PER_LIGHT_CTL_2
     850x227c SE_TCL_PER_LIGHT_CTL_3
     860x2284 VAP_PVS_STATE_FLUSH_REG
     870x22a8 SE_TCL_TEX_PROC_CTL_2
     880x22ac SE_TCL_TEX_PROC_CTL_3
     890x22b0 SE_TCL_TEX_PROC_CTL_0
     900x22b4 SE_TCL_TEX_PROC_CTL_1
     910x22b8 SE_TCL_TEX_CYL_WRAP_CTL
     920x22c0 SE_TCL_UCP_VERT_BLEND_CNTL
     930x22c4 SE_TCL_POINT_SPRITE_CNTL
     940x22d0 SE_PVS_CNTL
     950x22d4 SE_PVS_CONST_CNTL
     960x2648 RE_POINTSIZE
     970x26c0 RE_TOP_LEFT
     980x26c4 RE_MISC
     990x26f0 RE_AUX_SCISSOR_CNTL
    1000x2c14 PP_BORDER_COLOR_0
    1010x2c34 PP_BORDER_COLOR_1
    1020x2c54 PP_BORDER_COLOR_2
    1030x2c74 PP_BORDER_COLOR_3
    1040x2c94 PP_BORDER_COLOR_4
    1050x2cb4 PP_BORDER_COLOR_5
    1060x2cc4 PP_CNTL_X
    1070x2cf8 PP_TRI_PERF
    1080x2cfc PP_PERF_CNTL
    1090x2d9c PP_TAM_DEBUG3
    1100x2ee0 PP_TFACTOR_0
    1110x2ee4 PP_TFACTOR_1
    1120x2ee8 PP_TFACTOR_2
    1130x2eec PP_TFACTOR_3
    1140x2ef0 PP_TFACTOR_4
    1150x2ef4 PP_TFACTOR_5
    1160x2ef8 PP_TFACTOR_6
    1170x2efc PP_TFACTOR_7
    1180x2f00 PP_TXCBLEND_0
    1190x2f04 PP_TXCBLEND2_0
    1200x2f08 PP_TXABLEND_0
    1210x2f0c PP_TXABLEND2_0
    1220x2f10 PP_TXCBLEND_1
    1230x2f14 PP_TXCBLEND2_1
    1240x2f18 PP_TXABLEND_1
    1250x2f1c PP_TXABLEND2_1
    1260x2f20 PP_TXCBLEND_2
    1270x2f24 PP_TXCBLEND2_2
    1280x2f28 PP_TXABLEND_2
    1290x2f2c PP_TXABLEND2_2
    1300x2f30 PP_TXCBLEND_3
    1310x2f34 PP_TXCBLEND2_3
    1320x2f38 PP_TXABLEND_3
    1330x2f3c PP_TXABLEND2_3
    1340x2f40 PP_TXCBLEND_4
    1350x2f44 PP_TXCBLEND2_4
    1360x2f48 PP_TXABLEND_4
    1370x2f4c PP_TXABLEND2_4
    1380x2f50 PP_TXCBLEND_5
    1390x2f54 PP_TXCBLEND2_5
    1400x2f58 PP_TXABLEND_5
    1410x2f5c PP_TXABLEND2_5
    1420x2f60 PP_TXCBLEND_6
    1430x2f64 PP_TXCBLEND2_6
    1440x2f68 PP_TXABLEND_6
    1450x2f6c PP_TXABLEND2_6
    1460x2f70 PP_TXCBLEND_7
    1470x2f74 PP_TXCBLEND2_7
    1480x2f78 PP_TXABLEND_7
    1490x2f7c PP_TXABLEND2_7
    1500x2f80 PP_TXCBLEND_8
    1510x2f84 PP_TXCBLEND2_8
    1520x2f88 PP_TXABLEND_8
    1530x2f8c PP_TXABLEND2_8
    1540x2f90 PP_TXCBLEND_9
    1550x2f94 PP_TXCBLEND2_9
    1560x2f98 PP_TXABLEND_9
    1570x2f9c PP_TXABLEND2_9
    1580x2fa0 PP_TXCBLEND_10
    1590x2fa4 PP_TXCBLEND2_10
    1600x2fa8 PP_TXABLEND_10
    1610x2fac PP_TXABLEND2_10
    1620x2fb0 PP_TXCBLEND_11
    1630x2fb4 PP_TXCBLEND2_11
    1640x2fb8 PP_TXABLEND_11
    1650x2fbc PP_TXABLEND2_11
    1660x2fc0 PP_TXCBLEND_12
    1670x2fc4 PP_TXCBLEND2_12
    1680x2fc8 PP_TXABLEND_12
    1690x2fcc PP_TXABLEND2_12
    1700x2fd0 PP_TXCBLEND_13
    1710x2fd4 PP_TXCBLEND2_13
    1720x2fd8 PP_TXABLEND_13
    1730x2fdc PP_TXABLEND2_13
    1740x2fe0 PP_TXCBLEND_14
    1750x2fe4 PP_TXCBLEND2_14
    1760x2fe8 PP_TXABLEND_14
    1770x2fec PP_TXABLEND2_14
    1780x2ff0 PP_TXCBLEND_15
    1790x2ff4 PP_TXCBLEND2_15
    1800x2ff8 PP_TXABLEND_15
    1810x2ffc PP_TXABLEND2_15
    1820x3218 RB3D_BLENCOLOR
    1830x321c RB3D_ABLENDCNTL
    1840x3220 RB3D_CBLENDCNTL
    1850x3290 RB3D_ZPASS_DATA
    186