cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

uvd_v4_2.c (2538B)

      1/*
      2 * Copyright 2013 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: Christian König <christian.koenig@amd.com>
     23 */
     24
     25#include <linux/firmware.h>
     26
     27#include "radeon.h"
     28#include "radeon_asic.h"
     29#include "cikd.h"
     30
     31/**
     32 * uvd_v4_2_resume - memory controller programming
     33 *
     34 * @rdev: radeon_device pointer
     35 *
     36 * Let the UVD memory controller know it's offsets
     37 */
     38int uvd_v4_2_resume(struct radeon_device *rdev)
     39{
     40	uint64_t addr;
     41	uint32_t size;
     42
     43	/* program the VCPU memory controller bits 0-27 */
     44
     45	/* skip over the header of the new firmware format */
     46	if (rdev->uvd.fw_header_present)
     47		addr = (rdev->uvd.gpu_addr + 0x200) >> 3;
     48	else
     49		addr = rdev->uvd.gpu_addr >> 3;
     50
     51	size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;
     52	WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
     53	WREG32(UVD_VCPU_CACHE_SIZE0, size);
     54
     55	addr += size;
     56	size = RADEON_UVD_HEAP_SIZE >> 3;
     57	WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
     58	WREG32(UVD_VCPU_CACHE_SIZE1, size);
     59
     60	addr += size;
     61	size = (RADEON_UVD_STACK_SIZE +
     62	       (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3;
     63	WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
     64	WREG32(UVD_VCPU_CACHE_SIZE2, size);
     65
     66	/* bits 28-31 */
     67	addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
     68	WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
     69
     70	/* bits 32-39 */
     71	addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
     72	WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
     73
     74	if (rdev->uvd.fw_header_present)
     75		WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles);
     76
     77	return 0;
     78}