cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dc.c (92352B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (C) 2012 Avionic Design GmbH
      4 * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
      5 */
      6
      7#include <linux/clk.h>
      8#include <linux/debugfs.h>
      9#include <linux/delay.h>
     10#include <linux/iommu.h>
     11#include <linux/interconnect.h>
     12#include <linux/module.h>
     13#include <linux/of_device.h>
     14#include <linux/pm_domain.h>
     15#include <linux/pm_opp.h>
     16#include <linux/pm_runtime.h>
     17#include <linux/reset.h>
     18
     19#include <soc/tegra/common.h>
     20#include <soc/tegra/pmc.h>
     21
     22#include <drm/drm_atomic.h>
     23#include <drm/drm_atomic_helper.h>
     24#include <drm/drm_debugfs.h>
     25#include <drm/drm_fourcc.h>
     26#include <drm/drm_plane_helper.h>
     27#include <drm/drm_vblank.h>
     28
     29#include "dc.h"
     30#include "drm.h"
     31#include "gem.h"
     32#include "hub.h"
     33#include "plane.h"
     34
     35static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
     36					    struct drm_crtc_state *state);
     37
     38static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
     39{
     40	stats->frames = 0;
     41	stats->vblank = 0;
     42	stats->underflow = 0;
     43	stats->overflow = 0;
     44}
     45
     46/* Reads the active copy of a register. */
     47static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
     48{
     49	u32 value;
     50
     51	tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
     52	value = tegra_dc_readl(dc, offset);
     53	tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
     54
     55	return value;
     56}
     57
     58static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
     59					      unsigned int offset)
     60{
     61	if (offset >= 0x500 && offset <= 0x638) {
     62		offset = 0x000 + (offset - 0x500);
     63		return plane->offset + offset;
     64	}
     65
     66	if (offset >= 0x700 && offset <= 0x719) {
     67		offset = 0x180 + (offset - 0x700);
     68		return plane->offset + offset;
     69	}
     70
     71	if (offset >= 0x800 && offset <= 0x839) {
     72		offset = 0x1c0 + (offset - 0x800);
     73		return plane->offset + offset;
     74	}
     75
     76	dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
     77
     78	return plane->offset + offset;
     79}
     80
     81static inline u32 tegra_plane_readl(struct tegra_plane *plane,
     82				    unsigned int offset)
     83{
     84	return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
     85}
     86
     87static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
     88				      unsigned int offset)
     89{
     90	tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
     91}
     92
     93bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
     94{
     95	struct device_node *np = dc->dev->of_node;
     96	struct of_phandle_iterator it;
     97	int err;
     98
     99	of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
    100		if (it.node == dev->of_node)
    101			return true;
    102
    103	return false;
    104}
    105
    106/*
    107 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
    108 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
    109 * Latching happens mmediately if the display controller is in STOP mode or
    110 * on the next frame boundary otherwise.
    111 *
    112 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
    113 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
    114 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
    115 * into the ACTIVE copy, either immediately if the display controller is in
    116 * STOP mode, or at the next frame boundary otherwise.
    117 */
    118void tegra_dc_commit(struct tegra_dc *dc)
    119{
    120	tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
    121	tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
    122}
    123
    124static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
    125				  unsigned int bpp)
    126{
    127	fixed20_12 outf = dfixed_init(out);
    128	fixed20_12 inf = dfixed_init(in);
    129	u32 dda_inc;
    130	int max;
    131
    132	if (v)
    133		max = 15;
    134	else {
    135		switch (bpp) {
    136		case 2:
    137			max = 8;
    138			break;
    139
    140		default:
    141			WARN_ON_ONCE(1);
    142			fallthrough;
    143		case 4:
    144			max = 4;
    145			break;
    146		}
    147	}
    148
    149	outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
    150	inf.full -= dfixed_const(1);
    151
    152	dda_inc = dfixed_div(inf, outf);
    153	dda_inc = min_t(u32, dda_inc, dfixed_const(max));
    154
    155	return dda_inc;
    156}
    157
    158static inline u32 compute_initial_dda(unsigned int in)
    159{
    160	fixed20_12 inf = dfixed_init(in);
    161	return dfixed_frac(inf);
    162}
    163
    164static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
    165{
    166	u32 background[3] = {
    167		BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
    168		BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
    169		BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
    170	};
    171	u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
    172			 BLEND_COLOR_KEY_NONE;
    173	u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
    174	struct tegra_plane_state *state;
    175	u32 blending[2];
    176	unsigned int i;
    177
    178	/* disable blending for non-overlapping case */
    179	tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
    180	tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
    181
    182	state = to_tegra_plane_state(plane->base.state);
    183
    184	if (state->opaque) {
    185		/*
    186		 * Since custom fix-weight blending isn't utilized and weight
    187		 * of top window is set to max, we can enforce dependent
    188		 * blending which in this case results in transparent bottom
    189		 * window if top window is opaque and if top window enables
    190		 * alpha blending, then bottom window is getting alpha value
    191		 * of 1 minus the sum of alpha components of the overlapping
    192		 * plane.
    193		 */
    194		background[0] |= BLEND_CONTROL_DEPENDENT;
    195		background[1] |= BLEND_CONTROL_DEPENDENT;
    196
    197		/*
    198		 * The region where three windows overlap is the intersection
    199		 * of the two regions where two windows overlap. It contributes
    200		 * to the area if all of the windows on top of it have an alpha
    201		 * component.
    202		 */
    203		switch (state->base.normalized_zpos) {
    204		case 0:
    205			if (state->blending[0].alpha &&
    206			    state->blending[1].alpha)
    207				background[2] |= BLEND_CONTROL_DEPENDENT;
    208			break;
    209
    210		case 1:
    211			background[2] |= BLEND_CONTROL_DEPENDENT;
    212			break;
    213		}
    214	} else {
    215		/*
    216		 * Enable alpha blending if pixel format has an alpha
    217		 * component.
    218		 */
    219		foreground |= BLEND_CONTROL_ALPHA;
    220
    221		/*
    222		 * If any of the windows on top of this window is opaque, it
    223		 * will completely conceal this window within that area. If
    224		 * top window has an alpha component, it is blended over the
    225		 * bottom window.
    226		 */
    227		for (i = 0; i < 2; i++) {
    228			if (state->blending[i].alpha &&
    229			    state->blending[i].top)
    230				background[i] |= BLEND_CONTROL_DEPENDENT;
    231		}
    232
    233		switch (state->base.normalized_zpos) {
    234		case 0:
    235			if (state->blending[0].alpha &&
    236			    state->blending[1].alpha)
    237				background[2] |= BLEND_CONTROL_DEPENDENT;
    238			break;
    239
    240		case 1:
    241			/*
    242			 * When both middle and topmost windows have an alpha,
    243			 * these windows a mixed together and then the result
    244			 * is blended over the bottom window.
    245			 */
    246			if (state->blending[0].alpha &&
    247			    state->blending[0].top)
    248				background[2] |= BLEND_CONTROL_ALPHA;
    249
    250			if (state->blending[1].alpha &&
    251			    state->blending[1].top)
    252				background[2] |= BLEND_CONTROL_ALPHA;
    253			break;
    254		}
    255	}
    256
    257	switch (state->base.normalized_zpos) {
    258	case 0:
    259		tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
    260		tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
    261		tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
    262		break;
    263
    264	case 1:
    265		/*
    266		 * If window B / C is topmost, then X / Y registers are
    267		 * matching the order of blending[...] state indices,
    268		 * otherwise a swap is required.
    269		 */
    270		if (!state->blending[0].top && state->blending[1].top) {
    271			blending[0] = foreground;
    272			blending[1] = background[1];
    273		} else {
    274			blending[0] = background[0];
    275			blending[1] = foreground;
    276		}
    277
    278		tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
    279		tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
    280		tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
    281		break;
    282
    283	case 2:
    284		tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
    285		tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
    286		tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
    287		break;
    288	}
    289}
    290
    291static void tegra_plane_setup_blending(struct tegra_plane *plane,
    292				       const struct tegra_dc_window *window)
    293{
    294	u32 value;
    295
    296	value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
    297		BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
    298		BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
    299	tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
    300
    301	value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
    302		BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
    303		BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
    304	tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
    305
    306	value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
    307	tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
    308}
    309
    310static bool
    311tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
    312				     const struct tegra_dc_window *window)
    313{
    314	struct tegra_dc *dc = plane->dc;
    315
    316	if (window->src.w == window->dst.w)
    317		return false;
    318
    319	if (plane->index == 0 && dc->soc->has_win_a_without_filters)
    320		return false;
    321
    322	return true;
    323}
    324
    325static bool
    326tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
    327				   const struct tegra_dc_window *window)
    328{
    329	struct tegra_dc *dc = plane->dc;
    330
    331	if (window->src.h == window->dst.h)
    332		return false;
    333
    334	if (plane->index == 0 && dc->soc->has_win_a_without_filters)
    335		return false;
    336
    337	if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
    338		return false;
    339
    340	return true;
    341}
    342
    343static void tegra_dc_setup_window(struct tegra_plane *plane,
    344				  const struct tegra_dc_window *window)
    345{
    346	unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
    347	struct tegra_dc *dc = plane->dc;
    348	unsigned int planes;
    349	u32 value;
    350	bool yuv;
    351
    352	/*
    353	 * For YUV planar modes, the number of bytes per pixel takes into
    354	 * account only the luma component and therefore is 1.
    355	 */
    356	yuv = tegra_plane_format_is_yuv(window->format, &planes, NULL);
    357	if (!yuv)
    358		bpp = window->bits_per_pixel / 8;
    359	else
    360		bpp = (planes > 1) ? 1 : 2;
    361
    362	tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
    363	tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
    364
    365	value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
    366	tegra_plane_writel(plane, value, DC_WIN_POSITION);
    367
    368	value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
    369	tegra_plane_writel(plane, value, DC_WIN_SIZE);
    370
    371	h_offset = window->src.x * bpp;
    372	v_offset = window->src.y;
    373	h_size = window->src.w * bpp;
    374	v_size = window->src.h;
    375
    376	if (window->reflect_x)
    377		h_offset += (window->src.w - 1) * bpp;
    378
    379	if (window->reflect_y)
    380		v_offset += window->src.h - 1;
    381
    382	value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
    383	tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
    384
    385	/*
    386	 * For DDA computations the number of bytes per pixel for YUV planar
    387	 * modes needs to take into account all Y, U and V components.
    388	 */
    389	if (yuv && planes > 1)
    390		bpp = 2;
    391
    392	h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
    393	v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
    394
    395	value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
    396	tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
    397
    398	h_dda = compute_initial_dda(window->src.x);
    399	v_dda = compute_initial_dda(window->src.y);
    400
    401	tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
    402	tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
    403
    404	tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
    405	tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
    406
    407	tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
    408
    409	if (yuv && planes > 1) {
    410		tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
    411
    412		if (planes > 2)
    413			tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
    414
    415		value = window->stride[1] << 16 | window->stride[0];
    416		tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
    417	} else {
    418		tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
    419	}
    420
    421	tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
    422	tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
    423
    424	if (dc->soc->supports_block_linear) {
    425		unsigned long height = window->tiling.value;
    426
    427		switch (window->tiling.mode) {
    428		case TEGRA_BO_TILING_MODE_PITCH:
    429			value = DC_WINBUF_SURFACE_KIND_PITCH;
    430			break;
    431
    432		case TEGRA_BO_TILING_MODE_TILED:
    433			value = DC_WINBUF_SURFACE_KIND_TILED;
    434			break;
    435
    436		case TEGRA_BO_TILING_MODE_BLOCK:
    437			value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
    438				DC_WINBUF_SURFACE_KIND_BLOCK;
    439			break;
    440		}
    441
    442		tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
    443	} else {
    444		switch (window->tiling.mode) {
    445		case TEGRA_BO_TILING_MODE_PITCH:
    446			value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
    447				DC_WIN_BUFFER_ADDR_MODE_LINEAR;
    448			break;
    449
    450		case TEGRA_BO_TILING_MODE_TILED:
    451			value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
    452				DC_WIN_BUFFER_ADDR_MODE_TILE;
    453			break;
    454
    455		case TEGRA_BO_TILING_MODE_BLOCK:
    456			/*
    457			 * No need to handle this here because ->atomic_check
    458			 * will already have filtered it out.
    459			 */
    460			break;
    461		}
    462
    463		tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
    464	}
    465
    466	value = WIN_ENABLE;
    467
    468	if (yuv) {
    469		/* setup default colorspace conversion coefficients */
    470		tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
    471		tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
    472		tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
    473		tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
    474		tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
    475		tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
    476		tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
    477		tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
    478
    479		value |= CSC_ENABLE;
    480	} else if (window->bits_per_pixel < 24) {
    481		value |= COLOR_EXPAND;
    482	}
    483
    484	if (window->reflect_x)
    485		value |= H_DIRECTION;
    486
    487	if (window->reflect_y)
    488		value |= V_DIRECTION;
    489
    490	if (tegra_plane_use_horizontal_filtering(plane, window)) {
    491		/*
    492		 * Enable horizontal 6-tap filter and set filtering
    493		 * coefficients to the default values defined in TRM.
    494		 */
    495		tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
    496		tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
    497		tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
    498		tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
    499		tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
    500		tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
    501		tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
    502		tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
    503		tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
    504		tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
    505		tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
    506		tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
    507		tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
    508		tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
    509		tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
    510		tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
    511
    512		value |= H_FILTER;
    513	}
    514
    515	if (tegra_plane_use_vertical_filtering(plane, window)) {
    516		unsigned int i, k;
    517
    518		/*
    519		 * Enable vertical 2-tap filter and set filtering
    520		 * coefficients to the default values defined in TRM.
    521		 */
    522		for (i = 0, k = 128; i < 16; i++, k -= 8)
    523			tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
    524
    525		value |= V_FILTER;
    526	}
    527
    528	tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
    529
    530	if (dc->soc->has_legacy_blending)
    531		tegra_plane_setup_blending_legacy(plane);
    532	else
    533		tegra_plane_setup_blending(plane, window);
    534}
    535
    536static const u32 tegra20_primary_formats[] = {
    537	DRM_FORMAT_ARGB4444,
    538	DRM_FORMAT_ARGB1555,
    539	DRM_FORMAT_RGB565,
    540	DRM_FORMAT_RGBA5551,
    541	DRM_FORMAT_ABGR8888,
    542	DRM_FORMAT_ARGB8888,
    543	/* non-native formats */
    544	DRM_FORMAT_XRGB1555,
    545	DRM_FORMAT_RGBX5551,
    546	DRM_FORMAT_XBGR8888,
    547	DRM_FORMAT_XRGB8888,
    548};
    549
    550static const u64 tegra20_modifiers[] = {
    551	DRM_FORMAT_MOD_LINEAR,
    552	DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
    553	DRM_FORMAT_MOD_INVALID
    554};
    555
    556static const u32 tegra114_primary_formats[] = {
    557	DRM_FORMAT_ARGB4444,
    558	DRM_FORMAT_ARGB1555,
    559	DRM_FORMAT_RGB565,
    560	DRM_FORMAT_RGBA5551,
    561	DRM_FORMAT_ABGR8888,
    562	DRM_FORMAT_ARGB8888,
    563	/* new on Tegra114 */
    564	DRM_FORMAT_ABGR4444,
    565	DRM_FORMAT_ABGR1555,
    566	DRM_FORMAT_BGRA5551,
    567	DRM_FORMAT_XRGB1555,
    568	DRM_FORMAT_RGBX5551,
    569	DRM_FORMAT_XBGR1555,
    570	DRM_FORMAT_BGRX5551,
    571	DRM_FORMAT_BGR565,
    572	DRM_FORMAT_BGRA8888,
    573	DRM_FORMAT_RGBA8888,
    574	DRM_FORMAT_XRGB8888,
    575	DRM_FORMAT_XBGR8888,
    576};
    577
    578static const u32 tegra124_primary_formats[] = {
    579	DRM_FORMAT_ARGB4444,
    580	DRM_FORMAT_ARGB1555,
    581	DRM_FORMAT_RGB565,
    582	DRM_FORMAT_RGBA5551,
    583	DRM_FORMAT_ABGR8888,
    584	DRM_FORMAT_ARGB8888,
    585	/* new on Tegra114 */
    586	DRM_FORMAT_ABGR4444,
    587	DRM_FORMAT_ABGR1555,
    588	DRM_FORMAT_BGRA5551,
    589	DRM_FORMAT_XRGB1555,
    590	DRM_FORMAT_RGBX5551,
    591	DRM_FORMAT_XBGR1555,
    592	DRM_FORMAT_BGRX5551,
    593	DRM_FORMAT_BGR565,
    594	DRM_FORMAT_BGRA8888,
    595	DRM_FORMAT_RGBA8888,
    596	DRM_FORMAT_XRGB8888,
    597	DRM_FORMAT_XBGR8888,
    598	/* new on Tegra124 */
    599	DRM_FORMAT_RGBX8888,
    600	DRM_FORMAT_BGRX8888,
    601};
    602
    603static const u64 tegra124_modifiers[] = {
    604	DRM_FORMAT_MOD_LINEAR,
    605	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
    606	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
    607	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
    608	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
    609	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
    610	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
    611	DRM_FORMAT_MOD_INVALID
    612};
    613
    614static int tegra_plane_atomic_check(struct drm_plane *plane,
    615				    struct drm_atomic_state *state)
    616{
    617	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
    618										 plane);
    619	struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);
    620	unsigned int supported_rotation = DRM_MODE_ROTATE_0 |
    621					  DRM_MODE_REFLECT_X |
    622					  DRM_MODE_REFLECT_Y;
    623	unsigned int rotation = new_plane_state->rotation;
    624	struct tegra_bo_tiling *tiling = &plane_state->tiling;
    625	struct tegra_plane *tegra = to_tegra_plane(plane);
    626	struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc);
    627	int err;
    628
    629	plane_state->peak_memory_bandwidth = 0;
    630	plane_state->avg_memory_bandwidth = 0;
    631
    632	/* no need for further checks if the plane is being disabled */
    633	if (!new_plane_state->crtc) {
    634		plane_state->total_peak_memory_bandwidth = 0;
    635		return 0;
    636	}
    637
    638	err = tegra_plane_format(new_plane_state->fb->format->format,
    639				 &plane_state->format,
    640				 &plane_state->swap);
    641	if (err < 0)
    642		return err;
    643
    644	/*
    645	 * Tegra20 and Tegra30 are special cases here because they support
    646	 * only variants of specific formats with an alpha component, but not
    647	 * the corresponding opaque formats. However, the opaque formats can
    648	 * be emulated by disabling alpha blending for the plane.
    649	 */
    650	if (dc->soc->has_legacy_blending) {
    651		err = tegra_plane_setup_legacy_state(tegra, plane_state);
    652		if (err < 0)
    653			return err;
    654	}
    655
    656	err = tegra_fb_get_tiling(new_plane_state->fb, tiling);
    657	if (err < 0)
    658		return err;
    659
    660	if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
    661	    !dc->soc->supports_block_linear) {
    662		DRM_ERROR("hardware doesn't support block linear mode\n");
    663		return -EINVAL;
    664	}
    665
    666	/*
    667	 * Older userspace used custom BO flag in order to specify the Y
    668	 * reflection, while modern userspace uses the generic DRM rotation
    669	 * property in order to achieve the same result.  The legacy BO flag
    670	 * duplicates the DRM rotation property when both are set.
    671	 */
    672	if (tegra_fb_is_bottom_up(new_plane_state->fb))
    673		rotation |= DRM_MODE_REFLECT_Y;
    674
    675	rotation = drm_rotation_simplify(rotation, supported_rotation);
    676
    677	if (rotation & DRM_MODE_REFLECT_X)
    678		plane_state->reflect_x = true;
    679	else
    680		plane_state->reflect_x = false;
    681
    682	if (rotation & DRM_MODE_REFLECT_Y)
    683		plane_state->reflect_y = true;
    684	else
    685		plane_state->reflect_y = false;
    686
    687	/*
    688	 * Tegra doesn't support different strides for U and V planes so we
    689	 * error out if the user tries to display a framebuffer with such a
    690	 * configuration.
    691	 */
    692	if (new_plane_state->fb->format->num_planes > 2) {
    693		if (new_plane_state->fb->pitches[2] != new_plane_state->fb->pitches[1]) {
    694			DRM_ERROR("unsupported UV-plane configuration\n");
    695			return -EINVAL;
    696		}
    697	}
    698
    699	err = tegra_plane_state_add(tegra, new_plane_state);
    700	if (err < 0)
    701		return err;
    702
    703	return 0;
    704}
    705
    706static void tegra_plane_atomic_disable(struct drm_plane *plane,
    707				       struct drm_atomic_state *state)
    708{
    709	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
    710									   plane);
    711	struct tegra_plane *p = to_tegra_plane(plane);
    712	u32 value;
    713
    714	/* rien ne va plus */
    715	if (!old_state || !old_state->crtc)
    716		return;
    717
    718	value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
    719	value &= ~WIN_ENABLE;
    720	tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
    721}
    722
    723static void tegra_plane_atomic_update(struct drm_plane *plane,
    724				      struct drm_atomic_state *state)
    725{
    726	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
    727									   plane);
    728	struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state);
    729	struct drm_framebuffer *fb = new_state->fb;
    730	struct tegra_plane *p = to_tegra_plane(plane);
    731	struct tegra_dc_window window;
    732	unsigned int i;
    733
    734	/* rien ne va plus */
    735	if (!new_state->crtc || !new_state->fb)
    736		return;
    737
    738	if (!new_state->visible)
    739		return tegra_plane_atomic_disable(plane, state);
    740
    741	memset(&window, 0, sizeof(window));
    742	window.src.x = new_state->src.x1 >> 16;
    743	window.src.y = new_state->src.y1 >> 16;
    744	window.src.w = drm_rect_width(&new_state->src) >> 16;
    745	window.src.h = drm_rect_height(&new_state->src) >> 16;
    746	window.dst.x = new_state->dst.x1;
    747	window.dst.y = new_state->dst.y1;
    748	window.dst.w = drm_rect_width(&new_state->dst);
    749	window.dst.h = drm_rect_height(&new_state->dst);
    750	window.bits_per_pixel = fb->format->cpp[0] * 8;
    751	window.reflect_x = tegra_plane_state->reflect_x;
    752	window.reflect_y = tegra_plane_state->reflect_y;
    753
    754	/* copy from state */
    755	window.zpos = new_state->normalized_zpos;
    756	window.tiling = tegra_plane_state->tiling;
    757	window.format = tegra_plane_state->format;
    758	window.swap = tegra_plane_state->swap;
    759
    760	for (i = 0; i < fb->format->num_planes; i++) {
    761		window.base[i] = tegra_plane_state->iova[i] + fb->offsets[i];
    762
    763		/*
    764		 * Tegra uses a shared stride for UV planes. Framebuffers are
    765		 * already checked for this in the tegra_plane_atomic_check()
    766		 * function, so it's safe to ignore the V-plane pitch here.
    767		 */
    768		if (i < 2)
    769			window.stride[i] = fb->pitches[i];
    770	}
    771
    772	tegra_dc_setup_window(p, &window);
    773}
    774
    775static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
    776	.prepare_fb = tegra_plane_prepare_fb,
    777	.cleanup_fb = tegra_plane_cleanup_fb,
    778	.atomic_check = tegra_plane_atomic_check,
    779	.atomic_disable = tegra_plane_atomic_disable,
    780	.atomic_update = tegra_plane_atomic_update,
    781};
    782
    783static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
    784{
    785	/*
    786	 * Ideally this would use drm_crtc_mask(), but that would require the
    787	 * CRTC to already be in the mode_config's list of CRTCs. However, it
    788	 * will only be added to that list in the drm_crtc_init_with_planes()
    789	 * (in tegra_dc_init()), which in turn requires registration of these
    790	 * planes. So we have ourselves a nice little chicken and egg problem
    791	 * here.
    792	 *
    793	 * We work around this by manually creating the mask from the number
    794	 * of CRTCs that have been registered, and should therefore always be
    795	 * the same as drm_crtc_index() after registration.
    796	 */
    797	return 1 << drm->mode_config.num_crtc;
    798}
    799
    800static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
    801						    struct tegra_dc *dc)
    802{
    803	unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
    804	enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
    805	struct tegra_plane *plane;
    806	unsigned int num_formats;
    807	const u64 *modifiers;
    808	const u32 *formats;
    809	int err;
    810
    811	plane = kzalloc(sizeof(*plane), GFP_KERNEL);
    812	if (!plane)
    813		return ERR_PTR(-ENOMEM);
    814
    815	/* Always use window A as primary window */
    816	plane->offset = 0xa00;
    817	plane->index = 0;
    818	plane->dc = dc;
    819
    820	num_formats = dc->soc->num_primary_formats;
    821	formats = dc->soc->primary_formats;
    822	modifiers = dc->soc->modifiers;
    823
    824	err = tegra_plane_interconnect_init(plane);
    825	if (err) {
    826		kfree(plane);
    827		return ERR_PTR(err);
    828	}
    829
    830	err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
    831				       &tegra_plane_funcs, formats,
    832				       num_formats, modifiers, type, NULL);
    833	if (err < 0) {
    834		kfree(plane);
    835		return ERR_PTR(err);
    836	}
    837
    838	drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
    839	drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
    840
    841	err = drm_plane_create_rotation_property(&plane->base,
    842						 DRM_MODE_ROTATE_0,
    843						 DRM_MODE_ROTATE_0 |
    844						 DRM_MODE_ROTATE_180 |
    845						 DRM_MODE_REFLECT_X |
    846						 DRM_MODE_REFLECT_Y);
    847	if (err < 0)
    848		dev_err(dc->dev, "failed to create rotation property: %d\n",
    849			err);
    850
    851	return &plane->base;
    852}
    853
    854static const u32 tegra_legacy_cursor_plane_formats[] = {
    855	DRM_FORMAT_RGBA8888,
    856};
    857
    858static const u32 tegra_cursor_plane_formats[] = {
    859	DRM_FORMAT_ARGB8888,
    860};
    861
    862static int tegra_cursor_atomic_check(struct drm_plane *plane,
    863				     struct drm_atomic_state *state)
    864{
    865	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
    866										 plane);
    867	struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);
    868	struct tegra_plane *tegra = to_tegra_plane(plane);
    869	int err;
    870
    871	plane_state->peak_memory_bandwidth = 0;
    872	plane_state->avg_memory_bandwidth = 0;
    873
    874	/* no need for further checks if the plane is being disabled */
    875	if (!new_plane_state->crtc) {
    876		plane_state->total_peak_memory_bandwidth = 0;
    877		return 0;
    878	}
    879
    880	/* scaling not supported for cursor */
    881	if ((new_plane_state->src_w >> 16 != new_plane_state->crtc_w) ||
    882	    (new_plane_state->src_h >> 16 != new_plane_state->crtc_h))
    883		return -EINVAL;
    884
    885	/* only square cursors supported */
    886	if (new_plane_state->src_w != new_plane_state->src_h)
    887		return -EINVAL;
    888
    889	if (new_plane_state->crtc_w != 32 && new_plane_state->crtc_w != 64 &&
    890	    new_plane_state->crtc_w != 128 && new_plane_state->crtc_w != 256)
    891		return -EINVAL;
    892
    893	err = tegra_plane_state_add(tegra, new_plane_state);
    894	if (err < 0)
    895		return err;
    896
    897	return 0;
    898}
    899
    900static void __tegra_cursor_atomic_update(struct drm_plane *plane,
    901					 struct drm_plane_state *new_state)
    902{
    903	struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state);
    904	struct tegra_dc *dc = to_tegra_dc(new_state->crtc);
    905	struct tegra_drm *tegra = plane->dev->dev_private;
    906#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
    907	u64 dma_mask = *dc->dev->dma_mask;
    908#endif
    909	unsigned int x, y;
    910	u32 value = 0;
    911
    912	/* rien ne va plus */
    913	if (!new_state->crtc || !new_state->fb)
    914		return;
    915
    916	/*
    917	 * Legacy display supports hardware clipping of the cursor, but
    918	 * nvdisplay relies on software to clip the cursor to the screen.
    919	 */
    920	if (!dc->soc->has_nvdisplay)
    921		value |= CURSOR_CLIP_DISPLAY;
    922
    923	switch (new_state->crtc_w) {
    924	case 32:
    925		value |= CURSOR_SIZE_32x32;
    926		break;
    927
    928	case 64:
    929		value |= CURSOR_SIZE_64x64;
    930		break;
    931
    932	case 128:
    933		value |= CURSOR_SIZE_128x128;
    934		break;
    935
    936	case 256:
    937		value |= CURSOR_SIZE_256x256;
    938		break;
    939
    940	default:
    941		WARN(1, "cursor size %ux%u not supported\n",
    942		     new_state->crtc_w, new_state->crtc_h);
    943		return;
    944	}
    945
    946	value |= (tegra_plane_state->iova[0] >> 10) & 0x3fffff;
    947	tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
    948
    949#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
    950	value = (tegra_plane_state->iova[0] >> 32) & (dma_mask >> 32);
    951	tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
    952#endif
    953
    954	/* enable cursor and set blend mode */
    955	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
    956	value |= CURSOR_ENABLE;
    957	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
    958
    959	value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
    960	value &= ~CURSOR_DST_BLEND_MASK;
    961	value &= ~CURSOR_SRC_BLEND_MASK;
    962
    963	if (dc->soc->has_nvdisplay)
    964		value &= ~CURSOR_COMPOSITION_MODE_XOR;
    965	else
    966		value |= CURSOR_MODE_NORMAL;
    967
    968	value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
    969	value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
    970	value |= CURSOR_ALPHA;
    971	tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
    972
    973	/* nvdisplay relies on software for clipping */
    974	if (dc->soc->has_nvdisplay) {
    975		struct drm_rect src;
    976
    977		x = new_state->dst.x1;
    978		y = new_state->dst.y1;
    979
    980		drm_rect_fp_to_int(&src, &new_state->src);
    981
    982		value = (src.y1 & tegra->vmask) << 16 | (src.x1 & tegra->hmask);
    983		tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR);
    984
    985		value = (drm_rect_height(&src) & tegra->vmask) << 16 |
    986			(drm_rect_width(&src) & tegra->hmask);
    987		tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR);
    988	} else {
    989		x = new_state->crtc_x;
    990		y = new_state->crtc_y;
    991	}
    992
    993	/* position the cursor */
    994	value = ((y & tegra->vmask) << 16) | (x & tegra->hmask);
    995	tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
    996}
    997
    998static void tegra_cursor_atomic_update(struct drm_plane *plane,
    999				       struct drm_atomic_state *state)
   1000{
   1001	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
   1002
   1003	__tegra_cursor_atomic_update(plane, new_state);
   1004}
   1005
   1006static void tegra_cursor_atomic_disable(struct drm_plane *plane,
   1007					struct drm_atomic_state *state)
   1008{
   1009	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
   1010									   plane);
   1011	struct tegra_dc *dc;
   1012	u32 value;
   1013
   1014	/* rien ne va plus */
   1015	if (!old_state || !old_state->crtc)
   1016		return;
   1017
   1018	dc = to_tegra_dc(old_state->crtc);
   1019
   1020	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
   1021	value &= ~CURSOR_ENABLE;
   1022	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
   1023}
   1024
   1025static int tegra_cursor_atomic_async_check(struct drm_plane *plane, struct drm_atomic_state *state)
   1026{
   1027	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
   1028	struct drm_crtc_state *crtc_state;
   1029	int min_scale, max_scale;
   1030	int err;
   1031
   1032	crtc_state = drm_atomic_get_existing_crtc_state(state, new_state->crtc);
   1033	if (WARN_ON(!crtc_state))
   1034		return -EINVAL;
   1035
   1036	if (!crtc_state->active)
   1037		return -EINVAL;
   1038
   1039	if (plane->state->crtc != new_state->crtc ||
   1040	    plane->state->src_w != new_state->src_w ||
   1041	    plane->state->src_h != new_state->src_h ||
   1042	    plane->state->crtc_w != new_state->crtc_w ||
   1043	    plane->state->crtc_h != new_state->crtc_h ||
   1044	    plane->state->fb != new_state->fb ||
   1045	    plane->state->fb == NULL)
   1046		return -EINVAL;
   1047
   1048	min_scale = (1 << 16) / 8;
   1049	max_scale = (8 << 16) / 1;
   1050
   1051	err = drm_atomic_helper_check_plane_state(new_state, crtc_state, min_scale, max_scale,
   1052						  true, true);
   1053	if (err < 0)
   1054		return err;
   1055
   1056	if (new_state->visible != plane->state->visible)
   1057		return -EINVAL;
   1058
   1059	return 0;
   1060}
   1061
   1062static void tegra_cursor_atomic_async_update(struct drm_plane *plane,
   1063					     struct drm_atomic_state *state)
   1064{
   1065	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
   1066	struct tegra_dc *dc = to_tegra_dc(new_state->crtc);
   1067
   1068	plane->state->src_x = new_state->src_x;
   1069	plane->state->src_y = new_state->src_y;
   1070	plane->state->crtc_x = new_state->crtc_x;
   1071	plane->state->crtc_y = new_state->crtc_y;
   1072
   1073	if (new_state->visible) {
   1074		struct tegra_plane *p = to_tegra_plane(plane);
   1075		u32 value;
   1076
   1077		__tegra_cursor_atomic_update(plane, new_state);
   1078
   1079		value = (WIN_A_ACT_REQ << p->index) << 8 | GENERAL_UPDATE;
   1080		tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
   1081		(void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
   1082
   1083		value = (WIN_A_ACT_REQ << p->index) | GENERAL_ACT_REQ;
   1084		tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
   1085		(void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
   1086	}
   1087}
   1088
   1089static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
   1090	.prepare_fb = tegra_plane_prepare_fb,
   1091	.cleanup_fb = tegra_plane_cleanup_fb,
   1092	.atomic_check = tegra_cursor_atomic_check,
   1093	.atomic_update = tegra_cursor_atomic_update,
   1094	.atomic_disable = tegra_cursor_atomic_disable,
   1095	.atomic_async_check = tegra_cursor_atomic_async_check,
   1096	.atomic_async_update = tegra_cursor_atomic_async_update,
   1097};
   1098
   1099static const uint64_t linear_modifiers[] = {
   1100	DRM_FORMAT_MOD_LINEAR,
   1101	DRM_FORMAT_MOD_INVALID
   1102};
   1103
   1104static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
   1105						      struct tegra_dc *dc)
   1106{
   1107	unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
   1108	struct tegra_plane *plane;
   1109	unsigned int num_formats;
   1110	const u32 *formats;
   1111	int err;
   1112
   1113	plane = kzalloc(sizeof(*plane), GFP_KERNEL);
   1114	if (!plane)
   1115		return ERR_PTR(-ENOMEM);
   1116
   1117	/*
   1118	 * This index is kind of fake. The cursor isn't a regular plane, but
   1119	 * its update and activation request bits in DC_CMD_STATE_CONTROL do
   1120	 * use the same programming. Setting this fake index here allows the
   1121	 * code in tegra_add_plane_state() to do the right thing without the
   1122	 * need to special-casing the cursor plane.
   1123	 */
   1124	plane->index = 6;
   1125	plane->dc = dc;
   1126
   1127	if (!dc->soc->has_nvdisplay) {
   1128		num_formats = ARRAY_SIZE(tegra_legacy_cursor_plane_formats);
   1129		formats = tegra_legacy_cursor_plane_formats;
   1130
   1131		err = tegra_plane_interconnect_init(plane);
   1132		if (err) {
   1133			kfree(plane);
   1134			return ERR_PTR(err);
   1135		}
   1136	} else {
   1137		num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
   1138		formats = tegra_cursor_plane_formats;
   1139	}
   1140
   1141	err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
   1142				       &tegra_plane_funcs, formats,
   1143				       num_formats, linear_modifiers,
   1144				       DRM_PLANE_TYPE_CURSOR, NULL);
   1145	if (err < 0) {
   1146		kfree(plane);
   1147		return ERR_PTR(err);
   1148	}
   1149
   1150	drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
   1151	drm_plane_create_zpos_immutable_property(&plane->base, 255);
   1152
   1153	return &plane->base;
   1154}
   1155
   1156static const u32 tegra20_overlay_formats[] = {
   1157	DRM_FORMAT_ARGB4444,
   1158	DRM_FORMAT_ARGB1555,
   1159	DRM_FORMAT_RGB565,
   1160	DRM_FORMAT_RGBA5551,
   1161	DRM_FORMAT_ABGR8888,
   1162	DRM_FORMAT_ARGB8888,
   1163	/* non-native formats */
   1164	DRM_FORMAT_XRGB1555,
   1165	DRM_FORMAT_RGBX5551,
   1166	DRM_FORMAT_XBGR8888,
   1167	DRM_FORMAT_XRGB8888,
   1168	/* planar formats */
   1169	DRM_FORMAT_UYVY,
   1170	DRM_FORMAT_YUYV,
   1171	DRM_FORMAT_YUV420,
   1172	DRM_FORMAT_YUV422,
   1173};
   1174
   1175static const u32 tegra114_overlay_formats[] = {
   1176	DRM_FORMAT_ARGB4444,
   1177	DRM_FORMAT_ARGB1555,
   1178	DRM_FORMAT_RGB565,
   1179	DRM_FORMAT_RGBA5551,
   1180	DRM_FORMAT_ABGR8888,
   1181	DRM_FORMAT_ARGB8888,
   1182	/* new on Tegra114 */
   1183	DRM_FORMAT_ABGR4444,
   1184	DRM_FORMAT_ABGR1555,
   1185	DRM_FORMAT_BGRA5551,
   1186	DRM_FORMAT_XRGB1555,
   1187	DRM_FORMAT_RGBX5551,
   1188	DRM_FORMAT_XBGR1555,
   1189	DRM_FORMAT_BGRX5551,
   1190	DRM_FORMAT_BGR565,
   1191	DRM_FORMAT_BGRA8888,
   1192	DRM_FORMAT_RGBA8888,
   1193	DRM_FORMAT_XRGB8888,
   1194	DRM_FORMAT_XBGR8888,
   1195	/* planar formats */
   1196	DRM_FORMAT_UYVY,
   1197	DRM_FORMAT_YUYV,
   1198	DRM_FORMAT_YUV420,
   1199	DRM_FORMAT_YUV422,
   1200	/* semi-planar formats */
   1201	DRM_FORMAT_NV12,
   1202	DRM_FORMAT_NV21,
   1203	DRM_FORMAT_NV16,
   1204	DRM_FORMAT_NV61,
   1205	DRM_FORMAT_NV24,
   1206	DRM_FORMAT_NV42,
   1207};
   1208
   1209static const u32 tegra124_overlay_formats[] = {
   1210	DRM_FORMAT_ARGB4444,
   1211	DRM_FORMAT_ARGB1555,
   1212	DRM_FORMAT_RGB565,
   1213	DRM_FORMAT_RGBA5551,
   1214	DRM_FORMAT_ABGR8888,
   1215	DRM_FORMAT_ARGB8888,
   1216	/* new on Tegra114 */
   1217	DRM_FORMAT_ABGR4444,
   1218	DRM_FORMAT_ABGR1555,
   1219	DRM_FORMAT_BGRA5551,
   1220	DRM_FORMAT_XRGB1555,
   1221	DRM_FORMAT_RGBX5551,
   1222	DRM_FORMAT_XBGR1555,
   1223	DRM_FORMAT_BGRX5551,
   1224	DRM_FORMAT_BGR565,
   1225	DRM_FORMAT_BGRA8888,
   1226	DRM_FORMAT_RGBA8888,
   1227	DRM_FORMAT_XRGB8888,
   1228	DRM_FORMAT_XBGR8888,
   1229	/* new on Tegra124 */
   1230	DRM_FORMAT_RGBX8888,
   1231	DRM_FORMAT_BGRX8888,
   1232	/* planar formats */
   1233	DRM_FORMAT_UYVY,
   1234	DRM_FORMAT_YUYV,
   1235	DRM_FORMAT_YVYU,
   1236	DRM_FORMAT_VYUY,
   1237	DRM_FORMAT_YUV420, /* YU12 */
   1238	DRM_FORMAT_YUV422, /* YU16 */
   1239	DRM_FORMAT_YUV444, /* YU24 */
   1240	/* semi-planar formats */
   1241	DRM_FORMAT_NV12,
   1242	DRM_FORMAT_NV21,
   1243	DRM_FORMAT_NV16,
   1244	DRM_FORMAT_NV61,
   1245	DRM_FORMAT_NV24,
   1246	DRM_FORMAT_NV42,
   1247};
   1248
   1249static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
   1250						       struct tegra_dc *dc,
   1251						       unsigned int index,
   1252						       bool cursor)
   1253{
   1254	unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
   1255	struct tegra_plane *plane;
   1256	unsigned int num_formats;
   1257	enum drm_plane_type type;
   1258	const u32 *formats;
   1259	int err;
   1260
   1261	plane = kzalloc(sizeof(*plane), GFP_KERNEL);
   1262	if (!plane)
   1263		return ERR_PTR(-ENOMEM);
   1264
   1265	plane->offset = 0xa00 + 0x200 * index;
   1266	plane->index = index;
   1267	plane->dc = dc;
   1268
   1269	num_formats = dc->soc->num_overlay_formats;
   1270	formats = dc->soc->overlay_formats;
   1271
   1272	err = tegra_plane_interconnect_init(plane);
   1273	if (err) {
   1274		kfree(plane);
   1275		return ERR_PTR(err);
   1276	}
   1277
   1278	if (!cursor)
   1279		type = DRM_PLANE_TYPE_OVERLAY;
   1280	else
   1281		type = DRM_PLANE_TYPE_CURSOR;
   1282
   1283	err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
   1284				       &tegra_plane_funcs, formats,
   1285				       num_formats, linear_modifiers,
   1286				       type, NULL);
   1287	if (err < 0) {
   1288		kfree(plane);
   1289		return ERR_PTR(err);
   1290	}
   1291
   1292	drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
   1293	drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
   1294
   1295	err = drm_plane_create_rotation_property(&plane->base,
   1296						 DRM_MODE_ROTATE_0,
   1297						 DRM_MODE_ROTATE_0 |
   1298						 DRM_MODE_ROTATE_180 |
   1299						 DRM_MODE_REFLECT_X |
   1300						 DRM_MODE_REFLECT_Y);
   1301	if (err < 0)
   1302		dev_err(dc->dev, "failed to create rotation property: %d\n",
   1303			err);
   1304
   1305	return &plane->base;
   1306}
   1307
   1308static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
   1309						    struct tegra_dc *dc)
   1310{
   1311	struct drm_plane *plane, *primary = NULL;
   1312	unsigned int i, j;
   1313
   1314	for (i = 0; i < dc->soc->num_wgrps; i++) {
   1315		const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
   1316
   1317		if (wgrp->dc == dc->pipe) {
   1318			for (j = 0; j < wgrp->num_windows; j++) {
   1319				unsigned int index = wgrp->windows[j];
   1320
   1321				plane = tegra_shared_plane_create(drm, dc,
   1322								  wgrp->index,
   1323								  index);
   1324				if (IS_ERR(plane))
   1325					return plane;
   1326
   1327				/*
   1328				 * Choose the first shared plane owned by this
   1329				 * head as the primary plane.
   1330				 */
   1331				if (!primary) {
   1332					plane->type = DRM_PLANE_TYPE_PRIMARY;
   1333					primary = plane;
   1334				}
   1335			}
   1336		}
   1337	}
   1338
   1339	return primary;
   1340}
   1341
   1342static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
   1343					     struct tegra_dc *dc)
   1344{
   1345	struct drm_plane *planes[2], *primary;
   1346	unsigned int planes_num;
   1347	unsigned int i;
   1348	int err;
   1349
   1350	primary = tegra_primary_plane_create(drm, dc);
   1351	if (IS_ERR(primary))
   1352		return primary;
   1353
   1354	if (dc->soc->supports_cursor)
   1355		planes_num = 2;
   1356	else
   1357		planes_num = 1;
   1358
   1359	for (i = 0; i < planes_num; i++) {
   1360		planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
   1361							  false);
   1362		if (IS_ERR(planes[i])) {
   1363			err = PTR_ERR(planes[i]);
   1364
   1365			while (i--)
   1366				planes[i]->funcs->destroy(planes[i]);
   1367
   1368			primary->funcs->destroy(primary);
   1369			return ERR_PTR(err);
   1370		}
   1371	}
   1372
   1373	return primary;
   1374}
   1375
   1376static void tegra_dc_destroy(struct drm_crtc *crtc)
   1377{
   1378	drm_crtc_cleanup(crtc);
   1379}
   1380
   1381static void tegra_crtc_reset(struct drm_crtc *crtc)
   1382{
   1383	struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
   1384
   1385	if (crtc->state)
   1386		tegra_crtc_atomic_destroy_state(crtc, crtc->state);
   1387
   1388	__drm_atomic_helper_crtc_reset(crtc, &state->base);
   1389}
   1390
   1391static struct drm_crtc_state *
   1392tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
   1393{
   1394	struct tegra_dc_state *state = to_dc_state(crtc->state);
   1395	struct tegra_dc_state *copy;
   1396
   1397	copy = kmalloc(sizeof(*copy), GFP_KERNEL);
   1398	if (!copy)
   1399		return NULL;
   1400
   1401	__drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
   1402	copy->clk = state->clk;
   1403	copy->pclk = state->pclk;
   1404	copy->div = state->div;
   1405	copy->planes = state->planes;
   1406
   1407	return &copy->base;
   1408}
   1409
   1410static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
   1411					    struct drm_crtc_state *state)
   1412{
   1413	__drm_atomic_helper_crtc_destroy_state(state);
   1414	kfree(state);
   1415}
   1416
   1417#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
   1418
   1419static const struct debugfs_reg32 tegra_dc_regs[] = {
   1420	DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
   1421	DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
   1422	DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
   1423	DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
   1424	DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
   1425	DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
   1426	DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
   1427	DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
   1428	DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
   1429	DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
   1430	DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
   1431	DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
   1432	DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
   1433	DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
   1434	DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
   1435	DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
   1436	DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
   1437	DEBUGFS_REG32(DC_CMD_INT_STATUS),
   1438	DEBUGFS_REG32(DC_CMD_INT_MASK),
   1439	DEBUGFS_REG32(DC_CMD_INT_ENABLE),
   1440	DEBUGFS_REG32(DC_CMD_INT_TYPE),
   1441	DEBUGFS_REG32(DC_CMD_INT_POLARITY),
   1442	DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
   1443	DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
   1444	DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
   1445	DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
   1446	DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
   1447	DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
   1448	DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
   1449	DEBUGFS_REG32(DC_COM_CRC_CONTROL),
   1450	DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
   1451	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
   1452	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
   1453	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
   1454	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
   1455	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
   1456	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
   1457	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
   1458	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
   1459	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
   1460	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
   1461	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
   1462	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
   1463	DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
   1464	DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
   1465	DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
   1466	DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
   1467	DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
   1468	DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
   1469	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
   1470	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
   1471	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
   1472	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
   1473	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
   1474	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
   1475	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
   1476	DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
   1477	DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
   1478	DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
   1479	DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
   1480	DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
   1481	DEBUGFS_REG32(DC_COM_SPI_CONTROL),
   1482	DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
   1483	DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
   1484	DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
   1485	DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
   1486	DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
   1487	DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
   1488	DEBUGFS_REG32(DC_COM_GPIO_CTRL),
   1489	DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
   1490	DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
   1491	DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
   1492	DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
   1493	DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
   1494	DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
   1495	DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
   1496	DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
   1497	DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
   1498	DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
   1499	DEBUGFS_REG32(DC_DISP_BACK_PORCH),
   1500	DEBUGFS_REG32(DC_DISP_ACTIVE),
   1501	DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
   1502	DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
   1503	DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
   1504	DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
   1505	DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
   1506	DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
   1507	DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
   1508	DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
   1509	DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
   1510	DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
   1511	DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
   1512	DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
   1513	DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
   1514	DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
   1515	DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
   1516	DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
   1517	DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
   1518	DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
   1519	DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
   1520	DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
   1521	DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
   1522	DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
   1523	DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
   1524	DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
   1525	DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
   1526	DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
   1527	DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
   1528	DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
   1529	DEBUGFS_REG32(DC_DISP_M0_CONTROL),
   1530	DEBUGFS_REG32(DC_DISP_M1_CONTROL),
   1531	DEBUGFS_REG32(DC_DISP_DI_CONTROL),
   1532	DEBUGFS_REG32(DC_DISP_PP_CONTROL),
   1533	DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
   1534	DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
   1535	DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
   1536	DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
   1537	DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
   1538	DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
   1539	DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
   1540	DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
   1541	DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
   1542	DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
   1543	DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
   1544	DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
   1545	DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
   1546	DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
   1547	DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
   1548	DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
   1549	DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
   1550	DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
   1551	DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
   1552	DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
   1553	DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
   1554	DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
   1555	DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
   1556	DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
   1557	DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
   1558	DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
   1559	DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
   1560	DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
   1561	DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
   1562	DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
   1563	DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
   1564	DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
   1565	DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
   1566	DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
   1567	DEBUGFS_REG32(DC_DISP_SD_CONTROL),
   1568	DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
   1569	DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
   1570	DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
   1571	DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
   1572	DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
   1573	DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
   1574	DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
   1575	DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
   1576	DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
   1577	DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
   1578	DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
   1579	DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
   1580	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
   1581	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
   1582	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
   1583	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
   1584	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
   1585	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
   1586	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
   1587	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
   1588	DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
   1589	DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
   1590	DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
   1591	DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
   1592	DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
   1593	DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
   1594	DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
   1595	DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
   1596	DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
   1597	DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
   1598	DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
   1599	DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
   1600	DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
   1601	DEBUGFS_REG32(DC_WIN_POSITION),
   1602	DEBUGFS_REG32(DC_WIN_SIZE),
   1603	DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
   1604	DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
   1605	DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
   1606	DEBUGFS_REG32(DC_WIN_DDA_INC),
   1607	DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
   1608	DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
   1609	DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
   1610	DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
   1611	DEBUGFS_REG32(DC_WIN_DV_CONTROL),
   1612	DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
   1613	DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
   1614	DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
   1615	DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
   1616	DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
   1617	DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
   1618	DEBUGFS_REG32(DC_WINBUF_START_ADDR),
   1619	DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
   1620	DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
   1621	DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
   1622	DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
   1623	DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
   1624	DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
   1625	DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
   1626	DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
   1627	DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
   1628	DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
   1629	DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
   1630	DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
   1631	DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
   1632};
   1633
   1634static int tegra_dc_show_regs(struct seq_file *s, void *data)
   1635{
   1636	struct drm_info_node *node = s->private;
   1637	struct tegra_dc *dc = node->info_ent->data;
   1638	unsigned int i;
   1639	int err = 0;
   1640
   1641	drm_modeset_lock(&dc->base.mutex, NULL);
   1642
   1643	if (!dc->base.state->active) {
   1644		err = -EBUSY;
   1645		goto unlock;
   1646	}
   1647
   1648	for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
   1649		unsigned int offset = tegra_dc_regs[i].offset;
   1650
   1651		seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
   1652			   offset, tegra_dc_readl(dc, offset));
   1653	}
   1654
   1655unlock:
   1656	drm_modeset_unlock(&dc->base.mutex);
   1657	return err;
   1658}
   1659
   1660static int tegra_dc_show_crc(struct seq_file *s, void *data)
   1661{
   1662	struct drm_info_node *node = s->private;
   1663	struct tegra_dc *dc = node->info_ent->data;
   1664	int err = 0;
   1665	u32 value;
   1666
   1667	drm_modeset_lock(&dc->base.mutex, NULL);
   1668
   1669	if (!dc->base.state->active) {
   1670		err = -EBUSY;
   1671		goto unlock;
   1672	}
   1673
   1674	value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
   1675	tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
   1676	tegra_dc_commit(dc);
   1677
   1678	drm_crtc_wait_one_vblank(&dc->base);
   1679	drm_crtc_wait_one_vblank(&dc->base);
   1680
   1681	value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
   1682	seq_printf(s, "%08x\n", value);
   1683
   1684	tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
   1685
   1686unlock:
   1687	drm_modeset_unlock(&dc->base.mutex);
   1688	return err;
   1689}
   1690
   1691static int tegra_dc_show_stats(struct seq_file *s, void *data)
   1692{
   1693	struct drm_info_node *node = s->private;
   1694	struct tegra_dc *dc = node->info_ent->data;
   1695
   1696	seq_printf(s, "frames: %lu\n", dc->stats.frames);
   1697	seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
   1698	seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
   1699	seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
   1700
   1701	seq_printf(s, "frames total: %lu\n", dc->stats.frames_total);
   1702	seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total);
   1703	seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total);
   1704	seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total);
   1705
   1706	return 0;
   1707}
   1708
   1709static struct drm_info_list debugfs_files[] = {
   1710	{ "regs", tegra_dc_show_regs, 0, NULL },
   1711	{ "crc", tegra_dc_show_crc, 0, NULL },
   1712	{ "stats", tegra_dc_show_stats, 0, NULL },
   1713};
   1714
   1715static int tegra_dc_late_register(struct drm_crtc *crtc)
   1716{
   1717	unsigned int i, count = ARRAY_SIZE(debugfs_files);
   1718	struct drm_minor *minor = crtc->dev->primary;
   1719	struct dentry *root;
   1720	struct tegra_dc *dc = to_tegra_dc(crtc);
   1721
   1722#ifdef CONFIG_DEBUG_FS
   1723	root = crtc->debugfs_entry;
   1724#else
   1725	root = NULL;
   1726#endif
   1727
   1728	dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
   1729				    GFP_KERNEL);
   1730	if (!dc->debugfs_files)
   1731		return -ENOMEM;
   1732
   1733	for (i = 0; i < count; i++)
   1734		dc->debugfs_files[i].data = dc;
   1735
   1736	drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
   1737
   1738	return 0;
   1739}
   1740
   1741static void tegra_dc_early_unregister(struct drm_crtc *crtc)
   1742{
   1743	unsigned int count = ARRAY_SIZE(debugfs_files);
   1744	struct drm_minor *minor = crtc->dev->primary;
   1745	struct tegra_dc *dc = to_tegra_dc(crtc);
   1746
   1747	drm_debugfs_remove_files(dc->debugfs_files, count, minor);
   1748	kfree(dc->debugfs_files);
   1749	dc->debugfs_files = NULL;
   1750}
   1751
   1752static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
   1753{
   1754	struct tegra_dc *dc = to_tegra_dc(crtc);
   1755
   1756	/* XXX vblank syncpoints don't work with nvdisplay yet */
   1757	if (dc->syncpt && !dc->soc->has_nvdisplay)
   1758		return host1x_syncpt_read(dc->syncpt);
   1759
   1760	/* fallback to software emulated VBLANK counter */
   1761	return (u32)drm_crtc_vblank_count(&dc->base);
   1762}
   1763
   1764static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
   1765{
   1766	struct tegra_dc *dc = to_tegra_dc(crtc);
   1767	u32 value;
   1768
   1769	value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
   1770	value |= VBLANK_INT;
   1771	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
   1772
   1773	return 0;
   1774}
   1775
   1776static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
   1777{
   1778	struct tegra_dc *dc = to_tegra_dc(crtc);
   1779	u32 value;
   1780
   1781	value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
   1782	value &= ~VBLANK_INT;
   1783	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
   1784}
   1785
   1786static const struct drm_crtc_funcs tegra_crtc_funcs = {
   1787	.page_flip = drm_atomic_helper_page_flip,
   1788	.set_config = drm_atomic_helper_set_config,
   1789	.destroy = tegra_dc_destroy,
   1790	.reset = tegra_crtc_reset,
   1791	.atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
   1792	.atomic_destroy_state = tegra_crtc_atomic_destroy_state,
   1793	.late_register = tegra_dc_late_register,
   1794	.early_unregister = tegra_dc_early_unregister,
   1795	.get_vblank_counter = tegra_dc_get_vblank_counter,
   1796	.enable_vblank = tegra_dc_enable_vblank,
   1797	.disable_vblank = tegra_dc_disable_vblank,
   1798};
   1799
   1800static int tegra_dc_set_timings(struct tegra_dc *dc,
   1801				struct drm_display_mode *mode)
   1802{
   1803	unsigned int h_ref_to_sync = 1;
   1804	unsigned int v_ref_to_sync = 1;
   1805	unsigned long value;
   1806
   1807	if (!dc->soc->has_nvdisplay) {
   1808		tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
   1809
   1810		value = (v_ref_to_sync << 16) | h_ref_to_sync;
   1811		tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
   1812	}
   1813
   1814	value = ((mode->vsync_end - mode->vsync_start) << 16) |
   1815		((mode->hsync_end - mode->hsync_start) <<  0);
   1816	tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
   1817
   1818	value = ((mode->vtotal - mode->vsync_end) << 16) |
   1819		((mode->htotal - mode->hsync_end) <<  0);
   1820	tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
   1821
   1822	value = ((mode->vsync_start - mode->vdisplay) << 16) |
   1823		((mode->hsync_start - mode->hdisplay) <<  0);
   1824	tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
   1825
   1826	value = (mode->vdisplay << 16) | mode->hdisplay;
   1827	tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
   1828
   1829	return 0;
   1830}
   1831
   1832/**
   1833 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
   1834 *     state
   1835 * @dc: display controller
   1836 * @crtc_state: CRTC atomic state
   1837 * @clk: parent clock for display controller
   1838 * @pclk: pixel clock
   1839 * @div: shift clock divider
   1840 *
   1841 * Returns:
   1842 * 0 on success or a negative error-code on failure.
   1843 */
   1844int tegra_dc_state_setup_clock(struct tegra_dc *dc,
   1845			       struct drm_crtc_state *crtc_state,
   1846			       struct clk *clk, unsigned long pclk,
   1847			       unsigned int div)
   1848{
   1849	struct tegra_dc_state *state = to_dc_state(crtc_state);
   1850
   1851	if (!clk_has_parent(dc->clk, clk))
   1852		return -EINVAL;
   1853
   1854	state->clk = clk;
   1855	state->pclk = pclk;
   1856	state->div = div;
   1857
   1858	return 0;
   1859}
   1860
   1861static void tegra_dc_update_voltage_state(struct tegra_dc *dc,
   1862					  struct tegra_dc_state *state)
   1863{
   1864	unsigned long rate, pstate;
   1865	struct dev_pm_opp *opp;
   1866	int err;
   1867
   1868	if (!dc->has_opp_table)
   1869		return;
   1870
   1871	/* calculate actual pixel clock rate which depends on internal divider */
   1872	rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2);
   1873
   1874	/* find suitable OPP for the rate */
   1875	opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate);
   1876
   1877	/*
   1878	 * Very high resolution modes may results in a clock rate that is
   1879	 * above the characterized maximum. In this case it's okay to fall
   1880	 * back to the characterized maximum.
   1881	 */
   1882	if (opp == ERR_PTR(-ERANGE))
   1883		opp = dev_pm_opp_find_freq_floor(dc->dev, &rate);
   1884
   1885	if (IS_ERR(opp)) {
   1886		dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n",
   1887			rate, opp);
   1888		return;
   1889	}
   1890
   1891	pstate = dev_pm_opp_get_required_pstate(opp, 0);
   1892	dev_pm_opp_put(opp);
   1893
   1894	/*
   1895	 * The minimum core voltage depends on the pixel clock rate (which
   1896	 * depends on internal clock divider of the CRTC) and not on the
   1897	 * rate of the display controller clock. This is why we're not using
   1898	 * dev_pm_opp_set_rate() API and instead controlling the power domain
   1899	 * directly.
   1900	 */
   1901	err = dev_pm_genpd_set_performance_state(dc->dev, pstate);
   1902	if (err)
   1903		dev_err(dc->dev, "failed to set power domain state to %lu: %d\n",
   1904			pstate, err);
   1905}
   1906
   1907static void tegra_dc_set_clock_rate(struct tegra_dc *dc,
   1908				    struct tegra_dc_state *state)
   1909{
   1910	int err;
   1911
   1912	err = clk_set_parent(dc->clk, state->clk);
   1913	if (err < 0)
   1914		dev_err(dc->dev, "failed to set parent clock: %d\n", err);
   1915
   1916	/*
   1917	 * Outputs may not want to change the parent clock rate. This is only
   1918	 * relevant to Tegra20 where only a single display PLL is available.
   1919	 * Since that PLL would typically be used for HDMI, an internal LVDS
   1920	 * panel would need to be driven by some other clock such as PLL_P
   1921	 * which is shared with other peripherals. Changing the clock rate
   1922	 * should therefore be avoided.
   1923	 */
   1924	if (state->pclk > 0) {
   1925		err = clk_set_rate(state->clk, state->pclk);
   1926		if (err < 0)
   1927			dev_err(dc->dev,
   1928				"failed to set clock rate to %lu Hz\n",
   1929				state->pclk);
   1930
   1931		err = clk_set_rate(dc->clk, state->pclk);
   1932		if (err < 0)
   1933			dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
   1934				dc->clk, state->pclk, err);
   1935	}
   1936
   1937	DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
   1938		      state->div);
   1939	DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
   1940
   1941	tegra_dc_update_voltage_state(dc, state);
   1942}
   1943
   1944static void tegra_dc_stop(struct tegra_dc *dc)
   1945{
   1946	u32 value;
   1947
   1948	/* stop the display controller */
   1949	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
   1950	value &= ~DISP_CTRL_MODE_MASK;
   1951	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
   1952
   1953	tegra_dc_commit(dc);
   1954}
   1955
   1956static bool tegra_dc_idle(struct tegra_dc *dc)
   1957{
   1958	u32 value;
   1959
   1960	value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
   1961
   1962	return (value & DISP_CTRL_MODE_MASK) == 0;
   1963}
   1964
   1965static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
   1966{
   1967	timeout = jiffies + msecs_to_jiffies(timeout);
   1968
   1969	while (time_before(jiffies, timeout)) {
   1970		if (tegra_dc_idle(dc))
   1971			return 0;
   1972
   1973		usleep_range(1000, 2000);
   1974	}
   1975
   1976	dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
   1977	return -ETIMEDOUT;
   1978}
   1979
   1980static void
   1981tegra_crtc_update_memory_bandwidth(struct drm_crtc *crtc,
   1982				   struct drm_atomic_state *state,
   1983				   bool prepare_bandwidth_transition)
   1984{
   1985	const struct tegra_plane_state *old_tegra_state, *new_tegra_state;
   1986	u32 i, new_avg_bw, old_avg_bw, new_peak_bw, old_peak_bw;
   1987	const struct drm_plane_state *old_plane_state;
   1988	const struct drm_crtc_state *old_crtc_state;
   1989	struct tegra_dc_window window, old_window;
   1990	struct tegra_dc *dc = to_tegra_dc(crtc);
   1991	struct tegra_plane *tegra;
   1992	struct drm_plane *plane;
   1993
   1994	if (dc->soc->has_nvdisplay)
   1995		return;
   1996
   1997	old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
   1998
   1999	if (!crtc->state->active) {
   2000		if (!old_crtc_state->active)
   2001			return;
   2002
   2003		/*
   2004		 * When CRTC is disabled on DPMS, the state of attached planes
   2005		 * is kept unchanged. Hence we need to enforce removal of the
   2006		 * bandwidths from the ICC paths.
   2007		 */
   2008		drm_atomic_crtc_for_each_plane(plane, crtc) {
   2009			tegra = to_tegra_plane(plane);
   2010
   2011			icc_set_bw(tegra->icc_mem, 0, 0);
   2012			icc_set_bw(tegra->icc_mem_vfilter, 0, 0);
   2013		}
   2014
   2015		return;
   2016	}
   2017
   2018	for_each_old_plane_in_state(old_crtc_state->state, plane,
   2019				    old_plane_state, i) {
   2020		old_tegra_state = to_const_tegra_plane_state(old_plane_state);
   2021		new_tegra_state = to_const_tegra_plane_state(plane->state);
   2022		tegra = to_tegra_plane(plane);
   2023
   2024		/*
   2025		 * We're iterating over the global atomic state and it contains
   2026		 * planes from another CRTC, hence we need to filter out the
   2027		 * planes unrelated to this CRTC.
   2028		 */
   2029		if (tegra->dc != dc)
   2030			continue;
   2031
   2032		new_avg_bw = new_tegra_state->avg_memory_bandwidth;
   2033		old_avg_bw = old_tegra_state->avg_memory_bandwidth;
   2034
   2035		new_peak_bw = new_tegra_state->total_peak_memory_bandwidth;
   2036		old_peak_bw = old_tegra_state->total_peak_memory_bandwidth;
   2037
   2038		/*
   2039		 * See the comment related to !crtc->state->active above,
   2040		 * which explains why bandwidths need to be updated when
   2041		 * CRTC is turning ON.
   2042		 */
   2043		if (new_avg_bw == old_avg_bw && new_peak_bw == old_peak_bw &&
   2044		    old_crtc_state->active)
   2045			continue;
   2046
   2047		window.src.h = drm_rect_height(&plane->state->src) >> 16;
   2048		window.dst.h = drm_rect_height(&plane->state->dst);
   2049
   2050		old_window.src.h = drm_rect_height(&old_plane_state->src) >> 16;
   2051		old_window.dst.h = drm_rect_height(&old_plane_state->dst);
   2052
   2053		/*
   2054		 * During the preparation phase (atomic_begin), the memory
   2055		 * freq should go high before the DC changes are committed
   2056		 * if bandwidth requirement goes up, otherwise memory freq
   2057		 * should to stay high if BW requirement goes down.  The
   2058		 * opposite applies to the completion phase (post_commit).
   2059		 */
   2060		if (prepare_bandwidth_transition) {
   2061			new_avg_bw = max(old_avg_bw, new_avg_bw);
   2062			new_peak_bw = max(old_peak_bw, new_peak_bw);
   2063
   2064			if (tegra_plane_use_vertical_filtering(tegra, &old_window))
   2065				window = old_window;
   2066		}
   2067
   2068		icc_set_bw(tegra->icc_mem, new_avg_bw, new_peak_bw);
   2069
   2070		if (tegra_plane_use_vertical_filtering(tegra, &window))
   2071			icc_set_bw(tegra->icc_mem_vfilter, new_avg_bw, new_peak_bw);
   2072		else
   2073			icc_set_bw(tegra->icc_mem_vfilter, 0, 0);
   2074	}
   2075}
   2076
   2077static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
   2078				      struct drm_atomic_state *state)
   2079{
   2080	struct tegra_dc *dc = to_tegra_dc(crtc);
   2081	u32 value;
   2082	int err;
   2083
   2084	if (!tegra_dc_idle(dc)) {
   2085		tegra_dc_stop(dc);
   2086
   2087		/*
   2088		 * Ignore the return value, there isn't anything useful to do
   2089		 * in case this fails.
   2090		 */
   2091		tegra_dc_wait_idle(dc, 100);
   2092	}
   2093
   2094	/*
   2095	 * This should really be part of the RGB encoder driver, but clearing
   2096	 * these bits has the side-effect of stopping the display controller.
   2097	 * When that happens no VBLANK interrupts will be raised. At the same
   2098	 * time the encoder is disabled before the display controller, so the
   2099	 * above code is always going to timeout waiting for the controller
   2100	 * to go idle.
   2101	 *
   2102	 * Given the close coupling between the RGB encoder and the display
   2103	 * controller doing it here is still kind of okay. None of the other
   2104	 * encoder drivers require these bits to be cleared.
   2105	 *
   2106	 * XXX: Perhaps given that the display controller is switched off at
   2107	 * this point anyway maybe clearing these bits isn't even useful for
   2108	 * the RGB encoder?
   2109	 */
   2110	if (dc->rgb) {
   2111		value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
   2112		value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
   2113			   PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
   2114		tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
   2115	}
   2116
   2117	tegra_dc_stats_reset(&dc->stats);
   2118	drm_crtc_vblank_off(crtc);
   2119
   2120	spin_lock_irq(&crtc->dev->event_lock);
   2121
   2122	if (crtc->state->event) {
   2123		drm_crtc_send_vblank_event(crtc, crtc->state->event);
   2124		crtc->state->event = NULL;
   2125	}
   2126
   2127	spin_unlock_irq(&crtc->dev->event_lock);
   2128
   2129	err = host1x_client_suspend(&dc->client);
   2130	if (err < 0)
   2131		dev_err(dc->dev, "failed to suspend: %d\n", err);
   2132
   2133	if (dc->has_opp_table) {
   2134		err = dev_pm_genpd_set_performance_state(dc->dev, 0);
   2135		if (err)
   2136			dev_err(dc->dev,
   2137				"failed to clear power domain state: %d\n", err);
   2138	}
   2139}
   2140
   2141static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
   2142				     struct drm_atomic_state *state)
   2143{
   2144	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
   2145	struct tegra_dc_state *crtc_state = to_dc_state(crtc->state);
   2146	struct tegra_dc *dc = to_tegra_dc(crtc);
   2147	u32 value;
   2148	int err;
   2149
   2150	/* apply PLL changes */
   2151	tegra_dc_set_clock_rate(dc, crtc_state);
   2152
   2153	err = host1x_client_resume(&dc->client);
   2154	if (err < 0) {
   2155		dev_err(dc->dev, "failed to resume: %d\n", err);
   2156		return;
   2157	}
   2158
   2159	/* initialize display controller */
   2160	if (dc->syncpt) {
   2161		u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
   2162
   2163		if (dc->soc->has_nvdisplay)
   2164			enable = 1 << 31;
   2165		else
   2166			enable = 1 << 8;
   2167
   2168		value = SYNCPT_CNTRL_NO_STALL;
   2169		tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
   2170
   2171		value = enable | syncpt;
   2172		tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
   2173	}
   2174
   2175	if (dc->soc->has_nvdisplay) {
   2176		value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
   2177			DSC_OBUF_UF_INT;
   2178		tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
   2179
   2180		value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
   2181			DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
   2182			HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
   2183			REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
   2184			VBLANK_INT | FRAME_END_INT;
   2185		tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
   2186
   2187		value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
   2188			FRAME_END_INT;
   2189		tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
   2190
   2191		value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
   2192		tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
   2193
   2194		tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
   2195	} else {
   2196		value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
   2197			WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
   2198		tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
   2199
   2200		value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
   2201			WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
   2202		tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
   2203
   2204		/* initialize timer */
   2205		value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
   2206			WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
   2207		tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
   2208
   2209		value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
   2210			WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
   2211		tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
   2212
   2213		value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
   2214			WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
   2215		tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
   2216
   2217		value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
   2218			WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
   2219		tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
   2220	}
   2221
   2222	if (dc->soc->supports_background_color)
   2223		tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
   2224	else
   2225		tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
   2226
   2227	/* apply pixel clock changes */
   2228	if (!dc->soc->has_nvdisplay) {
   2229		value = SHIFT_CLK_DIVIDER(crtc_state->div) | PIXEL_CLK_DIVIDER_PCD1;
   2230		tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
   2231	}
   2232
   2233	/* program display mode */
   2234	tegra_dc_set_timings(dc, mode);
   2235
   2236	/* interlacing isn't supported yet, so disable it */
   2237	if (dc->soc->supports_interlacing) {
   2238		value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
   2239		value &= ~INTERLACE_ENABLE;
   2240		tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
   2241	}
   2242
   2243	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
   2244	value &= ~DISP_CTRL_MODE_MASK;
   2245	value |= DISP_CTRL_MODE_C_DISPLAY;
   2246	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
   2247
   2248	if (!dc->soc->has_nvdisplay) {
   2249		value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
   2250		value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
   2251			 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
   2252		tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
   2253	}
   2254
   2255	/* enable underflow reporting and display red for missing pixels */
   2256	if (dc->soc->has_nvdisplay) {
   2257		value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
   2258		tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
   2259	}
   2260
   2261	if (dc->rgb) {
   2262		/* XXX: parameterize? */
   2263		value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
   2264		tegra_dc_writel(dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
   2265	}
   2266
   2267	tegra_dc_commit(dc);
   2268
   2269	drm_crtc_vblank_on(crtc);
   2270}
   2271
   2272static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
   2273				    struct drm_atomic_state *state)
   2274{
   2275	unsigned long flags;
   2276
   2277	tegra_crtc_update_memory_bandwidth(crtc, state, true);
   2278
   2279	if (crtc->state->event) {
   2280		spin_lock_irqsave(&crtc->dev->event_lock, flags);
   2281
   2282		if (drm_crtc_vblank_get(crtc) != 0)
   2283			drm_crtc_send_vblank_event(crtc, crtc->state->event);
   2284		else
   2285			drm_crtc_arm_vblank_event(crtc, crtc->state->event);
   2286
   2287		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
   2288
   2289		crtc->state->event = NULL;
   2290	}
   2291}
   2292
   2293static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
   2294				    struct drm_atomic_state *state)
   2295{
   2296	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
   2297									  crtc);
   2298	struct tegra_dc_state *dc_state = to_dc_state(crtc_state);
   2299	struct tegra_dc *dc = to_tegra_dc(crtc);
   2300	u32 value;
   2301
   2302	value = dc_state->planes << 8 | GENERAL_UPDATE;
   2303	tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
   2304	value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
   2305
   2306	value = dc_state->planes | GENERAL_ACT_REQ;
   2307	tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
   2308	value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
   2309}
   2310
   2311static bool tegra_plane_is_cursor(const struct drm_plane_state *state)
   2312{
   2313	const struct tegra_dc_soc_info *soc = to_tegra_dc(state->crtc)->soc;
   2314	const struct drm_format_info *fmt = state->fb->format;
   2315	unsigned int src_w = drm_rect_width(&state->src) >> 16;
   2316	unsigned int dst_w = drm_rect_width(&state->dst);
   2317
   2318	if (state->plane->type != DRM_PLANE_TYPE_CURSOR)
   2319		return false;
   2320
   2321	if (soc->supports_cursor)
   2322		return true;
   2323
   2324	if (src_w != dst_w || fmt->num_planes != 1 || src_w * fmt->cpp[0] > 256)
   2325		return false;
   2326
   2327	return true;
   2328}
   2329
   2330static unsigned long
   2331tegra_plane_overlap_mask(struct drm_crtc_state *state,
   2332			 const struct drm_plane_state *plane_state)
   2333{
   2334	const struct drm_plane_state *other_state;
   2335	const struct tegra_plane *tegra;
   2336	unsigned long overlap_mask = 0;
   2337	struct drm_plane *plane;
   2338	struct drm_rect rect;
   2339
   2340	if (!plane_state->visible || !plane_state->fb)
   2341		return 0;
   2342
   2343	/*
   2344	 * Data-prefetch FIFO will easily help to overcome temporal memory
   2345	 * pressure if other plane overlaps with the cursor plane.
   2346	 */
   2347	if (tegra_plane_is_cursor(plane_state))
   2348		return 0;
   2349
   2350	drm_atomic_crtc_state_for_each_plane_state(plane, other_state, state) {
   2351		rect = plane_state->dst;
   2352
   2353		tegra = to_tegra_plane(other_state->plane);
   2354
   2355		if (!other_state->visible || !other_state->fb)
   2356			continue;
   2357
   2358		/*
   2359		 * Ignore cursor plane overlaps because it's not practical to
   2360		 * assume that it contributes to the bandwidth in overlapping
   2361		 * area if window width is small.
   2362		 */
   2363		if (tegra_plane_is_cursor(other_state))
   2364			continue;
   2365
   2366		if (drm_rect_intersect(&rect, &other_state->dst))
   2367			overlap_mask |= BIT(tegra->index);
   2368	}
   2369
   2370	return overlap_mask;
   2371}
   2372
   2373static int tegra_crtc_calculate_memory_bandwidth(struct drm_crtc *crtc,
   2374						 struct drm_atomic_state *state)
   2375{
   2376	ulong overlap_mask[TEGRA_DC_LEGACY_PLANES_NUM] = {}, mask;
   2377	u32 plane_peak_bw[TEGRA_DC_LEGACY_PLANES_NUM] = {};
   2378	bool all_planes_overlap_simultaneously = true;
   2379	const struct tegra_plane_state *tegra_state;
   2380	const struct drm_plane_state *plane_state;
   2381	struct tegra_dc *dc = to_tegra_dc(crtc);
   2382	const struct drm_crtc_state *old_state;
   2383	struct drm_crtc_state *new_state;
   2384	struct tegra_plane *tegra;
   2385	struct drm_plane *plane;
   2386
   2387	/*
   2388	 * The nv-display uses shared planes.  The algorithm below assumes
   2389	 * maximum 3 planes per-CRTC, this assumption isn't applicable to
   2390	 * the nv-display.  Note that T124 support has additional windows,
   2391	 * but currently they aren't supported by the driver.
   2392	 */
   2393	if (dc->soc->has_nvdisplay)
   2394		return 0;
   2395
   2396	new_state = drm_atomic_get_new_crtc_state(state, crtc);
   2397	old_state = drm_atomic_get_old_crtc_state(state, crtc);
   2398
   2399	/*
   2400	 * For overlapping planes pixel's data is fetched for each plane at
   2401	 * the same time, hence bandwidths are accumulated in this case.
   2402	 * This needs to be taken into account for calculating total bandwidth
   2403	 * consumed by all planes.
   2404	 *
   2405	 * Here we get the overlapping state of each plane, which is a
   2406	 * bitmask of plane indices telling with what planes there is an
   2407	 * overlap. Note that bitmask[plane] includes BIT(plane) in order
   2408	 * to make further code nicer and simpler.
   2409	 */
   2410	drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) {
   2411		tegra_state = to_const_tegra_plane_state(plane_state);
   2412		tegra = to_tegra_plane(plane);
   2413
   2414		if (WARN_ON_ONCE(tegra->index >= TEGRA_DC_LEGACY_PLANES_NUM))
   2415			return -EINVAL;
   2416
   2417		plane_peak_bw[tegra->index] = tegra_state->peak_memory_bandwidth;
   2418		mask = tegra_plane_overlap_mask(new_state, plane_state);
   2419		overlap_mask[tegra->index] = mask;
   2420
   2421		if (hweight_long(mask) != 3)
   2422			all_planes_overlap_simultaneously = false;
   2423	}
   2424
   2425	/*
   2426	 * Then we calculate maximum bandwidth of each plane state.
   2427	 * The bandwidth includes the plane BW + BW of the "simultaneously"
   2428	 * overlapping planes, where "simultaneously" means areas where DC
   2429	 * fetches from the planes simultaneously during of scan-out process.
   2430	 *
   2431	 * For example, if plane A overlaps with planes B and C, but B and C
   2432	 * don't overlap, then the peak bandwidth will be either in area where
   2433	 * A-and-B or A-and-C planes overlap.
   2434	 *
   2435	 * The plane_peak_bw[] contains peak memory bandwidth values of
   2436	 * each plane, this information is needed by interconnect provider
   2437	 * in order to set up latency allowance based on the peak BW, see
   2438	 * tegra_crtc_update_memory_bandwidth().
   2439	 */
   2440	drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) {
   2441		u32 i, old_peak_bw, new_peak_bw, overlap_bw = 0;
   2442
   2443		/*
   2444		 * Note that plane's atomic check doesn't touch the
   2445		 * total_peak_memory_bandwidth of enabled plane, hence the
   2446		 * current state contains the old bandwidth state from the
   2447		 * previous CRTC commit.
   2448		 */
   2449		tegra_state = to_const_tegra_plane_state(plane_state);
   2450		tegra = to_tegra_plane(plane);
   2451
   2452		for_each_set_bit(i, &overlap_mask[tegra->index], 3) {
   2453			if (i == tegra->index)
   2454				continue;
   2455
   2456			if (all_planes_overlap_simultaneously)
   2457				overlap_bw += plane_peak_bw[i];
   2458			else
   2459				overlap_bw = max(overlap_bw, plane_peak_bw[i]);
   2460		}
   2461
   2462		new_peak_bw = plane_peak_bw[tegra->index] + overlap_bw;
   2463		old_peak_bw = tegra_state->total_peak_memory_bandwidth;
   2464
   2465		/*
   2466		 * If plane's peak bandwidth changed (for example plane isn't
   2467		 * overlapped anymore) and plane isn't in the atomic state,
   2468		 * then add plane to the state in order to have the bandwidth
   2469		 * updated.
   2470		 */
   2471		if (old_peak_bw != new_peak_bw) {
   2472			struct tegra_plane_state *new_tegra_state;
   2473			struct drm_plane_state *new_plane_state;
   2474
   2475			new_plane_state = drm_atomic_get_plane_state(state, plane);
   2476			if (IS_ERR(new_plane_state))
   2477				return PTR_ERR(new_plane_state);
   2478
   2479			new_tegra_state = to_tegra_plane_state(new_plane_state);
   2480			new_tegra_state->total_peak_memory_bandwidth = new_peak_bw;
   2481		}
   2482	}
   2483
   2484	return 0;
   2485}
   2486
   2487static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
   2488				   struct drm_atomic_state *state)
   2489{
   2490	int err;
   2491
   2492	err = tegra_crtc_calculate_memory_bandwidth(crtc, state);
   2493	if (err)
   2494		return err;
   2495
   2496	return 0;
   2497}
   2498
   2499void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc,
   2500				   struct drm_atomic_state *state)
   2501{
   2502	/*
   2503	 * Display bandwidth is allowed to go down only once hardware state
   2504	 * is known to be armed, i.e. state was committed and VBLANK event
   2505	 * received.
   2506	 */
   2507	tegra_crtc_update_memory_bandwidth(crtc, state, false);
   2508}
   2509
   2510static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
   2511	.atomic_check = tegra_crtc_atomic_check,
   2512	.atomic_begin = tegra_crtc_atomic_begin,
   2513	.atomic_flush = tegra_crtc_atomic_flush,
   2514	.atomic_enable = tegra_crtc_atomic_enable,
   2515	.atomic_disable = tegra_crtc_atomic_disable,
   2516};
   2517
   2518static irqreturn_t tegra_dc_irq(int irq, void *data)
   2519{
   2520	struct tegra_dc *dc = data;
   2521	unsigned long status;
   2522
   2523	status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
   2524	tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
   2525
   2526	if (status & FRAME_END_INT) {
   2527		/*
   2528		dev_dbg(dc->dev, "%s(): frame end\n", __func__);
   2529		*/
   2530		dc->stats.frames_total++;
   2531		dc->stats.frames++;
   2532	}
   2533
   2534	if (status & VBLANK_INT) {
   2535		/*
   2536		dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
   2537		*/
   2538		drm_crtc_handle_vblank(&dc->base);
   2539		dc->stats.vblank_total++;
   2540		dc->stats.vblank++;
   2541	}
   2542
   2543	if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
   2544		/*
   2545		dev_dbg(dc->dev, "%s(): underflow\n", __func__);
   2546		*/
   2547		dc->stats.underflow_total++;
   2548		dc->stats.underflow++;
   2549	}
   2550
   2551	if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
   2552		/*
   2553		dev_dbg(dc->dev, "%s(): overflow\n", __func__);
   2554		*/
   2555		dc->stats.overflow_total++;
   2556		dc->stats.overflow++;
   2557	}
   2558
   2559	if (status & HEAD_UF_INT) {
   2560		dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
   2561		dc->stats.underflow_total++;
   2562		dc->stats.underflow++;
   2563	}
   2564
   2565	return IRQ_HANDLED;
   2566}
   2567
   2568static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
   2569{
   2570	unsigned int i;
   2571
   2572	if (!dc->soc->wgrps)
   2573		return true;
   2574
   2575	for (i = 0; i < dc->soc->num_wgrps; i++) {
   2576		const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
   2577
   2578		if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
   2579			return true;
   2580	}
   2581
   2582	return false;
   2583}
   2584
   2585static int tegra_dc_early_init(struct host1x_client *client)
   2586{
   2587	struct drm_device *drm = dev_get_drvdata(client->host);
   2588	struct tegra_drm *tegra = drm->dev_private;
   2589
   2590	tegra->num_crtcs++;
   2591
   2592	return 0;
   2593}
   2594
   2595static int tegra_dc_init(struct host1x_client *client)
   2596{
   2597	struct drm_device *drm = dev_get_drvdata(client->host);
   2598	unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
   2599	struct tegra_dc *dc = host1x_client_to_dc(client);
   2600	struct tegra_drm *tegra = drm->dev_private;
   2601	struct drm_plane *primary = NULL;
   2602	struct drm_plane *cursor = NULL;
   2603	int err;
   2604
   2605	/*
   2606	 * DC has been reset by now, so VBLANK syncpoint can be released
   2607	 * for general use.
   2608	 */
   2609	host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe);
   2610
   2611	/*
   2612	 * XXX do not register DCs with no window groups because we cannot
   2613	 * assign a primary plane to them, which in turn will cause KMS to
   2614	 * crash.
   2615	 */
   2616	if (!tegra_dc_has_window_groups(dc))
   2617		return 0;
   2618
   2619	/*
   2620	 * Set the display hub as the host1x client parent for the display
   2621	 * controller. This is needed for the runtime reference counting that
   2622	 * ensures the display hub is always powered when any of the display
   2623	 * controllers are.
   2624	 */
   2625	if (dc->soc->has_nvdisplay)
   2626		client->parent = &tegra->hub->client;
   2627
   2628	dc->syncpt = host1x_syncpt_request(client, flags);
   2629	if (!dc->syncpt)
   2630		dev_warn(dc->dev, "failed to allocate syncpoint\n");
   2631
   2632	err = host1x_client_iommu_attach(client);
   2633	if (err < 0 && err != -ENODEV) {
   2634		dev_err(client->dev, "failed to attach to domain: %d\n", err);
   2635		return err;
   2636	}
   2637
   2638	if (dc->soc->wgrps)
   2639		primary = tegra_dc_add_shared_planes(drm, dc);
   2640	else
   2641		primary = tegra_dc_add_planes(drm, dc);
   2642
   2643	if (IS_ERR(primary)) {
   2644		err = PTR_ERR(primary);
   2645		goto cleanup;
   2646	}
   2647
   2648	if (dc->soc->supports_cursor) {
   2649		cursor = tegra_dc_cursor_plane_create(drm, dc);
   2650		if (IS_ERR(cursor)) {
   2651			err = PTR_ERR(cursor);
   2652			goto cleanup;
   2653		}
   2654	} else {
   2655		/* dedicate one overlay to mouse cursor */
   2656		cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
   2657		if (IS_ERR(cursor)) {
   2658			err = PTR_ERR(cursor);
   2659			goto cleanup;
   2660		}
   2661	}
   2662
   2663	err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
   2664					&tegra_crtc_funcs, NULL);
   2665	if (err < 0)
   2666		goto cleanup;
   2667
   2668	drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
   2669
   2670	/*
   2671	 * Keep track of the minimum pitch alignment across all display
   2672	 * controllers.
   2673	 */
   2674	if (dc->soc->pitch_align > tegra->pitch_align)
   2675		tegra->pitch_align = dc->soc->pitch_align;
   2676
   2677	/* track maximum resolution */
   2678	if (dc->soc->has_nvdisplay)
   2679		drm->mode_config.max_width = drm->mode_config.max_height = 16384;
   2680	else
   2681		drm->mode_config.max_width = drm->mode_config.max_height = 4096;
   2682
   2683	err = tegra_dc_rgb_init(drm, dc);
   2684	if (err < 0 && err != -ENODEV) {
   2685		dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
   2686		goto cleanup;
   2687	}
   2688
   2689	err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
   2690			       dev_name(dc->dev), dc);
   2691	if (err < 0) {
   2692		dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
   2693			err);
   2694		goto cleanup;
   2695	}
   2696
   2697	/*
   2698	 * Inherit the DMA parameters (such as maximum segment size) from the
   2699	 * parent host1x device.
   2700	 */
   2701	client->dev->dma_parms = client->host->dma_parms;
   2702
   2703	return 0;
   2704
   2705cleanup:
   2706	if (!IS_ERR_OR_NULL(cursor))
   2707		drm_plane_cleanup(cursor);
   2708
   2709	if (!IS_ERR(primary))
   2710		drm_plane_cleanup(primary);
   2711
   2712	host1x_client_iommu_detach(client);
   2713	host1x_syncpt_put(dc->syncpt);
   2714
   2715	return err;
   2716}
   2717
   2718static int tegra_dc_exit(struct host1x_client *client)
   2719{
   2720	struct tegra_dc *dc = host1x_client_to_dc(client);
   2721	int err;
   2722
   2723	if (!tegra_dc_has_window_groups(dc))
   2724		return 0;
   2725
   2726	/* avoid a dangling pointer just in case this disappears */
   2727	client->dev->dma_parms = NULL;
   2728
   2729	devm_free_irq(dc->dev, dc->irq, dc);
   2730
   2731	err = tegra_dc_rgb_exit(dc);
   2732	if (err) {
   2733		dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
   2734		return err;
   2735	}
   2736
   2737	host1x_client_iommu_detach(client);
   2738	host1x_syncpt_put(dc->syncpt);
   2739
   2740	return 0;
   2741}
   2742
   2743static int tegra_dc_late_exit(struct host1x_client *client)
   2744{
   2745	struct drm_device *drm = dev_get_drvdata(client->host);
   2746	struct tegra_drm *tegra = drm->dev_private;
   2747
   2748	tegra->num_crtcs--;
   2749
   2750	return 0;
   2751}
   2752
   2753static int tegra_dc_runtime_suspend(struct host1x_client *client)
   2754{
   2755	struct tegra_dc *dc = host1x_client_to_dc(client);
   2756	struct device *dev = client->dev;
   2757	int err;
   2758
   2759	err = reset_control_assert(dc->rst);
   2760	if (err < 0) {
   2761		dev_err(dev, "failed to assert reset: %d\n", err);
   2762		return err;
   2763	}
   2764
   2765	if (dc->soc->has_powergate)
   2766		tegra_powergate_power_off(dc->powergate);
   2767
   2768	clk_disable_unprepare(dc->clk);
   2769	pm_runtime_put_sync(dev);
   2770
   2771	return 0;
   2772}
   2773
   2774static int tegra_dc_runtime_resume(struct host1x_client *client)
   2775{
   2776	struct tegra_dc *dc = host1x_client_to_dc(client);
   2777	struct device *dev = client->dev;
   2778	int err;
   2779
   2780	err = pm_runtime_resume_and_get(dev);
   2781	if (err < 0) {
   2782		dev_err(dev, "failed to get runtime PM: %d\n", err);
   2783		return err;
   2784	}
   2785
   2786	if (dc->soc->has_powergate) {
   2787		err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
   2788							dc->rst);
   2789		if (err < 0) {
   2790			dev_err(dev, "failed to power partition: %d\n", err);
   2791			goto put_rpm;
   2792		}
   2793	} else {
   2794		err = clk_prepare_enable(dc->clk);
   2795		if (err < 0) {
   2796			dev_err(dev, "failed to enable clock: %d\n", err);
   2797			goto put_rpm;
   2798		}
   2799
   2800		err = reset_control_deassert(dc->rst);
   2801		if (err < 0) {
   2802			dev_err(dev, "failed to deassert reset: %d\n", err);
   2803			goto disable_clk;
   2804		}
   2805	}
   2806
   2807	return 0;
   2808
   2809disable_clk:
   2810	clk_disable_unprepare(dc->clk);
   2811put_rpm:
   2812	pm_runtime_put_sync(dev);
   2813	return err;
   2814}
   2815
   2816static const struct host1x_client_ops dc_client_ops = {
   2817	.early_init = tegra_dc_early_init,
   2818	.init = tegra_dc_init,
   2819	.exit = tegra_dc_exit,
   2820	.late_exit = tegra_dc_late_exit,
   2821	.suspend = tegra_dc_runtime_suspend,
   2822	.resume = tegra_dc_runtime_resume,
   2823};
   2824
   2825static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
   2826	.supports_background_color = false,
   2827	.supports_interlacing = false,
   2828	.supports_cursor = false,
   2829	.supports_block_linear = false,
   2830	.supports_sector_layout = false,
   2831	.has_legacy_blending = true,
   2832	.pitch_align = 8,
   2833	.has_powergate = false,
   2834	.coupled_pm = true,
   2835	.has_nvdisplay = false,
   2836	.num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
   2837	.primary_formats = tegra20_primary_formats,
   2838	.num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
   2839	.overlay_formats = tegra20_overlay_formats,
   2840	.modifiers = tegra20_modifiers,
   2841	.has_win_a_without_filters = true,
   2842	.has_win_b_vfilter_mem_client = true,
   2843	.has_win_c_without_vert_filter = true,
   2844	.plane_tiled_memory_bandwidth_x2 = false,
   2845	.has_pll_d2_out0 = false,
   2846};
   2847
   2848static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
   2849	.supports_background_color = false,
   2850	.supports_interlacing = false,
   2851	.supports_cursor = false,
   2852	.supports_block_linear = false,
   2853	.supports_sector_layout = false,
   2854	.has_legacy_blending = true,
   2855	.pitch_align = 8,
   2856	.has_powergate = false,
   2857	.coupled_pm = false,
   2858	.has_nvdisplay = false,
   2859	.num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
   2860	.primary_formats = tegra20_primary_formats,
   2861	.num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
   2862	.overlay_formats = tegra20_overlay_formats,
   2863	.modifiers = tegra20_modifiers,
   2864	.has_win_a_without_filters = false,
   2865	.has_win_b_vfilter_mem_client = true,
   2866	.has_win_c_without_vert_filter = false,
   2867	.plane_tiled_memory_bandwidth_x2 = true,
   2868	.has_pll_d2_out0 = true,
   2869};
   2870
   2871static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
   2872	.supports_background_color = false,
   2873	.supports_interlacing = false,
   2874	.supports_cursor = false,
   2875	.supports_block_linear = false,
   2876	.supports_sector_layout = false,
   2877	.has_legacy_blending = true,
   2878	.pitch_align = 64,
   2879	.has_powergate = true,
   2880	.coupled_pm = false,
   2881	.has_nvdisplay = false,
   2882	.num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
   2883	.primary_formats = tegra114_primary_formats,
   2884	.num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
   2885	.overlay_formats = tegra114_overlay_formats,
   2886	.modifiers = tegra20_modifiers,
   2887	.has_win_a_without_filters = false,
   2888	.has_win_b_vfilter_mem_client = false,
   2889	.has_win_c_without_vert_filter = false,
   2890	.plane_tiled_memory_bandwidth_x2 = true,
   2891	.has_pll_d2_out0 = true,
   2892};
   2893
   2894static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
   2895	.supports_background_color = true,
   2896	.supports_interlacing = true,
   2897	.supports_cursor = true,
   2898	.supports_block_linear = true,
   2899	.supports_sector_layout = false,
   2900	.has_legacy_blending = false,
   2901	.pitch_align = 64,
   2902	.has_powergate = true,
   2903	.coupled_pm = false,
   2904	.has_nvdisplay = false,
   2905	.num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
   2906	.primary_formats = tegra124_primary_formats,
   2907	.num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
   2908	.overlay_formats = tegra124_overlay_formats,
   2909	.modifiers = tegra124_modifiers,
   2910	.has_win_a_without_filters = false,
   2911	.has_win_b_vfilter_mem_client = false,
   2912	.has_win_c_without_vert_filter = false,
   2913	.plane_tiled_memory_bandwidth_x2 = false,
   2914	.has_pll_d2_out0 = true,
   2915};
   2916
   2917static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
   2918	.supports_background_color = true,
   2919	.supports_interlacing = true,
   2920	.supports_cursor = true,
   2921	.supports_block_linear = true,
   2922	.supports_sector_layout = false,
   2923	.has_legacy_blending = false,
   2924	.pitch_align = 64,
   2925	.has_powergate = true,
   2926	.coupled_pm = false,
   2927	.has_nvdisplay = false,
   2928	.num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
   2929	.primary_formats = tegra114_primary_formats,
   2930	.num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
   2931	.overlay_formats = tegra114_overlay_formats,
   2932	.modifiers = tegra124_modifiers,
   2933	.has_win_a_without_filters = false,
   2934	.has_win_b_vfilter_mem_client = false,
   2935	.has_win_c_without_vert_filter = false,
   2936	.plane_tiled_memory_bandwidth_x2 = false,
   2937	.has_pll_d2_out0 = true,
   2938};
   2939
   2940static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
   2941	{
   2942		.index = 0,
   2943		.dc = 0,
   2944		.windows = (const unsigned int[]) { 0 },
   2945		.num_windows = 1,
   2946	}, {
   2947		.index = 1,
   2948		.dc = 1,
   2949		.windows = (const unsigned int[]) { 1 },
   2950		.num_windows = 1,
   2951	}, {
   2952		.index = 2,
   2953		.dc = 1,
   2954		.windows = (const unsigned int[]) { 2 },
   2955		.num_windows = 1,
   2956	}, {
   2957		.index = 3,
   2958		.dc = 2,
   2959		.windows = (const unsigned int[]) { 3 },
   2960		.num_windows = 1,
   2961	}, {
   2962		.index = 4,
   2963		.dc = 2,
   2964		.windows = (const unsigned int[]) { 4 },
   2965		.num_windows = 1,
   2966	}, {
   2967		.index = 5,
   2968		.dc = 2,
   2969		.windows = (const unsigned int[]) { 5 },
   2970		.num_windows = 1,
   2971	},
   2972};
   2973
   2974static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
   2975	.supports_background_color = true,
   2976	.supports_interlacing = true,
   2977	.supports_cursor = true,
   2978	.supports_block_linear = true,
   2979	.supports_sector_layout = false,
   2980	.has_legacy_blending = false,
   2981	.pitch_align = 64,
   2982	.has_powergate = false,
   2983	.coupled_pm = false,
   2984	.has_nvdisplay = true,
   2985	.wgrps = tegra186_dc_wgrps,
   2986	.num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
   2987	.plane_tiled_memory_bandwidth_x2 = false,
   2988	.has_pll_d2_out0 = false,
   2989};
   2990
   2991static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
   2992	{
   2993		.index = 0,
   2994		.dc = 0,
   2995		.windows = (const unsigned int[]) { 0 },
   2996		.num_windows = 1,
   2997	}, {
   2998		.index = 1,
   2999		.dc = 1,
   3000		.windows = (const unsigned int[]) { 1 },
   3001		.num_windows = 1,
   3002	}, {
   3003		.index = 2,
   3004		.dc = 1,
   3005		.windows = (const unsigned int[]) { 2 },
   3006		.num_windows = 1,
   3007	}, {
   3008		.index = 3,
   3009		.dc = 2,
   3010		.windows = (const unsigned int[]) { 3 },
   3011		.num_windows = 1,
   3012	}, {
   3013		.index = 4,
   3014		.dc = 2,
   3015		.windows = (const unsigned int[]) { 4 },
   3016		.num_windows = 1,
   3017	}, {
   3018		.index = 5,
   3019		.dc = 2,
   3020		.windows = (const unsigned int[]) { 5 },
   3021		.num_windows = 1,
   3022	},
   3023};
   3024
   3025static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
   3026	.supports_background_color = true,
   3027	.supports_interlacing = true,
   3028	.supports_cursor = true,
   3029	.supports_block_linear = true,
   3030	.supports_sector_layout = true,
   3031	.has_legacy_blending = false,
   3032	.pitch_align = 64,
   3033	.has_powergate = false,
   3034	.coupled_pm = false,
   3035	.has_nvdisplay = true,
   3036	.wgrps = tegra194_dc_wgrps,
   3037	.num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
   3038	.plane_tiled_memory_bandwidth_x2 = false,
   3039	.has_pll_d2_out0 = false,
   3040};
   3041
   3042static const struct of_device_id tegra_dc_of_match[] = {
   3043	{
   3044		.compatible = "nvidia,tegra194-dc",
   3045		.data = &tegra194_dc_soc_info,
   3046	}, {
   3047		.compatible = "nvidia,tegra186-dc",
   3048		.data = &tegra186_dc_soc_info,
   3049	}, {
   3050		.compatible = "nvidia,tegra210-dc",
   3051		.data = &tegra210_dc_soc_info,
   3052	}, {
   3053		.compatible = "nvidia,tegra124-dc",
   3054		.data = &tegra124_dc_soc_info,
   3055	}, {
   3056		.compatible = "nvidia,tegra114-dc",
   3057		.data = &tegra114_dc_soc_info,
   3058	}, {
   3059		.compatible = "nvidia,tegra30-dc",
   3060		.data = &tegra30_dc_soc_info,
   3061	}, {
   3062		.compatible = "nvidia,tegra20-dc",
   3063		.data = &tegra20_dc_soc_info,
   3064	}, {
   3065		/* sentinel */
   3066	}
   3067};
   3068MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
   3069
   3070static int tegra_dc_parse_dt(struct tegra_dc *dc)
   3071{
   3072	struct device_node *np;
   3073	u32 value = 0;
   3074	int err;
   3075
   3076	err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
   3077	if (err < 0) {
   3078		dev_err(dc->dev, "missing \"nvidia,head\" property\n");
   3079
   3080		/*
   3081		 * If the nvidia,head property isn't present, try to find the
   3082		 * correct head number by looking up the position of this
   3083		 * display controller's node within the device tree. Assuming
   3084		 * that the nodes are ordered properly in the DTS file and
   3085		 * that the translation into a flattened device tree blob
   3086		 * preserves that ordering this will actually yield the right
   3087		 * head number.
   3088		 *
   3089		 * If those assumptions don't hold, this will still work for
   3090		 * cases where only a single display controller is used.
   3091		 */
   3092		for_each_matching_node(np, tegra_dc_of_match) {
   3093			if (np == dc->dev->of_node) {
   3094				of_node_put(np);
   3095				break;
   3096			}
   3097
   3098			value++;
   3099		}
   3100	}
   3101
   3102	dc->pipe = value;
   3103
   3104	return 0;
   3105}
   3106
   3107static int tegra_dc_match_by_pipe(struct device *dev, const void *data)
   3108{
   3109	struct tegra_dc *dc = dev_get_drvdata(dev);
   3110	unsigned int pipe = (unsigned long)(void *)data;
   3111
   3112	return dc->pipe == pipe;
   3113}
   3114
   3115static int tegra_dc_couple(struct tegra_dc *dc)
   3116{
   3117	/*
   3118	 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
   3119	 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
   3120	 * POWER_CONTROL registers during CRTC enabling.
   3121	 */
   3122	if (dc->soc->coupled_pm && dc->pipe == 1) {
   3123		struct device *companion;
   3124		struct tegra_dc *parent;
   3125
   3126		companion = driver_find_device(dc->dev->driver, NULL, (const void *)0,
   3127					       tegra_dc_match_by_pipe);
   3128		if (!companion)
   3129			return -EPROBE_DEFER;
   3130
   3131		parent = dev_get_drvdata(companion);
   3132		dc->client.parent = &parent->client;
   3133
   3134		dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion));
   3135	}
   3136
   3137	return 0;
   3138}
   3139
   3140static int tegra_dc_init_opp_table(struct tegra_dc *dc)
   3141{
   3142	struct tegra_core_opp_params opp_params = {};
   3143	int err;
   3144
   3145	err = devm_tegra_core_dev_init_opp_table(dc->dev, &opp_params);
   3146	if (err && err != -ENODEV)
   3147		return err;
   3148
   3149	if (err)
   3150		dc->has_opp_table = false;
   3151	else
   3152		dc->has_opp_table = true;
   3153
   3154	return 0;
   3155}
   3156
   3157static int tegra_dc_probe(struct platform_device *pdev)
   3158{
   3159	u64 dma_mask = dma_get_mask(pdev->dev.parent);
   3160	struct tegra_dc *dc;
   3161	int err;
   3162
   3163	err = dma_coerce_mask_and_coherent(&pdev->dev, dma_mask);
   3164	if (err < 0) {
   3165		dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
   3166		return err;
   3167	}
   3168
   3169	dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
   3170	if (!dc)
   3171		return -ENOMEM;
   3172
   3173	dc->soc = of_device_get_match_data(&pdev->dev);
   3174
   3175	INIT_LIST_HEAD(&dc->list);
   3176	dc->dev = &pdev->dev;
   3177
   3178	err = tegra_dc_parse_dt(dc);
   3179	if (err < 0)
   3180		return err;
   3181
   3182	err = tegra_dc_couple(dc);
   3183	if (err < 0)
   3184		return err;
   3185
   3186	dc->clk = devm_clk_get(&pdev->dev, NULL);
   3187	if (IS_ERR(dc->clk)) {
   3188		dev_err(&pdev->dev, "failed to get clock\n");
   3189		return PTR_ERR(dc->clk);
   3190	}
   3191
   3192	dc->rst = devm_reset_control_get(&pdev->dev, "dc");
   3193	if (IS_ERR(dc->rst)) {
   3194		dev_err(&pdev->dev, "failed to get reset\n");
   3195		return PTR_ERR(dc->rst);
   3196	}
   3197
   3198	/* assert reset and disable clock */
   3199	err = clk_prepare_enable(dc->clk);
   3200	if (err < 0)
   3201		return err;
   3202
   3203	usleep_range(2000, 4000);
   3204
   3205	err = reset_control_assert(dc->rst);
   3206	if (err < 0)
   3207		return err;
   3208
   3209	usleep_range(2000, 4000);
   3210
   3211	clk_disable_unprepare(dc->clk);
   3212
   3213	if (dc->soc->has_powergate) {
   3214		if (dc->pipe == 0)
   3215			dc->powergate = TEGRA_POWERGATE_DIS;
   3216		else
   3217			dc->powergate = TEGRA_POWERGATE_DISB;
   3218
   3219		tegra_powergate_power_off(dc->powergate);
   3220	}
   3221
   3222	err = tegra_dc_init_opp_table(dc);
   3223	if (err < 0)
   3224		return err;
   3225
   3226	dc->regs = devm_platform_ioremap_resource(pdev, 0);
   3227	if (IS_ERR(dc->regs))
   3228		return PTR_ERR(dc->regs);
   3229
   3230	dc->irq = platform_get_irq(pdev, 0);
   3231	if (dc->irq < 0)
   3232		return -ENXIO;
   3233
   3234	err = tegra_dc_rgb_probe(dc);
   3235	if (err < 0 && err != -ENODEV)
   3236		return dev_err_probe(&pdev->dev, err,
   3237				     "failed to probe RGB output\n");
   3238
   3239	platform_set_drvdata(pdev, dc);
   3240	pm_runtime_enable(&pdev->dev);
   3241
   3242	INIT_LIST_HEAD(&dc->client.list);
   3243	dc->client.ops = &dc_client_ops;
   3244	dc->client.dev = &pdev->dev;
   3245
   3246	err = host1x_client_register(&dc->client);
   3247	if (err < 0) {
   3248		dev_err(&pdev->dev, "failed to register host1x client: %d\n",
   3249			err);
   3250		goto disable_pm;
   3251	}
   3252
   3253	return 0;
   3254
   3255disable_pm:
   3256	pm_runtime_disable(&pdev->dev);
   3257	tegra_dc_rgb_remove(dc);
   3258
   3259	return err;
   3260}
   3261
   3262static int tegra_dc_remove(struct platform_device *pdev)
   3263{
   3264	struct tegra_dc *dc = platform_get_drvdata(pdev);
   3265	int err;
   3266
   3267	err = host1x_client_unregister(&dc->client);
   3268	if (err < 0) {
   3269		dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
   3270			err);
   3271		return err;
   3272	}
   3273
   3274	err = tegra_dc_rgb_remove(dc);
   3275	if (err < 0) {
   3276		dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
   3277		return err;
   3278	}
   3279
   3280	pm_runtime_disable(&pdev->dev);
   3281
   3282	return 0;
   3283}
   3284
   3285struct platform_driver tegra_dc_driver = {
   3286	.driver = {
   3287		.name = "tegra-dc",
   3288		.of_match_table = tegra_dc_of_match,
   3289	},
   3290	.probe = tegra_dc_probe,
   3291	.remove = tegra_dc_remove,
   3292};