cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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tidss_dispc.h (4300B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
      4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
      5 */
      6
      7#ifndef __TIDSS_DISPC_H__
      8#define __TIDSS_DISPC_H__
      9
     10#include "tidss_drv.h"
     11
     12struct dispc_device;
     13
     14struct drm_crtc_state;
     15
     16enum tidss_gamma_type { TIDSS_GAMMA_8BIT, TIDSS_GAMMA_10BIT };
     17
     18struct tidss_vp_feat {
     19	struct tidss_vp_color_feat {
     20		u32 gamma_size;
     21		enum tidss_gamma_type gamma_type;
     22		bool has_ctm;
     23	} color;
     24};
     25
     26struct tidss_plane_feat {
     27	struct tidss_plane_color_feat {
     28		u32 encodings;
     29		u32 ranges;
     30		enum drm_color_encoding default_encoding;
     31		enum drm_color_range default_range;
     32	} color;
     33	struct tidss_plane_blend_feat {
     34		bool global_alpha;
     35	} blend;
     36};
     37
     38struct dispc_features_scaling {
     39	u32 in_width_max_5tap_rgb;
     40	u32 in_width_max_3tap_rgb;
     41	u32 in_width_max_5tap_yuv;
     42	u32 in_width_max_3tap_yuv;
     43	u32 upscale_limit;
     44	u32 downscale_limit_5tap;
     45	u32 downscale_limit_3tap;
     46	u32 xinc_max;
     47};
     48
     49struct dispc_errata {
     50	bool i2000; /* DSS Does Not Support YUV Pixel Data Formats */
     51};
     52
     53enum dispc_vp_bus_type {
     54	DISPC_VP_DPI,		/* DPI output */
     55	DISPC_VP_OLDI,		/* OLDI (LVDS) output */
     56	DISPC_VP_INTERNAL,	/* SoC internal routing */
     57	DISPC_VP_MAX_BUS_TYPE,
     58};
     59
     60enum dispc_dss_subrevision {
     61	DISPC_K2G,
     62	DISPC_AM65X,
     63	DISPC_J721E,
     64};
     65
     66struct dispc_features {
     67	int min_pclk_khz;
     68	int max_pclk_khz[DISPC_VP_MAX_BUS_TYPE];
     69
     70	struct dispc_features_scaling scaling;
     71
     72	enum dispc_dss_subrevision subrev;
     73
     74	const char *common;
     75	const u16 *common_regs;
     76	u32 num_vps;
     77	const char *vp_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */
     78	const char *ovr_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */
     79	const char *vpclk_name[TIDSS_MAX_PORTS]; /* Should match dt clk names */
     80	const enum dispc_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS];
     81	struct tidss_vp_feat vp_feat;
     82	u32 num_planes;
     83	const char *vid_name[TIDSS_MAX_PLANES]; /* Should match dt reg names */
     84	bool vid_lite[TIDSS_MAX_PLANES];
     85	u32 vid_order[TIDSS_MAX_PLANES];
     86};
     87
     88extern const struct dispc_features dispc_k2g_feats;
     89extern const struct dispc_features dispc_am65x_feats;
     90extern const struct dispc_features dispc_j721e_feats;
     91
     92void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask);
     93dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc);
     94
     95void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
     96			 u32 hw_videoport, u32 x, u32 y, u32 layer);
     97void dispc_ovr_enable_layer(struct dispc_device *dispc,
     98			    u32 hw_videoport, u32 layer, bool enable);
     99
    100void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
    101		      const struct drm_crtc_state *state);
    102void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
    103		     const struct drm_crtc_state *state);
    104void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport);
    105void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport);
    106bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport);
    107void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport);
    108int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport,
    109		       const struct drm_crtc_state *state);
    110enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
    111					 u32 hw_videoport,
    112					 const struct drm_display_mode *mode);
    113int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport);
    114void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport);
    115int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
    116			  unsigned long rate);
    117void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport,
    118		    const struct drm_crtc_state *state, bool newmodeset);
    119
    120int dispc_runtime_suspend(struct dispc_device *dispc);
    121int dispc_runtime_resume(struct dispc_device *dispc);
    122
    123int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane,
    124		      const struct drm_plane_state *state,
    125		      u32 hw_videoport);
    126int dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
    127		      const struct drm_plane_state *state,
    128		      u32 hw_videoport);
    129int dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable);
    130const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len);
    131
    132int dispc_init(struct tidss_device *tidss);
    133void dispc_remove(struct tidss_device *tidss);
    134
    135#endif