cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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coresight-catu.h (3033B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Copyright (C) 2018 Arm Limited. All rights reserved.
      4 *
      5 * Author: Suzuki K Poulose <suzuki.poulose@arm.com>
      6 */
      7
      8#ifndef _CORESIGHT_CATU_H
      9#define _CORESIGHT_CATU_H
     10
     11#include "coresight-priv.h"
     12
     13/* Register offset from base */
     14#define CATU_CONTROL		0x000
     15#define CATU_MODE		0x004
     16#define CATU_AXICTRL		0x008
     17#define CATU_IRQEN		0x00c
     18#define CATU_SLADDRLO		0x020
     19#define CATU_SLADDRHI		0x024
     20#define CATU_INADDRLO		0x028
     21#define CATU_INADDRHI		0x02c
     22#define CATU_STATUS		0x100
     23#define CATU_DEVARCH		0xfbc
     24
     25#define CATU_CONTROL_ENABLE	0
     26
     27#define CATU_MODE_PASS_THROUGH	0U
     28#define CATU_MODE_TRANSLATE	1U
     29
     30#define CATU_AXICTRL_ARCACHE_SHIFT	4
     31#define CATU_AXICTRL_ARCACHE_MASK	0xf
     32#define CATU_AXICTRL_ARPROT_MASK	0x3
     33#define CATU_AXICTRL_ARCACHE(arcache)		\
     34	(((arcache) & CATU_AXICTRL_ARCACHE_MASK) << CATU_AXICTRL_ARCACHE_SHIFT)
     35
     36#define CATU_AXICTRL_VAL(arcache, arprot)	\
     37	(CATU_AXICTRL_ARCACHE(arcache) | ((arprot) & CATU_AXICTRL_ARPROT_MASK))
     38
     39#define AXI3_AxCACHE_WB_READ_ALLOC	0x7
     40/*
     41 * AXI - ARPROT bits:
     42 * See AMBA AXI & ACE Protocol specification (ARM IHI 0022E)
     43 * sectionA4.7 Access Permissions.
     44 *
     45 * Bit 0: 0 - Unprivileged access, 1 - Privileged access
     46 * Bit 1: 0 - Secure access, 1 - Non-secure access.
     47 * Bit 2: 0 - Data access, 1 - instruction access.
     48 *
     49 * CATU AXICTRL:ARPROT[2] is res0 as we always access data.
     50 */
     51#define CATU_OS_ARPROT			0x2
     52
     53#define CATU_OS_AXICTRL		\
     54	CATU_AXICTRL_VAL(AXI3_AxCACHE_WB_READ_ALLOC, CATU_OS_ARPROT)
     55
     56#define CATU_STATUS_READY	8
     57#define CATU_STATUS_ADRERR	0
     58#define CATU_STATUS_AXIERR	4
     59
     60#define CATU_IRQEN_ON		0x1
     61#define CATU_IRQEN_OFF		0x0
     62
     63struct catu_drvdata {
     64	void __iomem *base;
     65	struct coresight_device *csdev;
     66	int irq;
     67};
     68
     69#define CATU_REG32(name, offset)					\
     70static inline u32							\
     71catu_read_##name(struct catu_drvdata *drvdata)				\
     72{									\
     73	return coresight_read_reg_pair(drvdata->base, offset, -1);	\
     74}									\
     75static inline void							\
     76catu_write_##name(struct catu_drvdata *drvdata, u32 val)		\
     77{									\
     78	coresight_write_reg_pair(drvdata->base, val, offset, -1);	\
     79}
     80
     81#define CATU_REG_PAIR(name, lo_off, hi_off)				\
     82static inline u64							\
     83catu_read_##name(struct catu_drvdata *drvdata)				\
     84{									\
     85	return coresight_read_reg_pair(drvdata->base, lo_off, hi_off);	\
     86}									\
     87static inline void							\
     88catu_write_##name(struct catu_drvdata *drvdata, u64 val)		\
     89{									\
     90	coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off);	\
     91}
     92
     93CATU_REG32(control, CATU_CONTROL);
     94CATU_REG32(mode, CATU_MODE);
     95CATU_REG32(irqen, CATU_IRQEN);
     96CATU_REG32(axictrl, CATU_AXICTRL);
     97CATU_REG_PAIR(sladdr, CATU_SLADDRLO, CATU_SLADDRHI)
     98CATU_REG_PAIR(inaddr, CATU_INADDRLO, CATU_INADDRHI)
     99
    100static inline bool coresight_is_catu_device(struct coresight_device *csdev)
    101{
    102	if (!IS_ENABLED(CONFIG_CORESIGHT_CATU))
    103		return false;
    104	if (csdev->type != CORESIGHT_DEV_TYPE_HELPER)
    105		return false;
    106	if (csdev->subtype.helper_subtype != CORESIGHT_DEV_SUBTYPE_HELPER_CATU)
    107		return false;
    108	return true;
    109}
    110
    111#endif