cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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coresight-etm-perf.h (2902B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Copyright(C) 2015 Linaro Limited. All rights reserved.
      4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
      5 */
      6
      7#ifndef _CORESIGHT_ETM_PERF_H
      8#define _CORESIGHT_ETM_PERF_H
      9
     10#include <linux/percpu-defs.h>
     11#include "coresight-priv.h"
     12
     13struct coresight_device;
     14struct cscfg_config_desc;
     15
     16/*
     17 * In both ETMv3 and v4 the maximum number of address comparator implentable
     18 * is 8.  The actual number is implementation specific and will be checked
     19 * when filters are applied.
     20 */
     21#define ETM_ADDR_CMP_MAX	8
     22
     23/**
     24 * struct etm_filter - single instruction range or start/stop configuration.
     25 * @start_addr:	The address to start tracing on.
     26 * @stop_addr:	The address to stop tracing on.
     27 * @type:	Is this a range or start/stop filter.
     28 */
     29struct etm_filter {
     30	unsigned long start_addr;
     31	unsigned long stop_addr;
     32	enum etm_addr_type type;
     33};
     34
     35/**
     36 * struct etm_filters - set of filters for a session
     37 * @etm_filter:	All the filters for this session.
     38 * @nr_filters:	Number of filters
     39 * @ssstatus:	Status of the start/stop logic.
     40 */
     41struct etm_filters {
     42	struct etm_filter	etm_filter[ETM_ADDR_CMP_MAX];
     43	unsigned int		nr_filters;
     44	bool			ssstatus;
     45};
     46
     47/**
     48 * struct etm_event_data - Coresight specifics associated to an event
     49 * @work:		Handle to free allocated memory outside IRQ context.
     50 * @mask:		Hold the CPU(s) this event was set for.
     51 * @snk_config:		The sink configuration.
     52 * @cfg_hash:		The hash id of any coresight config selected.
     53 * @path:		An array of path, each slot for one CPU.
     54 */
     55struct etm_event_data {
     56	struct work_struct work;
     57	cpumask_t mask;
     58	void *snk_config;
     59	u32 cfg_hash;
     60	struct list_head * __percpu *path;
     61};
     62
     63#if IS_ENABLED(CONFIG_CORESIGHT)
     64int etm_perf_symlink(struct coresight_device *csdev, bool link);
     65int etm_perf_add_symlink_sink(struct coresight_device *csdev);
     66void etm_perf_del_symlink_sink(struct coresight_device *csdev);
     67static inline void *etm_perf_sink_config(struct perf_output_handle *handle)
     68{
     69	struct etm_event_data *data = perf_get_aux(handle);
     70
     71	if (data)
     72		return data->snk_config;
     73	return NULL;
     74}
     75int etm_perf_add_symlink_cscfg(struct device *dev,
     76			       struct cscfg_config_desc *config_desc);
     77void etm_perf_del_symlink_cscfg(struct cscfg_config_desc *config_desc);
     78#else
     79static inline int etm_perf_symlink(struct coresight_device *csdev, bool link)
     80{ return -EINVAL; }
     81int etm_perf_add_symlink_sink(struct coresight_device *csdev)
     82{ return -EINVAL; }
     83void etm_perf_del_symlink_sink(struct coresight_device *csdev) {}
     84static inline void *etm_perf_sink_config(struct perf_output_handle *handle)
     85{
     86	return NULL;
     87}
     88int etm_perf_add_symlink_cscfg(struct device *dev,
     89			       struct cscfg_config_desc *config_desc)
     90{ return -EINVAL; }
     91void etm_perf_del_symlink_cscfg(struct cscfg_config_desc *config_desc) {}
     92
     93#endif /* CONFIG_CORESIGHT */
     94
     95int __init etm_perf_init(void);
     96void etm_perf_exit(void);
     97
     98#endif