cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

Kconfig (2837B)


      1# SPDX-License-Identifier: GPL-2.0-only
      2config INTEL_TH
      3	tristate "Intel(R) Trace Hub controller"
      4	depends on HAS_DMA && HAS_IOMEM
      5	help
      6	  Intel(R) Trace Hub (TH) is a set of hardware blocks (subdevices) that
      7	  produce, switch and output trace data from multiple hardware and
      8	  software sources over several types of trace output ports encoded
      9	  in System Trace Protocol (MIPI STPv2) and is intended to perform
     10	  full system debugging.
     11
     12	  This option enables intel_th bus and common code used by TH
     13	  subdevices to interact with each other and hardware and for
     14	  platform glue layers to drive Intel TH devices.
     15
     16	  Say Y here to enable Intel(R) Trace Hub controller support.
     17
     18if INTEL_TH
     19
     20config INTEL_TH_PCI
     21	tristate "Intel(R) Trace Hub PCI controller"
     22	depends on PCI
     23	help
     24	  Intel(R) Trace Hub may exist as a PCI device. This option enables
     25	  support glue layer for PCI-based Intel TH.
     26
     27	  Say Y here to enable PCI Intel TH support.
     28
     29config INTEL_TH_ACPI
     30	tristate "Intel(R) Trace Hub ACPI controller"
     31	depends on ACPI
     32	help
     33	  Intel(R) Trace Hub may exist as an ACPI device. This option enables
     34	  support glue layer for ACPI-based Intel TH. This typically implies
     35	  'host debugger' mode, that is, the trace configuration and capture
     36	  is handled by an external debug host and corresponding controls will
     37	  not be available on the target.
     38
     39	  Say Y here to enable ACPI Intel TH support.
     40
     41config INTEL_TH_GTH
     42	tristate "Intel(R) Trace Hub Global Trace Hub"
     43	help
     44	  Global Trace Hub (GTH) is the central component of the
     45	  Intel TH infrastructure and acts as a switch for source
     46	  and output devices. This driver is required for other
     47	  Intel TH subdevices to initialize.
     48
     49	  Say Y here to enable GTH subdevice of Intel(R) Trace Hub.
     50
     51config INTEL_TH_STH
     52	tristate "Intel(R) Trace Hub Software Trace Hub support"
     53	depends on STM
     54	help
     55	  Software Trace Hub (STH) enables trace data from software
     56	  trace sources to be sent out via Intel(R) Trace Hub. It
     57	  uses stm class device to interface with its sources.
     58
     59	  Say Y here to enable STH subdevice of Intel(R) Trace Hub.
     60
     61config INTEL_TH_MSU
     62	tristate "Intel(R) Trace Hub Memory Storage Unit"
     63	help
     64	  Memory Storage Unit (MSU) trace output device enables
     65	  storing STP traces to system memory. It supports single
     66	  and multiblock modes of operation and provides read()
     67	  and mmap() access to the collected data.
     68
     69	  Say Y here to enable MSU output device for Intel TH.
     70
     71config INTEL_TH_PTI
     72	tristate "Intel(R) Trace Hub PTI output"
     73	help
     74	  Parallel Trace Interface unit (PTI) is a trace output device
     75	  of Intel TH architecture that facilitates STP trace output via
     76	  a PTI port.
     77
     78	  Say Y to enable PTI output of Intel TH data.
     79
     80config INTEL_TH_DEBUG
     81	bool "Intel(R) Trace Hub debugging"
     82	depends on DEBUG_FS
     83	help
     84	  Say Y here to enable debugging.
     85
     86endif