cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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i2c-aspeed.c (32788B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 *  Aspeed 24XX/25XX I2C Controller.
      4 *
      5 *  Copyright (C) 2012-2017 ASPEED Technology Inc.
      6 *  Copyright 2017 IBM Corporation
      7 *  Copyright 2017 Google, Inc.
      8 */
      9
     10#include <linux/clk.h>
     11#include <linux/completion.h>
     12#include <linux/err.h>
     13#include <linux/errno.h>
     14#include <linux/i2c.h>
     15#include <linux/init.h>
     16#include <linux/interrupt.h>
     17#include <linux/io.h>
     18#include <linux/irq.h>
     19#include <linux/kernel.h>
     20#include <linux/module.h>
     21#include <linux/of_address.h>
     22#include <linux/of_irq.h>
     23#include <linux/of_platform.h>
     24#include <linux/platform_device.h>
     25#include <linux/reset.h>
     26#include <linux/slab.h>
     27
     28/* I2C Register */
     29#define ASPEED_I2C_FUN_CTRL_REG				0x00
     30#define ASPEED_I2C_AC_TIMING_REG1			0x04
     31#define ASPEED_I2C_AC_TIMING_REG2			0x08
     32#define ASPEED_I2C_INTR_CTRL_REG			0x0c
     33#define ASPEED_I2C_INTR_STS_REG				0x10
     34#define ASPEED_I2C_CMD_REG				0x14
     35#define ASPEED_I2C_DEV_ADDR_REG				0x18
     36#define ASPEED_I2C_BYTE_BUF_REG				0x20
     37
     38/* Global Register Definition */
     39/* 0x00 : I2C Interrupt Status Register  */
     40/* 0x08 : I2C Interrupt Target Assignment  */
     41
     42/* Device Register Definition */
     43/* 0x00 : I2CD Function Control Register  */
     44#define ASPEED_I2CD_MULTI_MASTER_DIS			BIT(15)
     45#define ASPEED_I2CD_SDA_DRIVE_1T_EN			BIT(8)
     46#define ASPEED_I2CD_M_SDA_DRIVE_1T_EN			BIT(7)
     47#define ASPEED_I2CD_M_HIGH_SPEED_EN			BIT(6)
     48#define ASPEED_I2CD_SLAVE_EN				BIT(1)
     49#define ASPEED_I2CD_MASTER_EN				BIT(0)
     50
     51/* 0x04 : I2CD Clock and AC Timing Control Register #1 */
     52#define ASPEED_I2CD_TIME_TBUF_MASK			GENMASK(31, 28)
     53#define ASPEED_I2CD_TIME_THDSTA_MASK			GENMASK(27, 24)
     54#define ASPEED_I2CD_TIME_TACST_MASK			GENMASK(23, 20)
     55#define ASPEED_I2CD_TIME_SCL_HIGH_SHIFT			16
     56#define ASPEED_I2CD_TIME_SCL_HIGH_MASK			GENMASK(19, 16)
     57#define ASPEED_I2CD_TIME_SCL_LOW_SHIFT			12
     58#define ASPEED_I2CD_TIME_SCL_LOW_MASK			GENMASK(15, 12)
     59#define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK		GENMASK(3, 0)
     60#define ASPEED_I2CD_TIME_SCL_REG_MAX			GENMASK(3, 0)
     61/* 0x08 : I2CD Clock and AC Timing Control Register #2 */
     62#define ASPEED_NO_TIMEOUT_CTRL				0
     63
     64/* 0x0c : I2CD Interrupt Control Register &
     65 * 0x10 : I2CD Interrupt Status Register
     66 *
     67 * These share bit definitions, so use the same values for the enable &
     68 * status bits.
     69 */
     70#define ASPEED_I2CD_INTR_RECV_MASK			0xf000ffff
     71#define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT			BIT(14)
     72#define ASPEED_I2CD_INTR_BUS_RECOVER_DONE		BIT(13)
     73#define ASPEED_I2CD_INTR_SLAVE_MATCH			BIT(7)
     74#define ASPEED_I2CD_INTR_SCL_TIMEOUT			BIT(6)
     75#define ASPEED_I2CD_INTR_ABNORMAL			BIT(5)
     76#define ASPEED_I2CD_INTR_NORMAL_STOP			BIT(4)
     77#define ASPEED_I2CD_INTR_ARBIT_LOSS			BIT(3)
     78#define ASPEED_I2CD_INTR_RX_DONE			BIT(2)
     79#define ASPEED_I2CD_INTR_TX_NAK				BIT(1)
     80#define ASPEED_I2CD_INTR_TX_ACK				BIT(0)
     81#define ASPEED_I2CD_INTR_MASTER_ERRORS					       \
     82		(ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |			       \
     83		 ASPEED_I2CD_INTR_SCL_TIMEOUT |				       \
     84		 ASPEED_I2CD_INTR_ABNORMAL |				       \
     85		 ASPEED_I2CD_INTR_ARBIT_LOSS)
     86#define ASPEED_I2CD_INTR_ALL						       \
     87		(ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |			       \
     88		 ASPEED_I2CD_INTR_BUS_RECOVER_DONE |			       \
     89		 ASPEED_I2CD_INTR_SCL_TIMEOUT |				       \
     90		 ASPEED_I2CD_INTR_ABNORMAL |				       \
     91		 ASPEED_I2CD_INTR_NORMAL_STOP |				       \
     92		 ASPEED_I2CD_INTR_ARBIT_LOSS |				       \
     93		 ASPEED_I2CD_INTR_RX_DONE |				       \
     94		 ASPEED_I2CD_INTR_TX_NAK |				       \
     95		 ASPEED_I2CD_INTR_TX_ACK)
     96
     97/* 0x14 : I2CD Command/Status Register   */
     98#define ASPEED_I2CD_SCL_LINE_STS			BIT(18)
     99#define ASPEED_I2CD_SDA_LINE_STS			BIT(17)
    100#define ASPEED_I2CD_BUS_BUSY_STS			BIT(16)
    101#define ASPEED_I2CD_BUS_RECOVER_CMD			BIT(11)
    102
    103/* Command Bit */
    104#define ASPEED_I2CD_M_STOP_CMD				BIT(5)
    105#define ASPEED_I2CD_M_S_RX_CMD_LAST			BIT(4)
    106#define ASPEED_I2CD_M_RX_CMD				BIT(3)
    107#define ASPEED_I2CD_S_TX_CMD				BIT(2)
    108#define ASPEED_I2CD_M_TX_CMD				BIT(1)
    109#define ASPEED_I2CD_M_START_CMD				BIT(0)
    110#define ASPEED_I2CD_MASTER_CMDS_MASK					       \
    111		(ASPEED_I2CD_M_STOP_CMD |				       \
    112		 ASPEED_I2CD_M_S_RX_CMD_LAST |				       \
    113		 ASPEED_I2CD_M_RX_CMD |					       \
    114		 ASPEED_I2CD_M_TX_CMD |					       \
    115		 ASPEED_I2CD_M_START_CMD)
    116
    117/* 0x18 : I2CD Slave Device Address Register   */
    118#define ASPEED_I2CD_DEV_ADDR_MASK			GENMASK(6, 0)
    119
    120enum aspeed_i2c_master_state {
    121	ASPEED_I2C_MASTER_INACTIVE,
    122	ASPEED_I2C_MASTER_PENDING,
    123	ASPEED_I2C_MASTER_START,
    124	ASPEED_I2C_MASTER_TX_FIRST,
    125	ASPEED_I2C_MASTER_TX,
    126	ASPEED_I2C_MASTER_RX_FIRST,
    127	ASPEED_I2C_MASTER_RX,
    128	ASPEED_I2C_MASTER_STOP,
    129};
    130
    131enum aspeed_i2c_slave_state {
    132	ASPEED_I2C_SLAVE_INACTIVE,
    133	ASPEED_I2C_SLAVE_START,
    134	ASPEED_I2C_SLAVE_READ_REQUESTED,
    135	ASPEED_I2C_SLAVE_READ_PROCESSED,
    136	ASPEED_I2C_SLAVE_WRITE_REQUESTED,
    137	ASPEED_I2C_SLAVE_WRITE_RECEIVED,
    138	ASPEED_I2C_SLAVE_STOP,
    139};
    140
    141struct aspeed_i2c_bus {
    142	struct i2c_adapter		adap;
    143	struct device			*dev;
    144	void __iomem			*base;
    145	struct reset_control		*rst;
    146	/* Synchronizes I/O mem access to base. */
    147	spinlock_t			lock;
    148	struct completion		cmd_complete;
    149	u32				(*get_clk_reg_val)(struct device *dev,
    150							   u32 divisor);
    151	unsigned long			parent_clk_frequency;
    152	u32				bus_frequency;
    153	/* Transaction state. */
    154	enum aspeed_i2c_master_state	master_state;
    155	struct i2c_msg			*msgs;
    156	size_t				buf_index;
    157	size_t				msgs_index;
    158	size_t				msgs_count;
    159	bool				send_stop;
    160	int				cmd_err;
    161	/* Protected only by i2c_lock_bus */
    162	int				master_xfer_result;
    163	/* Multi-master */
    164	bool				multi_master;
    165#if IS_ENABLED(CONFIG_I2C_SLAVE)
    166	struct i2c_client		*slave;
    167	enum aspeed_i2c_slave_state	slave_state;
    168#endif /* CONFIG_I2C_SLAVE */
    169};
    170
    171static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus);
    172
    173static int aspeed_i2c_recover_bus(struct aspeed_i2c_bus *bus)
    174{
    175	unsigned long time_left, flags;
    176	int ret = 0;
    177	u32 command;
    178
    179	spin_lock_irqsave(&bus->lock, flags);
    180	command = readl(bus->base + ASPEED_I2C_CMD_REG);
    181
    182	if (command & ASPEED_I2CD_SDA_LINE_STS) {
    183		/* Bus is idle: no recovery needed. */
    184		if (command & ASPEED_I2CD_SCL_LINE_STS)
    185			goto out;
    186		dev_dbg(bus->dev, "SCL hung (state %x), attempting recovery\n",
    187			command);
    188
    189		reinit_completion(&bus->cmd_complete);
    190		writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
    191		spin_unlock_irqrestore(&bus->lock, flags);
    192
    193		time_left = wait_for_completion_timeout(
    194				&bus->cmd_complete, bus->adap.timeout);
    195
    196		spin_lock_irqsave(&bus->lock, flags);
    197		if (time_left == 0)
    198			goto reset_out;
    199		else if (bus->cmd_err)
    200			goto reset_out;
    201		/* Recovery failed. */
    202		else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) &
    203			   ASPEED_I2CD_SCL_LINE_STS))
    204			goto reset_out;
    205	/* Bus error. */
    206	} else {
    207		dev_dbg(bus->dev, "SDA hung (state %x), attempting recovery\n",
    208			command);
    209
    210		reinit_completion(&bus->cmd_complete);
    211		/* Writes 1 to 8 SCL clock cycles until SDA is released. */
    212		writel(ASPEED_I2CD_BUS_RECOVER_CMD,
    213		       bus->base + ASPEED_I2C_CMD_REG);
    214		spin_unlock_irqrestore(&bus->lock, flags);
    215
    216		time_left = wait_for_completion_timeout(
    217				&bus->cmd_complete, bus->adap.timeout);
    218
    219		spin_lock_irqsave(&bus->lock, flags);
    220		if (time_left == 0)
    221			goto reset_out;
    222		else if (bus->cmd_err)
    223			goto reset_out;
    224		/* Recovery failed. */
    225		else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) &
    226			   ASPEED_I2CD_SDA_LINE_STS))
    227			goto reset_out;
    228	}
    229
    230out:
    231	spin_unlock_irqrestore(&bus->lock, flags);
    232
    233	return ret;
    234
    235reset_out:
    236	spin_unlock_irqrestore(&bus->lock, flags);
    237
    238	return aspeed_i2c_reset(bus);
    239}
    240
    241#if IS_ENABLED(CONFIG_I2C_SLAVE)
    242static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
    243{
    244	u32 command, irq_handled = 0;
    245	struct i2c_client *slave = bus->slave;
    246	u8 value;
    247
    248	if (!slave)
    249		return 0;
    250
    251	command = readl(bus->base + ASPEED_I2C_CMD_REG);
    252
    253	/* Slave was requested, restart state machine. */
    254	if (irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH) {
    255		irq_handled |= ASPEED_I2CD_INTR_SLAVE_MATCH;
    256		bus->slave_state = ASPEED_I2C_SLAVE_START;
    257	}
    258
    259	/* Slave is not currently active, irq was for someone else. */
    260	if (bus->slave_state == ASPEED_I2C_SLAVE_INACTIVE)
    261		return irq_handled;
    262
    263	dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n",
    264		irq_status, command);
    265
    266	/* Slave was sent something. */
    267	if (irq_status & ASPEED_I2CD_INTR_RX_DONE) {
    268		value = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
    269		/* Handle address frame. */
    270		if (bus->slave_state == ASPEED_I2C_SLAVE_START) {
    271			if (value & 0x1)
    272				bus->slave_state =
    273						ASPEED_I2C_SLAVE_READ_REQUESTED;
    274			else
    275				bus->slave_state =
    276						ASPEED_I2C_SLAVE_WRITE_REQUESTED;
    277		}
    278		irq_handled |= ASPEED_I2CD_INTR_RX_DONE;
    279	}
    280
    281	/* Slave was asked to stop. */
    282	if (irq_status & ASPEED_I2CD_INTR_NORMAL_STOP) {
    283		irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP;
    284		bus->slave_state = ASPEED_I2C_SLAVE_STOP;
    285	}
    286	if (irq_status & ASPEED_I2CD_INTR_TX_NAK &&
    287	    bus->slave_state == ASPEED_I2C_SLAVE_READ_PROCESSED) {
    288		irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
    289		bus->slave_state = ASPEED_I2C_SLAVE_STOP;
    290	}
    291
    292	switch (bus->slave_state) {
    293	case ASPEED_I2C_SLAVE_READ_REQUESTED:
    294		if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_ACK))
    295			dev_err(bus->dev, "Unexpected ACK on read request.\n");
    296		bus->slave_state = ASPEED_I2C_SLAVE_READ_PROCESSED;
    297		i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
    298		writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
    299		writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
    300		break;
    301	case ASPEED_I2C_SLAVE_READ_PROCESSED:
    302		if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
    303			dev_err(bus->dev,
    304				"Expected ACK after processed read.\n");
    305			break;
    306		}
    307		irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
    308		i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
    309		writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
    310		writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
    311		break;
    312	case ASPEED_I2C_SLAVE_WRITE_REQUESTED:
    313		bus->slave_state = ASPEED_I2C_SLAVE_WRITE_RECEIVED;
    314		i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
    315		break;
    316	case ASPEED_I2C_SLAVE_WRITE_RECEIVED:
    317		i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, &value);
    318		break;
    319	case ASPEED_I2C_SLAVE_STOP:
    320		i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
    321		bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
    322		break;
    323	case ASPEED_I2C_SLAVE_START:
    324		/* Slave was just started. Waiting for the next event. */;
    325		break;
    326	default:
    327		dev_err(bus->dev, "unknown slave_state: %d\n",
    328			bus->slave_state);
    329		bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
    330		break;
    331	}
    332
    333	return irq_handled;
    334}
    335#endif /* CONFIG_I2C_SLAVE */
    336
    337/* precondition: bus.lock has been acquired. */
    338static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus)
    339{
    340	u32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD;
    341	struct i2c_msg *msg = &bus->msgs[bus->msgs_index];
    342	u8 slave_addr = i2c_8bit_addr_from_msg(msg);
    343
    344#if IS_ENABLED(CONFIG_I2C_SLAVE)
    345	/*
    346	 * If it's requested in the middle of a slave session, set the master
    347	 * state to 'pending' then H/W will continue handling this master
    348	 * command when the bus comes back to the idle state.
    349	 */
    350	if (bus->slave_state != ASPEED_I2C_SLAVE_INACTIVE) {
    351		bus->master_state = ASPEED_I2C_MASTER_PENDING;
    352		return;
    353	}
    354#endif /* CONFIG_I2C_SLAVE */
    355
    356	bus->master_state = ASPEED_I2C_MASTER_START;
    357	bus->buf_index = 0;
    358
    359	if (msg->flags & I2C_M_RD) {
    360		command |= ASPEED_I2CD_M_RX_CMD;
    361		/* Need to let the hardware know to NACK after RX. */
    362		if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN))
    363			command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
    364	}
    365
    366	writel(slave_addr, bus->base + ASPEED_I2C_BYTE_BUF_REG);
    367	writel(command, bus->base + ASPEED_I2C_CMD_REG);
    368}
    369
    370/* precondition: bus.lock has been acquired. */
    371static void aspeed_i2c_do_stop(struct aspeed_i2c_bus *bus)
    372{
    373	bus->master_state = ASPEED_I2C_MASTER_STOP;
    374	writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
    375}
    376
    377/* precondition: bus.lock has been acquired. */
    378static void aspeed_i2c_next_msg_or_stop(struct aspeed_i2c_bus *bus)
    379{
    380	if (bus->msgs_index + 1 < bus->msgs_count) {
    381		bus->msgs_index++;
    382		aspeed_i2c_do_start(bus);
    383	} else {
    384		aspeed_i2c_do_stop(bus);
    385	}
    386}
    387
    388static int aspeed_i2c_is_irq_error(u32 irq_status)
    389{
    390	if (irq_status & ASPEED_I2CD_INTR_ARBIT_LOSS)
    391		return -EAGAIN;
    392	if (irq_status & (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |
    393			  ASPEED_I2CD_INTR_SCL_TIMEOUT))
    394		return -EBUSY;
    395	if (irq_status & (ASPEED_I2CD_INTR_ABNORMAL))
    396		return -EPROTO;
    397
    398	return 0;
    399}
    400
    401static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
    402{
    403	u32 irq_handled = 0, command = 0;
    404	struct i2c_msg *msg;
    405	u8 recv_byte;
    406	int ret;
    407
    408	if (irq_status & ASPEED_I2CD_INTR_BUS_RECOVER_DONE) {
    409		bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
    410		irq_handled |= ASPEED_I2CD_INTR_BUS_RECOVER_DONE;
    411		goto out_complete;
    412	}
    413
    414	/*
    415	 * We encountered an interrupt that reports an error: the hardware
    416	 * should clear the command queue effectively taking us back to the
    417	 * INACTIVE state.
    418	 */
    419	ret = aspeed_i2c_is_irq_error(irq_status);
    420	if (ret) {
    421		dev_dbg(bus->dev, "received error interrupt: 0x%08x\n",
    422			irq_status);
    423		irq_handled |= (irq_status & ASPEED_I2CD_INTR_MASTER_ERRORS);
    424		if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE) {
    425			bus->cmd_err = ret;
    426			bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
    427			goto out_complete;
    428		}
    429	}
    430
    431	/* Master is not currently active, irq was for someone else. */
    432	if (bus->master_state == ASPEED_I2C_MASTER_INACTIVE ||
    433	    bus->master_state == ASPEED_I2C_MASTER_PENDING)
    434		goto out_no_complete;
    435
    436	/* We are in an invalid state; reset bus to a known state. */
    437	if (!bus->msgs) {
    438		dev_err(bus->dev, "bus in unknown state. irq_status: 0x%x\n",
    439			irq_status);
    440		bus->cmd_err = -EIO;
    441		if (bus->master_state != ASPEED_I2C_MASTER_STOP &&
    442		    bus->master_state != ASPEED_I2C_MASTER_INACTIVE)
    443			aspeed_i2c_do_stop(bus);
    444		goto out_no_complete;
    445	}
    446	msg = &bus->msgs[bus->msgs_index];
    447
    448	/*
    449	 * START is a special case because we still have to handle a subsequent
    450	 * TX or RX immediately after we handle it, so we handle it here and
    451	 * then update the state and handle the new state below.
    452	 */
    453	if (bus->master_state == ASPEED_I2C_MASTER_START) {
    454#if IS_ENABLED(CONFIG_I2C_SLAVE)
    455		/*
    456		 * If a peer master starts a xfer immediately after it queues a
    457		 * master command, clear the queued master command and change
    458		 * its state to 'pending'. To simplify handling of pending
    459		 * cases, it uses S/W solution instead of H/W command queue
    460		 * handling.
    461		 */
    462		if (unlikely(irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH)) {
    463			writel(readl(bus->base + ASPEED_I2C_CMD_REG) &
    464				~ASPEED_I2CD_MASTER_CMDS_MASK,
    465			       bus->base + ASPEED_I2C_CMD_REG);
    466			bus->master_state = ASPEED_I2C_MASTER_PENDING;
    467			dev_dbg(bus->dev,
    468				"master goes pending due to a slave start\n");
    469			goto out_no_complete;
    470		}
    471#endif /* CONFIG_I2C_SLAVE */
    472		if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
    473			if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_NAK))) {
    474				bus->cmd_err = -ENXIO;
    475				bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
    476				goto out_complete;
    477			}
    478			pr_devel("no slave present at %02x\n", msg->addr);
    479			irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
    480			bus->cmd_err = -ENXIO;
    481			aspeed_i2c_do_stop(bus);
    482			goto out_no_complete;
    483		}
    484		irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
    485		if (msg->len == 0) { /* SMBUS_QUICK */
    486			aspeed_i2c_do_stop(bus);
    487			goto out_no_complete;
    488		}
    489		if (msg->flags & I2C_M_RD)
    490			bus->master_state = ASPEED_I2C_MASTER_RX_FIRST;
    491		else
    492			bus->master_state = ASPEED_I2C_MASTER_TX_FIRST;
    493	}
    494
    495	switch (bus->master_state) {
    496	case ASPEED_I2C_MASTER_TX:
    497		if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_NAK)) {
    498			dev_dbg(bus->dev, "slave NACKed TX\n");
    499			irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
    500			goto error_and_stop;
    501		} else if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
    502			dev_err(bus->dev, "slave failed to ACK TX\n");
    503			goto error_and_stop;
    504		}
    505		irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
    506		fallthrough;
    507	case ASPEED_I2C_MASTER_TX_FIRST:
    508		if (bus->buf_index < msg->len) {
    509			bus->master_state = ASPEED_I2C_MASTER_TX;
    510			writel(msg->buf[bus->buf_index++],
    511			       bus->base + ASPEED_I2C_BYTE_BUF_REG);
    512			writel(ASPEED_I2CD_M_TX_CMD,
    513			       bus->base + ASPEED_I2C_CMD_REG);
    514		} else {
    515			aspeed_i2c_next_msg_or_stop(bus);
    516		}
    517		goto out_no_complete;
    518	case ASPEED_I2C_MASTER_RX_FIRST:
    519		/* RX may not have completed yet (only address cycle) */
    520		if (!(irq_status & ASPEED_I2CD_INTR_RX_DONE))
    521			goto out_no_complete;
    522		fallthrough;
    523	case ASPEED_I2C_MASTER_RX:
    524		if (unlikely(!(irq_status & ASPEED_I2CD_INTR_RX_DONE))) {
    525			dev_err(bus->dev, "master failed to RX\n");
    526			goto error_and_stop;
    527		}
    528		irq_handled |= ASPEED_I2CD_INTR_RX_DONE;
    529
    530		recv_byte = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
    531		msg->buf[bus->buf_index++] = recv_byte;
    532
    533		if (msg->flags & I2C_M_RECV_LEN) {
    534			if (unlikely(recv_byte > I2C_SMBUS_BLOCK_MAX)) {
    535				bus->cmd_err = -EPROTO;
    536				aspeed_i2c_do_stop(bus);
    537				goto out_no_complete;
    538			}
    539			msg->len = recv_byte +
    540					((msg->flags & I2C_CLIENT_PEC) ? 2 : 1);
    541			msg->flags &= ~I2C_M_RECV_LEN;
    542		}
    543
    544		if (bus->buf_index < msg->len) {
    545			bus->master_state = ASPEED_I2C_MASTER_RX;
    546			command = ASPEED_I2CD_M_RX_CMD;
    547			if (bus->buf_index + 1 == msg->len)
    548				command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
    549			writel(command, bus->base + ASPEED_I2C_CMD_REG);
    550		} else {
    551			aspeed_i2c_next_msg_or_stop(bus);
    552		}
    553		goto out_no_complete;
    554	case ASPEED_I2C_MASTER_STOP:
    555		if (unlikely(!(irq_status & ASPEED_I2CD_INTR_NORMAL_STOP))) {
    556			dev_err(bus->dev,
    557				"master failed to STOP. irq_status:0x%x\n",
    558				irq_status);
    559			bus->cmd_err = -EIO;
    560			/* Do not STOP as we have already tried. */
    561		} else {
    562			irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP;
    563		}
    564
    565		bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
    566		goto out_complete;
    567	case ASPEED_I2C_MASTER_INACTIVE:
    568		dev_err(bus->dev,
    569			"master received interrupt 0x%08x, but is inactive\n",
    570			irq_status);
    571		bus->cmd_err = -EIO;
    572		/* Do not STOP as we should be inactive. */
    573		goto out_complete;
    574	default:
    575		WARN(1, "unknown master state\n");
    576		bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
    577		bus->cmd_err = -EINVAL;
    578		goto out_complete;
    579	}
    580error_and_stop:
    581	bus->cmd_err = -EIO;
    582	aspeed_i2c_do_stop(bus);
    583	goto out_no_complete;
    584out_complete:
    585	bus->msgs = NULL;
    586	if (bus->cmd_err)
    587		bus->master_xfer_result = bus->cmd_err;
    588	else
    589		bus->master_xfer_result = bus->msgs_index + 1;
    590	complete(&bus->cmd_complete);
    591out_no_complete:
    592	return irq_handled;
    593}
    594
    595static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id)
    596{
    597	struct aspeed_i2c_bus *bus = dev_id;
    598	u32 irq_received, irq_remaining, irq_handled;
    599
    600	spin_lock(&bus->lock);
    601	irq_received = readl(bus->base + ASPEED_I2C_INTR_STS_REG);
    602	/* Ack all interrupts except for Rx done */
    603	writel(irq_received & ~ASPEED_I2CD_INTR_RX_DONE,
    604	       bus->base + ASPEED_I2C_INTR_STS_REG);
    605	readl(bus->base + ASPEED_I2C_INTR_STS_REG);
    606	irq_received &= ASPEED_I2CD_INTR_RECV_MASK;
    607	irq_remaining = irq_received;
    608
    609#if IS_ENABLED(CONFIG_I2C_SLAVE)
    610	/*
    611	 * In most cases, interrupt bits will be set one by one, although
    612	 * multiple interrupt bits could be set at the same time. It's also
    613	 * possible that master interrupt bits could be set along with slave
    614	 * interrupt bits. Each case needs to be handled using corresponding
    615	 * handlers depending on the current state.
    616	 */
    617	if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE &&
    618	    bus->master_state != ASPEED_I2C_MASTER_PENDING) {
    619		irq_handled = aspeed_i2c_master_irq(bus, irq_remaining);
    620		irq_remaining &= ~irq_handled;
    621		if (irq_remaining)
    622			irq_handled |= aspeed_i2c_slave_irq(bus, irq_remaining);
    623	} else {
    624		irq_handled = aspeed_i2c_slave_irq(bus, irq_remaining);
    625		irq_remaining &= ~irq_handled;
    626		if (irq_remaining)
    627			irq_handled |= aspeed_i2c_master_irq(bus,
    628							     irq_remaining);
    629	}
    630
    631	/*
    632	 * Start a pending master command at here if a slave operation is
    633	 * completed.
    634	 */
    635	if (bus->master_state == ASPEED_I2C_MASTER_PENDING &&
    636	    bus->slave_state == ASPEED_I2C_SLAVE_INACTIVE)
    637		aspeed_i2c_do_start(bus);
    638#else
    639	irq_handled = aspeed_i2c_master_irq(bus, irq_remaining);
    640#endif /* CONFIG_I2C_SLAVE */
    641
    642	irq_remaining &= ~irq_handled;
    643	if (irq_remaining)
    644		dev_err(bus->dev,
    645			"irq handled != irq. expected 0x%08x, but was 0x%08x\n",
    646			irq_received, irq_handled);
    647
    648	/* Ack Rx done */
    649	if (irq_received & ASPEED_I2CD_INTR_RX_DONE) {
    650		writel(ASPEED_I2CD_INTR_RX_DONE,
    651		       bus->base + ASPEED_I2C_INTR_STS_REG);
    652		readl(bus->base + ASPEED_I2C_INTR_STS_REG);
    653	}
    654	spin_unlock(&bus->lock);
    655	return irq_remaining ? IRQ_NONE : IRQ_HANDLED;
    656}
    657
    658static int aspeed_i2c_master_xfer(struct i2c_adapter *adap,
    659				  struct i2c_msg *msgs, int num)
    660{
    661	struct aspeed_i2c_bus *bus = i2c_get_adapdata(adap);
    662	unsigned long time_left, flags;
    663
    664	spin_lock_irqsave(&bus->lock, flags);
    665	bus->cmd_err = 0;
    666
    667	/* If bus is busy in a single master environment, attempt recovery. */
    668	if (!bus->multi_master &&
    669	    (readl(bus->base + ASPEED_I2C_CMD_REG) &
    670	     ASPEED_I2CD_BUS_BUSY_STS)) {
    671		int ret;
    672
    673		spin_unlock_irqrestore(&bus->lock, flags);
    674		ret = aspeed_i2c_recover_bus(bus);
    675		if (ret)
    676			return ret;
    677		spin_lock_irqsave(&bus->lock, flags);
    678	}
    679
    680	bus->cmd_err = 0;
    681	bus->msgs = msgs;
    682	bus->msgs_index = 0;
    683	bus->msgs_count = num;
    684
    685	reinit_completion(&bus->cmd_complete);
    686	aspeed_i2c_do_start(bus);
    687	spin_unlock_irqrestore(&bus->lock, flags);
    688
    689	time_left = wait_for_completion_timeout(&bus->cmd_complete,
    690						bus->adap.timeout);
    691
    692	if (time_left == 0) {
    693		/*
    694		 * If timed out and bus is still busy in a multi master
    695		 * environment, attempt recovery at here.
    696		 */
    697		if (bus->multi_master &&
    698		    (readl(bus->base + ASPEED_I2C_CMD_REG) &
    699		     ASPEED_I2CD_BUS_BUSY_STS))
    700			aspeed_i2c_recover_bus(bus);
    701
    702		/*
    703		 * If timed out and the state is still pending, drop the pending
    704		 * master command.
    705		 */
    706		spin_lock_irqsave(&bus->lock, flags);
    707		if (bus->master_state == ASPEED_I2C_MASTER_PENDING)
    708			bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
    709		spin_unlock_irqrestore(&bus->lock, flags);
    710
    711		return -ETIMEDOUT;
    712	}
    713
    714	return bus->master_xfer_result;
    715}
    716
    717static u32 aspeed_i2c_functionality(struct i2c_adapter *adap)
    718{
    719	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
    720}
    721
    722#if IS_ENABLED(CONFIG_I2C_SLAVE)
    723/* precondition: bus.lock has been acquired. */
    724static void __aspeed_i2c_reg_slave(struct aspeed_i2c_bus *bus, u16 slave_addr)
    725{
    726	u32 addr_reg_val, func_ctrl_reg_val;
    727
    728	/*
    729	 * Set slave addr.  Reserved bits can all safely be written with zeros
    730	 * on all of ast2[456]00, so zero everything else to ensure we only
    731	 * enable a single slave address (ast2500 has two, ast2600 has three,
    732	 * the enable bits for which are also in this register) so that we don't
    733	 * end up with additional phantom devices responding on the bus.
    734	 */
    735	addr_reg_val = slave_addr & ASPEED_I2CD_DEV_ADDR_MASK;
    736	writel(addr_reg_val, bus->base + ASPEED_I2C_DEV_ADDR_REG);
    737
    738	/* Turn on slave mode. */
    739	func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG);
    740	func_ctrl_reg_val |= ASPEED_I2CD_SLAVE_EN;
    741	writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
    742}
    743
    744static int aspeed_i2c_reg_slave(struct i2c_client *client)
    745{
    746	struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter);
    747	unsigned long flags;
    748
    749	spin_lock_irqsave(&bus->lock, flags);
    750	if (bus->slave) {
    751		spin_unlock_irqrestore(&bus->lock, flags);
    752		return -EINVAL;
    753	}
    754
    755	__aspeed_i2c_reg_slave(bus, client->addr);
    756
    757	bus->slave = client;
    758	bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
    759	spin_unlock_irqrestore(&bus->lock, flags);
    760
    761	return 0;
    762}
    763
    764static int aspeed_i2c_unreg_slave(struct i2c_client *client)
    765{
    766	struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter);
    767	u32 func_ctrl_reg_val;
    768	unsigned long flags;
    769
    770	spin_lock_irqsave(&bus->lock, flags);
    771	if (!bus->slave) {
    772		spin_unlock_irqrestore(&bus->lock, flags);
    773		return -EINVAL;
    774	}
    775
    776	/* Turn off slave mode. */
    777	func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG);
    778	func_ctrl_reg_val &= ~ASPEED_I2CD_SLAVE_EN;
    779	writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
    780
    781	bus->slave = NULL;
    782	spin_unlock_irqrestore(&bus->lock, flags);
    783
    784	return 0;
    785}
    786#endif /* CONFIG_I2C_SLAVE */
    787
    788static const struct i2c_algorithm aspeed_i2c_algo = {
    789	.master_xfer	= aspeed_i2c_master_xfer,
    790	.functionality	= aspeed_i2c_functionality,
    791#if IS_ENABLED(CONFIG_I2C_SLAVE)
    792	.reg_slave	= aspeed_i2c_reg_slave,
    793	.unreg_slave	= aspeed_i2c_unreg_slave,
    794#endif /* CONFIG_I2C_SLAVE */
    795};
    796
    797static u32 aspeed_i2c_get_clk_reg_val(struct device *dev,
    798				      u32 clk_high_low_mask,
    799				      u32 divisor)
    800{
    801	u32 base_clk_divisor, clk_high_low_max, clk_high, clk_low, tmp;
    802
    803	/*
    804	 * SCL_high and SCL_low represent a value 1 greater than what is stored
    805	 * since a zero divider is meaningless. Thus, the max value each can
    806	 * store is every bit set + 1. Since SCL_high and SCL_low are added
    807	 * together (see below), the max value of both is the max value of one
    808	 * them times two.
    809	 */
    810	clk_high_low_max = (clk_high_low_mask + 1) * 2;
    811
    812	/*
    813	 * The actual clock frequency of SCL is:
    814	 *	SCL_freq = APB_freq / (base_freq * (SCL_high + SCL_low))
    815	 *		 = APB_freq / divisor
    816	 * where base_freq is a programmable clock divider; its value is
    817	 *	base_freq = 1 << base_clk_divisor
    818	 * SCL_high is the number of base_freq clock cycles that SCL stays high
    819	 * and SCL_low is the number of base_freq clock cycles that SCL stays
    820	 * low for a period of SCL.
    821	 * The actual register has a minimum SCL_high and SCL_low minimum of 1;
    822	 * thus, they start counting at zero. So
    823	 *	SCL_high = clk_high + 1
    824	 *	SCL_low	 = clk_low + 1
    825	 * Thus,
    826	 *	SCL_freq = APB_freq /
    827	 *		((1 << base_clk_divisor) * (clk_high + 1 + clk_low + 1))
    828	 * The documentation recommends clk_high >= clk_high_max / 2 and
    829	 * clk_low >= clk_low_max / 2 - 1 when possible; this last constraint
    830	 * gives us the following solution:
    831	 */
    832	base_clk_divisor = divisor > clk_high_low_max ?
    833			ilog2((divisor - 1) / clk_high_low_max) + 1 : 0;
    834
    835	if (base_clk_divisor > ASPEED_I2CD_TIME_BASE_DIVISOR_MASK) {
    836		base_clk_divisor = ASPEED_I2CD_TIME_BASE_DIVISOR_MASK;
    837		clk_low = clk_high_low_mask;
    838		clk_high = clk_high_low_mask;
    839		dev_err(dev,
    840			"clamping clock divider: divider requested, %u, is greater than largest possible divider, %u.\n",
    841			divisor, (1 << base_clk_divisor) * clk_high_low_max);
    842	} else {
    843		tmp = (divisor + (1 << base_clk_divisor) - 1)
    844				>> base_clk_divisor;
    845		clk_low = tmp / 2;
    846		clk_high = tmp - clk_low;
    847
    848		if (clk_high)
    849			clk_high--;
    850
    851		if (clk_low)
    852			clk_low--;
    853	}
    854
    855
    856	return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT)
    857		& ASPEED_I2CD_TIME_SCL_HIGH_MASK)
    858			| ((clk_low << ASPEED_I2CD_TIME_SCL_LOW_SHIFT)
    859			   & ASPEED_I2CD_TIME_SCL_LOW_MASK)
    860			| (base_clk_divisor
    861			   & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK);
    862}
    863
    864static u32 aspeed_i2c_24xx_get_clk_reg_val(struct device *dev, u32 divisor)
    865{
    866	/*
    867	 * clk_high and clk_low are each 3 bits wide, so each can hold a max
    868	 * value of 8 giving a clk_high_low_max of 16.
    869	 */
    870	return aspeed_i2c_get_clk_reg_val(dev, GENMASK(2, 0), divisor);
    871}
    872
    873static u32 aspeed_i2c_25xx_get_clk_reg_val(struct device *dev, u32 divisor)
    874{
    875	/*
    876	 * clk_high and clk_low are each 4 bits wide, so each can hold a max
    877	 * value of 16 giving a clk_high_low_max of 32.
    878	 */
    879	return aspeed_i2c_get_clk_reg_val(dev, GENMASK(3, 0), divisor);
    880}
    881
    882/* precondition: bus.lock has been acquired. */
    883static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus)
    884{
    885	u32 divisor, clk_reg_val;
    886
    887	divisor = DIV_ROUND_UP(bus->parent_clk_frequency, bus->bus_frequency);
    888	clk_reg_val = readl(bus->base + ASPEED_I2C_AC_TIMING_REG1);
    889	clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK |
    890			ASPEED_I2CD_TIME_THDSTA_MASK |
    891			ASPEED_I2CD_TIME_TACST_MASK);
    892	clk_reg_val |= bus->get_clk_reg_val(bus->dev, divisor);
    893	writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1);
    894	writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2);
    895
    896	return 0;
    897}
    898
    899/* precondition: bus.lock has been acquired. */
    900static int aspeed_i2c_init(struct aspeed_i2c_bus *bus,
    901			     struct platform_device *pdev)
    902{
    903	u32 fun_ctrl_reg = ASPEED_I2CD_MASTER_EN;
    904	int ret;
    905
    906	/* Disable everything. */
    907	writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
    908
    909	ret = aspeed_i2c_init_clk(bus);
    910	if (ret < 0)
    911		return ret;
    912
    913	if (of_property_read_bool(pdev->dev.of_node, "multi-master"))
    914		bus->multi_master = true;
    915	else
    916		fun_ctrl_reg |= ASPEED_I2CD_MULTI_MASTER_DIS;
    917
    918	/* Enable Master Mode */
    919	writel(readl(bus->base + ASPEED_I2C_FUN_CTRL_REG) | fun_ctrl_reg,
    920	       bus->base + ASPEED_I2C_FUN_CTRL_REG);
    921
    922#if IS_ENABLED(CONFIG_I2C_SLAVE)
    923	/* If slave has already been registered, re-enable it. */
    924	if (bus->slave)
    925		__aspeed_i2c_reg_slave(bus, bus->slave->addr);
    926#endif /* CONFIG_I2C_SLAVE */
    927
    928	/* Set interrupt generation of I2C controller */
    929	writel(ASPEED_I2CD_INTR_ALL, bus->base + ASPEED_I2C_INTR_CTRL_REG);
    930
    931	return 0;
    932}
    933
    934static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus)
    935{
    936	struct platform_device *pdev = to_platform_device(bus->dev);
    937	unsigned long flags;
    938	int ret;
    939
    940	spin_lock_irqsave(&bus->lock, flags);
    941
    942	/* Disable and ack all interrupts. */
    943	writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
    944	writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
    945
    946	ret = aspeed_i2c_init(bus, pdev);
    947
    948	spin_unlock_irqrestore(&bus->lock, flags);
    949
    950	return ret;
    951}
    952
    953static const struct of_device_id aspeed_i2c_bus_of_table[] = {
    954	{
    955		.compatible = "aspeed,ast2400-i2c-bus",
    956		.data = aspeed_i2c_24xx_get_clk_reg_val,
    957	},
    958	{
    959		.compatible = "aspeed,ast2500-i2c-bus",
    960		.data = aspeed_i2c_25xx_get_clk_reg_val,
    961	},
    962	{
    963		.compatible = "aspeed,ast2600-i2c-bus",
    964		.data = aspeed_i2c_25xx_get_clk_reg_val,
    965	},
    966	{ },
    967};
    968MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table);
    969
    970static int aspeed_i2c_probe_bus(struct platform_device *pdev)
    971{
    972	const struct of_device_id *match;
    973	struct aspeed_i2c_bus *bus;
    974	struct clk *parent_clk;
    975	struct resource *res;
    976	int irq, ret;
    977
    978	bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
    979	if (!bus)
    980		return -ENOMEM;
    981
    982	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
    983	bus->base = devm_ioremap_resource(&pdev->dev, res);
    984	if (IS_ERR(bus->base))
    985		return PTR_ERR(bus->base);
    986
    987	parent_clk = devm_clk_get(&pdev->dev, NULL);
    988	if (IS_ERR(parent_clk))
    989		return PTR_ERR(parent_clk);
    990	bus->parent_clk_frequency = clk_get_rate(parent_clk);
    991	/* We just need the clock rate, we don't actually use the clk object. */
    992	devm_clk_put(&pdev->dev, parent_clk);
    993
    994	bus->rst = devm_reset_control_get_shared(&pdev->dev, NULL);
    995	if (IS_ERR(bus->rst)) {
    996		dev_err(&pdev->dev,
    997			"missing or invalid reset controller device tree entry\n");
    998		return PTR_ERR(bus->rst);
    999	}
   1000	reset_control_deassert(bus->rst);
   1001
   1002	ret = of_property_read_u32(pdev->dev.of_node,
   1003				   "bus-frequency", &bus->bus_frequency);
   1004	if (ret < 0) {
   1005		dev_err(&pdev->dev,
   1006			"Could not read bus-frequency property\n");
   1007		bus->bus_frequency = I2C_MAX_STANDARD_MODE_FREQ;
   1008	}
   1009
   1010	match = of_match_node(aspeed_i2c_bus_of_table, pdev->dev.of_node);
   1011	if (!match)
   1012		bus->get_clk_reg_val = aspeed_i2c_24xx_get_clk_reg_val;
   1013	else
   1014		bus->get_clk_reg_val = (u32 (*)(struct device *, u32))
   1015				match->data;
   1016
   1017	/* Initialize the I2C adapter */
   1018	spin_lock_init(&bus->lock);
   1019	init_completion(&bus->cmd_complete);
   1020	bus->adap.owner = THIS_MODULE;
   1021	bus->adap.retries = 0;
   1022	bus->adap.algo = &aspeed_i2c_algo;
   1023	bus->adap.dev.parent = &pdev->dev;
   1024	bus->adap.dev.of_node = pdev->dev.of_node;
   1025	strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name));
   1026	i2c_set_adapdata(&bus->adap, bus);
   1027
   1028	bus->dev = &pdev->dev;
   1029
   1030	/* Clean up any left over interrupt state. */
   1031	writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
   1032	writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
   1033	/*
   1034	 * bus.lock does not need to be held because the interrupt handler has
   1035	 * not been enabled yet.
   1036	 */
   1037	ret = aspeed_i2c_init(bus, pdev);
   1038	if (ret < 0)
   1039		return ret;
   1040
   1041	irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
   1042	ret = devm_request_irq(&pdev->dev, irq, aspeed_i2c_bus_irq,
   1043			       0, dev_name(&pdev->dev), bus);
   1044	if (ret < 0)
   1045		return ret;
   1046
   1047	ret = i2c_add_adapter(&bus->adap);
   1048	if (ret < 0)
   1049		return ret;
   1050
   1051	platform_set_drvdata(pdev, bus);
   1052
   1053	dev_info(bus->dev, "i2c bus %d registered, irq %d\n",
   1054		 bus->adap.nr, irq);
   1055
   1056	return 0;
   1057}
   1058
   1059static int aspeed_i2c_remove_bus(struct platform_device *pdev)
   1060{
   1061	struct aspeed_i2c_bus *bus = platform_get_drvdata(pdev);
   1062	unsigned long flags;
   1063
   1064	spin_lock_irqsave(&bus->lock, flags);
   1065
   1066	/* Disable everything. */
   1067	writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
   1068	writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
   1069
   1070	spin_unlock_irqrestore(&bus->lock, flags);
   1071
   1072	reset_control_assert(bus->rst);
   1073
   1074	i2c_del_adapter(&bus->adap);
   1075
   1076	return 0;
   1077}
   1078
   1079static struct platform_driver aspeed_i2c_bus_driver = {
   1080	.probe		= aspeed_i2c_probe_bus,
   1081	.remove		= aspeed_i2c_remove_bus,
   1082	.driver		= {
   1083		.name		= "aspeed-i2c-bus",
   1084		.of_match_table	= aspeed_i2c_bus_of_table,
   1085	},
   1086};
   1087module_platform_driver(aspeed_i2c_bus_driver);
   1088
   1089MODULE_AUTHOR("Brendan Higgins <brendanhiggins@google.com>");
   1090MODULE_DESCRIPTION("Aspeed I2C Bus Driver");
   1091MODULE_LICENSE("GPL v2");