cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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i2c-lpc2k.c (12198B)


      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Copyright (C) 2011 NXP Semiconductors
      4 *
      5 * Code portions referenced from the i2x-pxa and i2c-pnx drivers
      6 *
      7 * Make SMBus byte and word transactions work on LPC178x/7x
      8 * Copyright (c) 2012
      9 * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
     10 * Anton Protopopov, Emcraft Systems, antonp@emcraft.com
     11 *
     12 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
     13 */
     14
     15#include <linux/clk.h>
     16#include <linux/errno.h>
     17#include <linux/i2c.h>
     18#include <linux/interrupt.h>
     19#include <linux/io.h>
     20#include <linux/kernel.h>
     21#include <linux/module.h>
     22#include <linux/of.h>
     23#include <linux/of_device.h>
     24#include <linux/platform_device.h>
     25#include <linux/sched.h>
     26#include <linux/time.h>
     27
     28/* LPC24xx register offsets and bits */
     29#define LPC24XX_I2CONSET	0x00
     30#define LPC24XX_I2STAT		0x04
     31#define LPC24XX_I2DAT		0x08
     32#define LPC24XX_I2ADDR		0x0c
     33#define LPC24XX_I2SCLH		0x10
     34#define LPC24XX_I2SCLL		0x14
     35#define LPC24XX_I2CONCLR	0x18
     36
     37#define LPC24XX_AA		BIT(2)
     38#define LPC24XX_SI		BIT(3)
     39#define LPC24XX_STO		BIT(4)
     40#define LPC24XX_STA		BIT(5)
     41#define LPC24XX_I2EN		BIT(6)
     42
     43#define LPC24XX_STO_AA		(LPC24XX_STO | LPC24XX_AA)
     44#define LPC24XX_CLEAR_ALL	(LPC24XX_AA | LPC24XX_SI | LPC24XX_STO | \
     45				 LPC24XX_STA | LPC24XX_I2EN)
     46
     47/* I2C SCL clock has different duty cycle depending on mode */
     48#define I2C_STD_MODE_DUTY		46
     49#define I2C_FAST_MODE_DUTY		36
     50#define I2C_FAST_MODE_PLUS_DUTY		38
     51
     52/*
     53 * 26 possible I2C status codes, but codes applicable only
     54 * to master are listed here and used in this driver
     55 */
     56enum {
     57	M_BUS_ERROR		= 0x00,
     58	M_START			= 0x08,
     59	M_REPSTART		= 0x10,
     60	MX_ADDR_W_ACK		= 0x18,
     61	MX_ADDR_W_NACK		= 0x20,
     62	MX_DATA_W_ACK		= 0x28,
     63	MX_DATA_W_NACK		= 0x30,
     64	M_DATA_ARB_LOST		= 0x38,
     65	MR_ADDR_R_ACK		= 0x40,
     66	MR_ADDR_R_NACK		= 0x48,
     67	MR_DATA_R_ACK		= 0x50,
     68	MR_DATA_R_NACK		= 0x58,
     69	M_I2C_IDLE		= 0xf8,
     70};
     71
     72struct lpc2k_i2c {
     73	void __iomem		*base;
     74	struct clk		*clk;
     75	int			irq;
     76	wait_queue_head_t	wait;
     77	struct i2c_adapter	adap;
     78	struct i2c_msg		*msg;
     79	int			msg_idx;
     80	int			msg_status;
     81	int			is_last;
     82};
     83
     84static void i2c_lpc2k_reset(struct lpc2k_i2c *i2c)
     85{
     86	/* Will force clear all statuses */
     87	writel(LPC24XX_CLEAR_ALL, i2c->base + LPC24XX_I2CONCLR);
     88	writel(0, i2c->base + LPC24XX_I2ADDR);
     89	writel(LPC24XX_I2EN, i2c->base + LPC24XX_I2CONSET);
     90}
     91
     92static int i2c_lpc2k_clear_arb(struct lpc2k_i2c *i2c)
     93{
     94	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
     95
     96	/*
     97	 * If the transfer needs to abort for some reason, we'll try to
     98	 * force a stop condition to clear any pending bus conditions
     99	 */
    100	writel(LPC24XX_STO, i2c->base + LPC24XX_I2CONSET);
    101
    102	/* Wait for status change */
    103	while (readl(i2c->base + LPC24XX_I2STAT) != M_I2C_IDLE) {
    104		if (time_after(jiffies, timeout)) {
    105			/* Bus was not idle, try to reset adapter */
    106			i2c_lpc2k_reset(i2c);
    107			return -EBUSY;
    108		}
    109
    110		cpu_relax();
    111	}
    112
    113	return 0;
    114}
    115
    116static void i2c_lpc2k_pump_msg(struct lpc2k_i2c *i2c)
    117{
    118	unsigned char data;
    119	u32 status;
    120
    121	/*
    122	 * I2C in the LPC2xxx series is basically a state machine.
    123	 * Just run through the steps based on the current status.
    124	 */
    125	status = readl(i2c->base + LPC24XX_I2STAT);
    126
    127	switch (status) {
    128	case M_START:
    129	case M_REPSTART:
    130		/* Start bit was just sent out, send out addr and dir */
    131		data = i2c_8bit_addr_from_msg(i2c->msg);
    132
    133		writel(data, i2c->base + LPC24XX_I2DAT);
    134		writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
    135		break;
    136
    137	case MX_ADDR_W_ACK:
    138	case MX_DATA_W_ACK:
    139		/*
    140		 * Address or data was sent out with an ACK. If there is more
    141		 * data to send, send it now
    142		 */
    143		if (i2c->msg_idx < i2c->msg->len) {
    144			writel(i2c->msg->buf[i2c->msg_idx],
    145			       i2c->base + LPC24XX_I2DAT);
    146		} else if (i2c->is_last) {
    147			/* Last message, send stop */
    148			writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
    149			writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
    150			i2c->msg_status = 0;
    151			disable_irq_nosync(i2c->irq);
    152		} else {
    153			i2c->msg_status = 0;
    154			disable_irq_nosync(i2c->irq);
    155		}
    156
    157		i2c->msg_idx++;
    158		break;
    159
    160	case MR_ADDR_R_ACK:
    161		/* Receive first byte from slave */
    162		if (i2c->msg->len == 1) {
    163			/* Last byte, return NACK */
    164			writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR);
    165		} else {
    166			/* Not last byte, return ACK */
    167			writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET);
    168		}
    169
    170		writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
    171		break;
    172
    173	case MR_DATA_R_NACK:
    174		/*
    175		 * The I2C shows NACK status on reads, so we need to accept
    176		 * the NACK as an ACK here. This should be ok, as the real
    177		 * BACK would of been caught on the address write.
    178		 */
    179	case MR_DATA_R_ACK:
    180		/* Data was received */
    181		if (i2c->msg_idx < i2c->msg->len) {
    182			i2c->msg->buf[i2c->msg_idx] =
    183					readl(i2c->base + LPC24XX_I2DAT);
    184		}
    185
    186		/* If transfer is done, send STOP */
    187		if (i2c->msg_idx >= i2c->msg->len - 1 && i2c->is_last) {
    188			writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
    189			writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
    190			i2c->msg_status = 0;
    191		}
    192
    193		/* Message is done */
    194		if (i2c->msg_idx >= i2c->msg->len - 1) {
    195			i2c->msg_status = 0;
    196			disable_irq_nosync(i2c->irq);
    197		}
    198
    199		/*
    200		 * One pre-last data input, send NACK to tell the slave that
    201		 * this is going to be the last data byte to be transferred.
    202		 */
    203		if (i2c->msg_idx >= i2c->msg->len - 2) {
    204			/* One byte left to receive - NACK */
    205			writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR);
    206		} else {
    207			/* More than one byte left to receive - ACK */
    208			writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET);
    209		}
    210
    211		writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
    212		i2c->msg_idx++;
    213		break;
    214
    215	case MX_ADDR_W_NACK:
    216	case MX_DATA_W_NACK:
    217	case MR_ADDR_R_NACK:
    218		/* NACK processing is done */
    219		writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
    220		i2c->msg_status = -ENXIO;
    221		disable_irq_nosync(i2c->irq);
    222		break;
    223
    224	case M_DATA_ARB_LOST:
    225		/* Arbitration lost */
    226		i2c->msg_status = -EAGAIN;
    227
    228		/* Release the I2C bus */
    229		writel(LPC24XX_STA | LPC24XX_STO, i2c->base + LPC24XX_I2CONCLR);
    230		disable_irq_nosync(i2c->irq);
    231		break;
    232
    233	default:
    234		/* Unexpected statuses */
    235		i2c->msg_status = -EIO;
    236		disable_irq_nosync(i2c->irq);
    237		break;
    238	}
    239
    240	/* Exit on failure or all bytes transferred */
    241	if (i2c->msg_status != -EBUSY)
    242		wake_up(&i2c->wait);
    243
    244	/*
    245	 * If `msg_status` is zero, then `lpc2k_process_msg()`
    246	 * is responsible for clearing the SI flag.
    247	 */
    248	if (i2c->msg_status != 0)
    249		writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
    250}
    251
    252static int lpc2k_process_msg(struct lpc2k_i2c *i2c, int msgidx)
    253{
    254	/* A new transfer is kicked off by initiating a start condition */
    255	if (!msgidx) {
    256		writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET);
    257	} else {
    258		/*
    259		 * A multi-message I2C transfer continues where the
    260		 * previous I2C transfer left off and uses the
    261		 * current condition of the I2C adapter.
    262		 */
    263		if (unlikely(i2c->msg->flags & I2C_M_NOSTART)) {
    264			WARN_ON(i2c->msg->len == 0);
    265
    266			if (!(i2c->msg->flags & I2C_M_RD)) {
    267				/* Start transmit of data */
    268				writel(i2c->msg->buf[0],
    269				       i2c->base + LPC24XX_I2DAT);
    270				i2c->msg_idx++;
    271			}
    272		} else {
    273			/* Start or repeated start */
    274			writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET);
    275		}
    276
    277		writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
    278	}
    279
    280	enable_irq(i2c->irq);
    281
    282	/* Wait for transfer completion */
    283	if (wait_event_timeout(i2c->wait, i2c->msg_status != -EBUSY,
    284			       msecs_to_jiffies(1000)) == 0) {
    285		disable_irq_nosync(i2c->irq);
    286
    287		return -ETIMEDOUT;
    288	}
    289
    290	return i2c->msg_status;
    291}
    292
    293static int i2c_lpc2k_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
    294			  int msg_num)
    295{
    296	struct lpc2k_i2c *i2c = i2c_get_adapdata(adap);
    297	int ret, i;
    298	u32 stat;
    299
    300	/* Check for bus idle condition */
    301	stat = readl(i2c->base + LPC24XX_I2STAT);
    302	if (stat != M_I2C_IDLE) {
    303		/* Something is holding the bus, try to clear it */
    304		return i2c_lpc2k_clear_arb(i2c);
    305	}
    306
    307	/* Process a single message at a time */
    308	for (i = 0; i < msg_num; i++) {
    309		/* Save message pointer and current message data index */
    310		i2c->msg = &msgs[i];
    311		i2c->msg_idx = 0;
    312		i2c->msg_status = -EBUSY;
    313		i2c->is_last = (i == (msg_num - 1));
    314
    315		ret = lpc2k_process_msg(i2c, i);
    316		if (ret)
    317			return ret;
    318	}
    319
    320	return msg_num;
    321}
    322
    323static irqreturn_t i2c_lpc2k_handler(int irq, void *dev_id)
    324{
    325	struct lpc2k_i2c *i2c = dev_id;
    326
    327	if (readl(i2c->base + LPC24XX_I2CONSET) & LPC24XX_SI) {
    328		i2c_lpc2k_pump_msg(i2c);
    329		return IRQ_HANDLED;
    330	}
    331
    332	return IRQ_NONE;
    333}
    334
    335static u32 i2c_lpc2k_functionality(struct i2c_adapter *adap)
    336{
    337	/* Only emulated SMBus for now */
    338	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
    339}
    340
    341static const struct i2c_algorithm i2c_lpc2k_algorithm = {
    342	.master_xfer	= i2c_lpc2k_xfer,
    343	.functionality	= i2c_lpc2k_functionality,
    344};
    345
    346static int i2c_lpc2k_probe(struct platform_device *pdev)
    347{
    348	struct lpc2k_i2c *i2c;
    349	u32 bus_clk_rate;
    350	u32 scl_high;
    351	u32 clkrate;
    352	int ret;
    353
    354	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
    355	if (!i2c)
    356		return -ENOMEM;
    357
    358	i2c->base = devm_platform_ioremap_resource(pdev, 0);
    359	if (IS_ERR(i2c->base))
    360		return PTR_ERR(i2c->base);
    361
    362	i2c->irq = platform_get_irq(pdev, 0);
    363	if (i2c->irq < 0)
    364		return i2c->irq;
    365
    366	init_waitqueue_head(&i2c->wait);
    367
    368	i2c->clk = devm_clk_get(&pdev->dev, NULL);
    369	if (IS_ERR(i2c->clk)) {
    370		dev_err(&pdev->dev, "error getting clock\n");
    371		return PTR_ERR(i2c->clk);
    372	}
    373
    374	ret = clk_prepare_enable(i2c->clk);
    375	if (ret) {
    376		dev_err(&pdev->dev, "unable to enable clock.\n");
    377		return ret;
    378	}
    379
    380	ret = devm_request_irq(&pdev->dev, i2c->irq, i2c_lpc2k_handler, 0,
    381			       dev_name(&pdev->dev), i2c);
    382	if (ret < 0) {
    383		dev_err(&pdev->dev, "can't request interrupt.\n");
    384		goto fail_clk;
    385	}
    386
    387	disable_irq_nosync(i2c->irq);
    388
    389	/* Place controller is a known state */
    390	i2c_lpc2k_reset(i2c);
    391
    392	ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
    393				   &bus_clk_rate);
    394	if (ret)
    395		bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
    396
    397	clkrate = clk_get_rate(i2c->clk);
    398	if (clkrate == 0) {
    399		dev_err(&pdev->dev, "can't get I2C base clock\n");
    400		ret = -EINVAL;
    401		goto fail_clk;
    402	}
    403
    404	/* Setup I2C dividers to generate clock with proper duty cycle */
    405	clkrate = clkrate / bus_clk_rate;
    406	if (bus_clk_rate <= I2C_MAX_STANDARD_MODE_FREQ)
    407		scl_high = (clkrate * I2C_STD_MODE_DUTY) / 100;
    408	else if (bus_clk_rate <= I2C_MAX_FAST_MODE_FREQ)
    409		scl_high = (clkrate * I2C_FAST_MODE_DUTY) / 100;
    410	else
    411		scl_high = (clkrate * I2C_FAST_MODE_PLUS_DUTY) / 100;
    412
    413	writel(scl_high, i2c->base + LPC24XX_I2SCLH);
    414	writel(clkrate - scl_high, i2c->base + LPC24XX_I2SCLL);
    415
    416	platform_set_drvdata(pdev, i2c);
    417
    418	i2c_set_adapdata(&i2c->adap, i2c);
    419	i2c->adap.owner = THIS_MODULE;
    420	strlcpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name));
    421	i2c->adap.algo = &i2c_lpc2k_algorithm;
    422	i2c->adap.dev.parent = &pdev->dev;
    423	i2c->adap.dev.of_node = pdev->dev.of_node;
    424
    425	ret = i2c_add_adapter(&i2c->adap);
    426	if (ret < 0)
    427		goto fail_clk;
    428
    429	dev_info(&pdev->dev, "LPC2K I2C adapter\n");
    430
    431	return 0;
    432
    433fail_clk:
    434	clk_disable_unprepare(i2c->clk);
    435	return ret;
    436}
    437
    438static int i2c_lpc2k_remove(struct platform_device *dev)
    439{
    440	struct lpc2k_i2c *i2c = platform_get_drvdata(dev);
    441
    442	i2c_del_adapter(&i2c->adap);
    443	clk_disable_unprepare(i2c->clk);
    444
    445	return 0;
    446}
    447
    448#ifdef CONFIG_PM
    449static int i2c_lpc2k_suspend(struct device *dev)
    450{
    451	struct lpc2k_i2c *i2c = dev_get_drvdata(dev);
    452
    453	clk_disable(i2c->clk);
    454
    455	return 0;
    456}
    457
    458static int i2c_lpc2k_resume(struct device *dev)
    459{
    460	struct lpc2k_i2c *i2c = dev_get_drvdata(dev);
    461
    462	clk_enable(i2c->clk);
    463	i2c_lpc2k_reset(i2c);
    464
    465	return 0;
    466}
    467
    468static const struct dev_pm_ops i2c_lpc2k_dev_pm_ops = {
    469	.suspend_noirq = i2c_lpc2k_suspend,
    470	.resume_noirq = i2c_lpc2k_resume,
    471};
    472
    473#define I2C_LPC2K_DEV_PM_OPS (&i2c_lpc2k_dev_pm_ops)
    474#else
    475#define I2C_LPC2K_DEV_PM_OPS NULL
    476#endif
    477
    478static const struct of_device_id lpc2k_i2c_match[] = {
    479	{ .compatible = "nxp,lpc1788-i2c" },
    480	{},
    481};
    482MODULE_DEVICE_TABLE(of, lpc2k_i2c_match);
    483
    484static struct platform_driver i2c_lpc2k_driver = {
    485	.probe	= i2c_lpc2k_probe,
    486	.remove	= i2c_lpc2k_remove,
    487	.driver	= {
    488		.name		= "lpc2k-i2c",
    489		.pm		= I2C_LPC2K_DEV_PM_OPS,
    490		.of_match_table	= lpc2k_i2c_match,
    491	},
    492};
    493module_platform_driver(i2c_lpc2k_driver);
    494
    495MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
    496MODULE_DESCRIPTION("I2C driver for LPC2xxx devices");
    497MODULE_LICENSE("GPL");
    498MODULE_ALIAS("platform:lpc2k-i2c");