cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
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i2c-rcar.c (31843B)


      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Driver for the Renesas R-Car I2C unit
      4 *
      5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
      6 * Copyright (C) 2011-2019 Renesas Electronics Corporation
      7 *
      8 * Copyright (C) 2012-14 Renesas Solutions Corp.
      9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
     10 *
     11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
     12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
     13 */
     14#include <linux/bitops.h>
     15#include <linux/clk.h>
     16#include <linux/delay.h>
     17#include <linux/dmaengine.h>
     18#include <linux/dma-mapping.h>
     19#include <linux/err.h>
     20#include <linux/interrupt.h>
     21#include <linux/io.h>
     22#include <linux/iopoll.h>
     23#include <linux/i2c.h>
     24#include <linux/i2c-smbus.h>
     25#include <linux/kernel.h>
     26#include <linux/module.h>
     27#include <linux/of_device.h>
     28#include <linux/platform_device.h>
     29#include <linux/pm_runtime.h>
     30#include <linux/reset.h>
     31#include <linux/slab.h>
     32
     33/* register offsets */
     34#define ICSCR	0x00	/* slave ctrl */
     35#define ICMCR	0x04	/* master ctrl */
     36#define ICSSR	0x08	/* slave status */
     37#define ICMSR	0x0C	/* master status */
     38#define ICSIER	0x10	/* slave irq enable */
     39#define ICMIER	0x14	/* master irq enable */
     40#define ICCCR	0x18	/* clock dividers */
     41#define ICSAR	0x1C	/* slave address */
     42#define ICMAR	0x20	/* master address */
     43#define ICRXTX	0x24	/* data port */
     44#define ICFBSCR	0x38	/* first bit setup cycle (Gen3) */
     45#define ICDMAER	0x3c	/* DMA enable (Gen3) */
     46
     47/* ICSCR */
     48#define SDBS	BIT(3)	/* slave data buffer select */
     49#define SIE	BIT(2)	/* slave interface enable */
     50#define GCAE	BIT(1)	/* general call address enable */
     51#define FNA	BIT(0)	/* forced non acknowledgment */
     52
     53/* ICMCR */
     54#define MDBS	BIT(7)	/* non-fifo mode switch */
     55#define FSCL	BIT(6)	/* override SCL pin */
     56#define FSDA	BIT(5)	/* override SDA pin */
     57#define OBPC	BIT(4)	/* override pins */
     58#define MIE	BIT(3)	/* master if enable */
     59#define TSBE	BIT(2)
     60#define FSB	BIT(1)	/* force stop bit */
     61#define ESG	BIT(0)	/* enable start bit gen */
     62
     63/* ICSSR (also for ICSIER) */
     64#define GCAR	BIT(6)	/* general call received */
     65#define STM	BIT(5)	/* slave transmit mode */
     66#define SSR	BIT(4)	/* stop received */
     67#define SDE	BIT(3)	/* slave data empty */
     68#define SDT	BIT(2)	/* slave data transmitted */
     69#define SDR	BIT(1)	/* slave data received */
     70#define SAR	BIT(0)	/* slave addr received */
     71
     72/* ICMSR (also for ICMIE) */
     73#define MNR	BIT(6)	/* nack received */
     74#define MAL	BIT(5)	/* arbitration lost */
     75#define MST	BIT(4)	/* sent a stop */
     76#define MDE	BIT(3)
     77#define MDT	BIT(2)
     78#define MDR	BIT(1)
     79#define MAT	BIT(0)	/* slave addr xfer done */
     80
     81/* ICDMAER */
     82#define RSDMAE	BIT(3)	/* DMA Slave Received Enable */
     83#define TSDMAE	BIT(2)	/* DMA Slave Transmitted Enable */
     84#define RMDMAE	BIT(1)	/* DMA Master Received Enable */
     85#define TMDMAE	BIT(0)	/* DMA Master Transmitted Enable */
     86
     87/* ICFBSCR */
     88#define TCYC17	0x0f		/* 17*Tcyc delay 1st bit between SDA and SCL */
     89
     90#define RCAR_MIN_DMA_LEN	8
     91
     92#define RCAR_BUS_PHASE_START	(MDBS | MIE | ESG)
     93#define RCAR_BUS_PHASE_DATA	(MDBS | MIE)
     94#define RCAR_BUS_PHASE_STOP	(MDBS | MIE | FSB)
     95
     96#define RCAR_IRQ_SEND	(MNR | MAL | MST | MAT | MDE)
     97#define RCAR_IRQ_RECV	(MNR | MAL | MST | MAT | MDR)
     98#define RCAR_IRQ_STOP	(MST)
     99
    100#define ID_LAST_MSG		BIT(0)
    101#define ID_REP_AFTER_RD		BIT(1)
    102#define ID_DONE			BIT(2)
    103#define ID_ARBLOST		BIT(3)
    104#define ID_NACK			BIT(4)
    105#define ID_EPROTO		BIT(5)
    106/* persistent flags */
    107#define ID_P_NOT_ATOMIC		BIT(28)
    108#define ID_P_HOST_NOTIFY	BIT(29)
    109#define ID_P_NO_RXDMA		BIT(30) /* HW forbids RXDMA sometimes */
    110#define ID_P_PM_BLOCKED		BIT(31)
    111#define ID_P_MASK		GENMASK(31, 28)
    112
    113enum rcar_i2c_type {
    114	I2C_RCAR_GEN1,
    115	I2C_RCAR_GEN2,
    116	I2C_RCAR_GEN3,
    117};
    118
    119struct rcar_i2c_priv {
    120	u32 flags;
    121	void __iomem *io;
    122	struct i2c_adapter adap;
    123	struct i2c_msg *msg;
    124	int msgs_left;
    125	struct clk *clk;
    126
    127	wait_queue_head_t wait;
    128
    129	int pos;
    130	u32 icccr;
    131	u8 recovery_icmcr;	/* protected by adapter lock */
    132	enum rcar_i2c_type devtype;
    133	struct i2c_client *slave;
    134
    135	struct resource *res;
    136	struct dma_chan *dma_tx;
    137	struct dma_chan *dma_rx;
    138	struct scatterlist sg;
    139	enum dma_data_direction dma_direction;
    140
    141	struct reset_control *rstc;
    142	int irq;
    143
    144	struct i2c_client *host_notify_client;
    145};
    146
    147#define rcar_i2c_priv_to_dev(p)		((p)->adap.dev.parent)
    148#define rcar_i2c_is_recv(p)		((p)->msg->flags & I2C_M_RD)
    149
    150static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
    151{
    152	writel(val, priv->io + reg);
    153}
    154
    155static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
    156{
    157	return readl(priv->io + reg);
    158}
    159
    160static void rcar_i2c_clear_irq(struct rcar_i2c_priv *priv, u32 val)
    161{
    162	writel(~val & 0x7f, priv->io + ICMSR);
    163}
    164
    165static int rcar_i2c_get_scl(struct i2c_adapter *adap)
    166{
    167	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
    168
    169	return !!(rcar_i2c_read(priv, ICMCR) & FSCL);
    170
    171};
    172
    173static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val)
    174{
    175	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
    176
    177	if (val)
    178		priv->recovery_icmcr |= FSCL;
    179	else
    180		priv->recovery_icmcr &= ~FSCL;
    181
    182	rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
    183};
    184
    185static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val)
    186{
    187	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
    188
    189	if (val)
    190		priv->recovery_icmcr |= FSDA;
    191	else
    192		priv->recovery_icmcr &= ~FSDA;
    193
    194	rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
    195};
    196
    197static int rcar_i2c_get_bus_free(struct i2c_adapter *adap)
    198{
    199	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
    200
    201	return !(rcar_i2c_read(priv, ICMCR) & FSDA);
    202
    203};
    204
    205static struct i2c_bus_recovery_info rcar_i2c_bri = {
    206	.get_scl = rcar_i2c_get_scl,
    207	.set_scl = rcar_i2c_set_scl,
    208	.set_sda = rcar_i2c_set_sda,
    209	.get_bus_free = rcar_i2c_get_bus_free,
    210	.recover_bus = i2c_generic_scl_recovery,
    211};
    212static void rcar_i2c_init(struct rcar_i2c_priv *priv)
    213{
    214	/* reset master mode */
    215	rcar_i2c_write(priv, ICMIER, 0);
    216	rcar_i2c_write(priv, ICMCR, MDBS);
    217	rcar_i2c_write(priv, ICMSR, 0);
    218	/* start clock */
    219	rcar_i2c_write(priv, ICCCR, priv->icccr);
    220
    221	if (priv->devtype == I2C_RCAR_GEN3)
    222		rcar_i2c_write(priv, ICFBSCR, TCYC17);
    223
    224}
    225
    226static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
    227{
    228	int ret;
    229	u32 val;
    230
    231	ret = readl_poll_timeout(priv->io + ICMCR, val, !(val & FSDA), 10,
    232				 priv->adap.timeout);
    233	if (ret) {
    234		/* Waiting did not help, try to recover */
    235		priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL;
    236		ret = i2c_recover_bus(&priv->adap);
    237	}
    238
    239	return ret;
    240}
    241
    242static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv)
    243{
    244	u32 scgd, cdf, round, ick, sum, scl, cdf_width;
    245	unsigned long rate;
    246	struct device *dev = rcar_i2c_priv_to_dev(priv);
    247	struct i2c_timings t = {
    248		.bus_freq_hz		= I2C_MAX_STANDARD_MODE_FREQ,
    249		.scl_fall_ns		= 35,
    250		.scl_rise_ns		= 200,
    251		.scl_int_delay_ns	= 50,
    252	};
    253
    254	/* Fall back to previously used values if not supplied */
    255	i2c_parse_fw_timings(dev, &t, false);
    256
    257	switch (priv->devtype) {
    258	case I2C_RCAR_GEN1:
    259		cdf_width = 2;
    260		break;
    261	case I2C_RCAR_GEN2:
    262	case I2C_RCAR_GEN3:
    263		cdf_width = 3;
    264		break;
    265	default:
    266		dev_err(dev, "device type error\n");
    267		return -EIO;
    268	}
    269
    270	/*
    271	 * calculate SCL clock
    272	 * see
    273	 *	ICCCR
    274	 *
    275	 * ick	= clkp / (1 + CDF)
    276	 * SCL	= ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
    277	 *
    278	 * ick  : I2C internal clock < 20 MHz
    279	 * ticf : I2C SCL falling time
    280	 * tr   : I2C SCL rising  time
    281	 * intd : LSI internal delay
    282	 * clkp : peripheral_clk
    283	 * F[]  : integer up-valuation
    284	 */
    285	rate = clk_get_rate(priv->clk);
    286	cdf = rate / 20000000;
    287	if (cdf >= 1U << cdf_width) {
    288		dev_err(dev, "Input clock %lu too high\n", rate);
    289		return -EIO;
    290	}
    291	ick = rate / (cdf + 1);
    292
    293	/*
    294	 * it is impossible to calculate large scale
    295	 * number on u32. separate it
    296	 *
    297	 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
    298	 *  = F[sum * ick / 1000000000]
    299	 *  = F[(ick / 1000000) * sum / 1000]
    300	 */
    301	sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns;
    302	round = (ick + 500000) / 1000000 * sum;
    303	round = (round + 500) / 1000;
    304
    305	/*
    306	 * SCL	= ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
    307	 *
    308	 * Calculation result (= SCL) should be less than
    309	 * bus_speed for hardware safety
    310	 *
    311	 * We could use something along the lines of
    312	 *	div = ick / (bus_speed + 1) + 1;
    313	 *	scgd = (div - 20 - round + 7) / 8;
    314	 *	scl = ick / (20 + (scgd * 8) + round);
    315	 * (not fully verified) but that would get pretty involved
    316	 */
    317	for (scgd = 0; scgd < 0x40; scgd++) {
    318		scl = ick / (20 + (scgd * 8) + round);
    319		if (scl <= t.bus_freq_hz)
    320			goto scgd_find;
    321	}
    322	dev_err(dev, "it is impossible to calculate best SCL\n");
    323	return -EIO;
    324
    325scgd_find:
    326	dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
    327		scl, t.bus_freq_hz, rate, round, cdf, scgd);
    328
    329	/* keep icccr value */
    330	priv->icccr = scgd << cdf_width | cdf;
    331
    332	return 0;
    333}
    334
    335/*
    336 * We don't have a test case but the HW engineers say that the write order of
    337 * ICMSR and ICMCR depends on whether we issue START or REP_START. So, ICMSR
    338 * handling is outside of this function. First messages clear ICMSR before this
    339 * function, interrupt handlers clear the relevant bits after this function.
    340 */
    341static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
    342{
    343	int read = !!rcar_i2c_is_recv(priv);
    344	bool rep_start = !(priv->flags & ID_REP_AFTER_RD);
    345
    346	priv->pos = 0;
    347	priv->flags &= ID_P_MASK;
    348
    349	if (priv->msgs_left == 1)
    350		priv->flags |= ID_LAST_MSG;
    351
    352	rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));
    353	if (priv->flags & ID_P_NOT_ATOMIC)
    354		rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
    355
    356	if (rep_start)
    357		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
    358}
    359
    360static void rcar_i2c_first_msg(struct rcar_i2c_priv *priv,
    361			       struct i2c_msg *msgs, int num)
    362{
    363	priv->msg = msgs;
    364	priv->msgs_left = num;
    365	rcar_i2c_write(priv, ICMSR, 0); /* must be before preparing msg */
    366	rcar_i2c_prepare_msg(priv);
    367}
    368
    369static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
    370{
    371	priv->msg++;
    372	priv->msgs_left--;
    373	rcar_i2c_prepare_msg(priv);
    374	/* ICMSR handling must come afterwards in the irq handler */
    375}
    376
    377static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv, bool terminate)
    378{
    379	struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE
    380		? priv->dma_rx : priv->dma_tx;
    381
    382	/* only allowed from thread context! */
    383	if (terminate)
    384		dmaengine_terminate_sync(chan);
    385
    386	dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
    387			 sg_dma_len(&priv->sg), priv->dma_direction);
    388
    389	/* Gen3 can only do one RXDMA per transfer and we just completed it */
    390	if (priv->devtype == I2C_RCAR_GEN3 &&
    391	    priv->dma_direction == DMA_FROM_DEVICE)
    392		priv->flags |= ID_P_NO_RXDMA;
    393
    394	priv->dma_direction = DMA_NONE;
    395
    396	/* Disable DMA Master Received/Transmitted, must be last! */
    397	rcar_i2c_write(priv, ICDMAER, 0);
    398}
    399
    400static void rcar_i2c_dma_callback(void *data)
    401{
    402	struct rcar_i2c_priv *priv = data;
    403
    404	priv->pos += sg_dma_len(&priv->sg);
    405
    406	rcar_i2c_cleanup_dma(priv, false);
    407}
    408
    409static bool rcar_i2c_dma(struct rcar_i2c_priv *priv)
    410{
    411	struct device *dev = rcar_i2c_priv_to_dev(priv);
    412	struct i2c_msg *msg = priv->msg;
    413	bool read = msg->flags & I2C_M_RD;
    414	enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
    415	struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx;
    416	struct dma_async_tx_descriptor *txdesc;
    417	dma_addr_t dma_addr;
    418	dma_cookie_t cookie;
    419	unsigned char *buf;
    420	int len;
    421
    422	/* Do various checks to see if DMA is feasible at all */
    423	if (!(priv->flags & ID_P_NOT_ATOMIC) || IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN ||
    424	    !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA))
    425		return false;
    426
    427	if (read) {
    428		/*
    429		 * The last two bytes needs to be fetched using PIO in
    430		 * order for the STOP phase to work.
    431		 */
    432		buf = priv->msg->buf;
    433		len = priv->msg->len - 2;
    434	} else {
    435		/*
    436		 * First byte in message was sent using PIO.
    437		 */
    438		buf = priv->msg->buf + 1;
    439		len = priv->msg->len - 1;
    440	}
    441
    442	dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
    443	if (dma_mapping_error(chan->device->dev, dma_addr)) {
    444		dev_dbg(dev, "dma map failed, using PIO\n");
    445		return false;
    446	}
    447
    448	sg_dma_len(&priv->sg) = len;
    449	sg_dma_address(&priv->sg) = dma_addr;
    450
    451	priv->dma_direction = dir;
    452
    453	txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1,
    454					 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
    455					 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
    456	if (!txdesc) {
    457		dev_dbg(dev, "dma prep slave sg failed, using PIO\n");
    458		rcar_i2c_cleanup_dma(priv, false);
    459		return false;
    460	}
    461
    462	txdesc->callback = rcar_i2c_dma_callback;
    463	txdesc->callback_param = priv;
    464
    465	cookie = dmaengine_submit(txdesc);
    466	if (dma_submit_error(cookie)) {
    467		dev_dbg(dev, "submitting dma failed, using PIO\n");
    468		rcar_i2c_cleanup_dma(priv, false);
    469		return false;
    470	}
    471
    472	/* Enable DMA Master Received/Transmitted */
    473	if (read)
    474		rcar_i2c_write(priv, ICDMAER, RMDMAE);
    475	else
    476		rcar_i2c_write(priv, ICDMAER, TMDMAE);
    477
    478	dma_async_issue_pending(chan);
    479	return true;
    480}
    481
    482static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
    483{
    484	struct i2c_msg *msg = priv->msg;
    485	u32 irqs_to_clear = MDE;
    486
    487	/* FIXME: sometimes, unknown interrupt happened. Do nothing */
    488	if (!(msr & MDE))
    489		return;
    490
    491	if (msr & MAT)
    492		irqs_to_clear |= MAT;
    493
    494	/* Check if DMA can be enabled and take over */
    495	if (priv->pos == 1 && rcar_i2c_dma(priv))
    496		return;
    497
    498	if (priv->pos < msg->len) {
    499		/*
    500		 * Prepare next data to ICRXTX register.
    501		 * This data will go to _SHIFT_ register.
    502		 *
    503		 *    *
    504		 * [ICRXTX] -> [SHIFT] -> [I2C bus]
    505		 */
    506		rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
    507		priv->pos++;
    508	} else {
    509		/*
    510		 * The last data was pushed to ICRXTX on _PREV_ empty irq.
    511		 * It is on _SHIFT_ register, and will sent to I2C bus.
    512		 *
    513		 *		  *
    514		 * [ICRXTX] -> [SHIFT] -> [I2C bus]
    515		 */
    516
    517		if (priv->flags & ID_LAST_MSG)
    518			/*
    519			 * If current msg is the _LAST_ msg,
    520			 * prepare stop condition here.
    521			 * ID_DONE will be set on STOP irq.
    522			 */
    523			rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
    524		else
    525			rcar_i2c_next_msg(priv);
    526	}
    527
    528	rcar_i2c_clear_irq(priv, irqs_to_clear);
    529}
    530
    531static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
    532{
    533	struct i2c_msg *msg = priv->msg;
    534	bool recv_len_init = priv->pos == 0 && msg->flags & I2C_M_RECV_LEN;
    535	u32 irqs_to_clear = MDR;
    536
    537	/* FIXME: sometimes, unknown interrupt happened. Do nothing */
    538	if (!(msr & MDR))
    539		return;
    540
    541	if (msr & MAT) {
    542		irqs_to_clear |= MAT;
    543		/*
    544		 * Address transfer phase finished, but no data at this point.
    545		 * Try to use DMA to receive data.
    546		 */
    547		rcar_i2c_dma(priv);
    548	} else if (priv->pos < msg->len) {
    549		/* get received data */
    550		u8 data = rcar_i2c_read(priv, ICRXTX);
    551
    552		msg->buf[priv->pos] = data;
    553		if (recv_len_init) {
    554			if (data == 0 || data > I2C_SMBUS_BLOCK_MAX) {
    555				priv->flags |= ID_DONE | ID_EPROTO;
    556				return;
    557			}
    558			msg->len += msg->buf[0];
    559			/* Enough data for DMA? */
    560			if (rcar_i2c_dma(priv))
    561				return;
    562			/* new length after RECV_LEN now properly initialized */
    563			recv_len_init = false;
    564		}
    565		priv->pos++;
    566	}
    567
    568	/*
    569	 * If next received data is the _LAST_ and we are not waiting for a new
    570	 * length because of RECV_LEN, then go to a new phase.
    571	 */
    572	if (priv->pos + 1 == msg->len && !recv_len_init) {
    573		if (priv->flags & ID_LAST_MSG) {
    574			rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
    575		} else {
    576			rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
    577			priv->flags |= ID_REP_AFTER_RD;
    578		}
    579	}
    580
    581	if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
    582		rcar_i2c_next_msg(priv);
    583
    584	rcar_i2c_clear_irq(priv, irqs_to_clear);
    585}
    586
    587static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
    588{
    589	u32 ssr_raw, ssr_filtered;
    590	u8 value;
    591
    592	ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
    593	ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
    594
    595	if (!ssr_filtered)
    596		return false;
    597
    598	/* address detected */
    599	if (ssr_filtered & SAR) {
    600		/* read or write request */
    601		if (ssr_raw & STM) {
    602			i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
    603			rcar_i2c_write(priv, ICRXTX, value);
    604			rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
    605		} else {
    606			i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
    607			rcar_i2c_read(priv, ICRXTX);	/* dummy read */
    608			rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
    609		}
    610
    611		/* Clear SSR, too, because of old STOPs to other clients than us */
    612		rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff);
    613	}
    614
    615	/* master sent stop */
    616	if (ssr_filtered & SSR) {
    617		i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
    618		rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */
    619		rcar_i2c_write(priv, ICSIER, SAR);
    620		rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
    621	}
    622
    623	/* master wants to write to us */
    624	if (ssr_filtered & SDR) {
    625		int ret;
    626
    627		value = rcar_i2c_read(priv, ICRXTX);
    628		ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
    629		/* Send NACK in case of error */
    630		rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
    631		rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
    632	}
    633
    634	/* master wants to read from us */
    635	if (ssr_filtered & SDE) {
    636		i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
    637		rcar_i2c_write(priv, ICRXTX, value);
    638		rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
    639	}
    640
    641	return true;
    642}
    643
    644/*
    645 * This driver has a lock-free design because there are IP cores (at least
    646 * R-Car Gen2) which have an inherent race condition in their hardware design.
    647 * There, we need to switch to RCAR_BUS_PHASE_DATA as soon as possible after
    648 * the interrupt was generated, otherwise an unwanted repeated message gets
    649 * generated. It turned out that taking a spinlock at the beginning of the ISR
    650 * was already causing repeated messages. Thus, this driver was converted to
    651 * the now lockless behaviour. Please keep this in mind when hacking the driver.
    652 * R-Car Gen3 seems to have this fixed but earlier versions than R-Car Gen2 are
    653 * likely affected. Therefore, we have different interrupt handler entries.
    654 */
    655static irqreturn_t rcar_i2c_irq(int irq, struct rcar_i2c_priv *priv, u32 msr)
    656{
    657	if (!msr) {
    658		if (rcar_i2c_slave_irq(priv))
    659			return IRQ_HANDLED;
    660
    661		return IRQ_NONE;
    662	}
    663
    664	/* Arbitration lost */
    665	if (msr & MAL) {
    666		priv->flags |= ID_DONE | ID_ARBLOST;
    667		goto out;
    668	}
    669
    670	/* Nack */
    671	if (msr & MNR) {
    672		/* HW automatically sends STOP after received NACK */
    673		if (priv->flags & ID_P_NOT_ATOMIC)
    674			rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
    675		priv->flags |= ID_NACK;
    676		goto out;
    677	}
    678
    679	/* Stop */
    680	if (msr & MST) {
    681		priv->msgs_left--; /* The last message also made it */
    682		priv->flags |= ID_DONE;
    683		goto out;
    684	}
    685
    686	if (rcar_i2c_is_recv(priv))
    687		rcar_i2c_irq_recv(priv, msr);
    688	else
    689		rcar_i2c_irq_send(priv, msr);
    690
    691out:
    692	if (priv->flags & ID_DONE) {
    693		rcar_i2c_write(priv, ICMIER, 0);
    694		rcar_i2c_write(priv, ICMSR, 0);
    695		if (priv->flags & ID_P_NOT_ATOMIC)
    696			wake_up(&priv->wait);
    697	}
    698
    699	return IRQ_HANDLED;
    700}
    701
    702static irqreturn_t rcar_i2c_gen2_irq(int irq, void *ptr)
    703{
    704	struct rcar_i2c_priv *priv = ptr;
    705	u32 msr;
    706
    707	/* Clear START or STOP immediately, except for REPSTART after read */
    708	if (likely(!(priv->flags & ID_REP_AFTER_RD)))
    709		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
    710
    711	/* Only handle interrupts that are currently enabled */
    712	msr = rcar_i2c_read(priv, ICMSR);
    713	if (priv->flags & ID_P_NOT_ATOMIC)
    714		msr &= rcar_i2c_read(priv, ICMIER);
    715
    716	return rcar_i2c_irq(irq, priv, msr);
    717}
    718
    719static irqreturn_t rcar_i2c_gen3_irq(int irq, void *ptr)
    720{
    721	struct rcar_i2c_priv *priv = ptr;
    722	u32 msr;
    723
    724	/* Only handle interrupts that are currently enabled */
    725	msr = rcar_i2c_read(priv, ICMSR);
    726	if (priv->flags & ID_P_NOT_ATOMIC)
    727		msr &= rcar_i2c_read(priv, ICMIER);
    728
    729	/*
    730	 * Clear START or STOP immediately, except for REPSTART after read or
    731	 * if a spurious interrupt was detected.
    732	 */
    733	if (likely(!(priv->flags & ID_REP_AFTER_RD) && msr))
    734		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
    735
    736	return rcar_i2c_irq(irq, priv, msr);
    737}
    738
    739static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev,
    740					enum dma_transfer_direction dir,
    741					dma_addr_t port_addr)
    742{
    743	struct dma_chan *chan;
    744	struct dma_slave_config cfg;
    745	char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
    746	int ret;
    747
    748	chan = dma_request_chan(dev, chan_name);
    749	if (IS_ERR(chan)) {
    750		dev_dbg(dev, "request_channel failed for %s (%ld)\n",
    751			chan_name, PTR_ERR(chan));
    752		return chan;
    753	}
    754
    755	memset(&cfg, 0, sizeof(cfg));
    756	cfg.direction = dir;
    757	if (dir == DMA_MEM_TO_DEV) {
    758		cfg.dst_addr = port_addr;
    759		cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
    760	} else {
    761		cfg.src_addr = port_addr;
    762		cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
    763	}
    764
    765	ret = dmaengine_slave_config(chan, &cfg);
    766	if (ret) {
    767		dev_dbg(dev, "slave_config failed for %s (%d)\n",
    768			chan_name, ret);
    769		dma_release_channel(chan);
    770		return ERR_PTR(ret);
    771	}
    772
    773	dev_dbg(dev, "got DMA channel for %s\n", chan_name);
    774	return chan;
    775}
    776
    777static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv,
    778				 struct i2c_msg *msg)
    779{
    780	struct device *dev = rcar_i2c_priv_to_dev(priv);
    781	bool read;
    782	struct dma_chan *chan;
    783	enum dma_transfer_direction dir;
    784
    785	read = msg->flags & I2C_M_RD;
    786
    787	chan = read ? priv->dma_rx : priv->dma_tx;
    788	if (PTR_ERR(chan) != -EPROBE_DEFER)
    789		return;
    790
    791	dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
    792	chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX);
    793
    794	if (read)
    795		priv->dma_rx = chan;
    796	else
    797		priv->dma_tx = chan;
    798}
    799
    800static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv)
    801{
    802	if (!IS_ERR(priv->dma_tx)) {
    803		dma_release_channel(priv->dma_tx);
    804		priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
    805	}
    806
    807	if (!IS_ERR(priv->dma_rx)) {
    808		dma_release_channel(priv->dma_rx);
    809		priv->dma_rx = ERR_PTR(-EPROBE_DEFER);
    810	}
    811}
    812
    813/* I2C is a special case, we need to poll the status of a reset */
    814static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv)
    815{
    816	int ret;
    817
    818	ret = reset_control_reset(priv->rstc);
    819	if (ret)
    820		return ret;
    821
    822	return read_poll_timeout_atomic(reset_control_status, ret, ret == 0, 1,
    823					100, false, priv->rstc);
    824}
    825
    826static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
    827				struct i2c_msg *msgs,
    828				int num)
    829{
    830	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
    831	struct device *dev = rcar_i2c_priv_to_dev(priv);
    832	int i, ret;
    833	long time_left;
    834
    835	priv->flags |= ID_P_NOT_ATOMIC;
    836
    837	pm_runtime_get_sync(dev);
    838
    839	/* Check bus state before init otherwise bus busy info will be lost */
    840	ret = rcar_i2c_bus_barrier(priv);
    841	if (ret < 0)
    842		goto out;
    843
    844	/* Gen3 needs a reset before allowing RXDMA once */
    845	if (priv->devtype == I2C_RCAR_GEN3) {
    846		priv->flags |= ID_P_NO_RXDMA;
    847		if (!IS_ERR(priv->rstc)) {
    848			ret = rcar_i2c_do_reset(priv);
    849			if (ret == 0)
    850				priv->flags &= ~ID_P_NO_RXDMA;
    851		}
    852	}
    853
    854	rcar_i2c_init(priv);
    855
    856	for (i = 0; i < num; i++)
    857		rcar_i2c_request_dma(priv, msgs + i);
    858
    859	rcar_i2c_first_msg(priv, msgs, num);
    860
    861	time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE,
    862				     num * adap->timeout);
    863
    864	/* cleanup DMA if it couldn't complete properly due to an error */
    865	if (priv->dma_direction != DMA_NONE)
    866		rcar_i2c_cleanup_dma(priv, true);
    867
    868	if (!time_left) {
    869		rcar_i2c_init(priv);
    870		ret = -ETIMEDOUT;
    871	} else if (priv->flags & ID_NACK) {
    872		ret = -ENXIO;
    873	} else if (priv->flags & ID_ARBLOST) {
    874		ret = -EAGAIN;
    875	} else if (priv->flags & ID_EPROTO) {
    876		ret = -EPROTO;
    877	} else {
    878		ret = num - priv->msgs_left; /* The number of transfer */
    879	}
    880out:
    881	pm_runtime_put(dev);
    882
    883	if (ret < 0 && ret != -ENXIO)
    884		dev_err(dev, "error %d : %x\n", ret, priv->flags);
    885
    886	return ret;
    887}
    888
    889static int rcar_i2c_master_xfer_atomic(struct i2c_adapter *adap,
    890				struct i2c_msg *msgs,
    891				int num)
    892{
    893	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
    894	struct device *dev = rcar_i2c_priv_to_dev(priv);
    895	unsigned long j;
    896	bool time_left;
    897	int ret;
    898
    899	priv->flags &= ~ID_P_NOT_ATOMIC;
    900
    901	pm_runtime_get_sync(dev);
    902
    903	/* Check bus state before init otherwise bus busy info will be lost */
    904	ret = rcar_i2c_bus_barrier(priv);
    905	if (ret < 0)
    906		goto out;
    907
    908	rcar_i2c_init(priv);
    909	rcar_i2c_first_msg(priv, msgs, num);
    910
    911	j = jiffies + num * adap->timeout;
    912	do {
    913		u32 msr = rcar_i2c_read(priv, ICMSR);
    914
    915		msr &= (rcar_i2c_is_recv(priv) ? RCAR_IRQ_RECV : RCAR_IRQ_SEND) | RCAR_IRQ_STOP;
    916
    917		if (msr) {
    918			if (priv->devtype < I2C_RCAR_GEN3)
    919				rcar_i2c_gen2_irq(0, priv);
    920			else
    921				rcar_i2c_gen3_irq(0, priv);
    922		}
    923
    924		time_left = time_before_eq(jiffies, j);
    925	} while (!(priv->flags & ID_DONE) && time_left);
    926
    927	if (!time_left) {
    928		rcar_i2c_init(priv);
    929		ret = -ETIMEDOUT;
    930	} else if (priv->flags & ID_NACK) {
    931		ret = -ENXIO;
    932	} else if (priv->flags & ID_ARBLOST) {
    933		ret = -EAGAIN;
    934	} else if (priv->flags & ID_EPROTO) {
    935		ret = -EPROTO;
    936	} else {
    937		ret = num - priv->msgs_left; /* The number of transfer */
    938	}
    939out:
    940	pm_runtime_put(dev);
    941
    942	if (ret < 0 && ret != -ENXIO)
    943		dev_err(dev, "error %d : %x\n", ret, priv->flags);
    944
    945	return ret;
    946}
    947
    948static int rcar_reg_slave(struct i2c_client *slave)
    949{
    950	struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
    951
    952	if (priv->slave)
    953		return -EBUSY;
    954
    955	if (slave->flags & I2C_CLIENT_TEN)
    956		return -EAFNOSUPPORT;
    957
    958	/* Keep device active for slave address detection logic */
    959	pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv));
    960
    961	priv->slave = slave;
    962	rcar_i2c_write(priv, ICSAR, slave->addr);
    963	rcar_i2c_write(priv, ICSSR, 0);
    964	rcar_i2c_write(priv, ICSIER, SAR);
    965	rcar_i2c_write(priv, ICSCR, SIE | SDBS);
    966
    967	return 0;
    968}
    969
    970static int rcar_unreg_slave(struct i2c_client *slave)
    971{
    972	struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
    973
    974	WARN_ON(!priv->slave);
    975
    976	/* ensure no irq is running before clearing ptr */
    977	disable_irq(priv->irq);
    978	rcar_i2c_write(priv, ICSIER, 0);
    979	rcar_i2c_write(priv, ICSSR, 0);
    980	enable_irq(priv->irq);
    981	rcar_i2c_write(priv, ICSCR, SDBS);
    982	rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */
    983
    984	priv->slave = NULL;
    985
    986	pm_runtime_put(rcar_i2c_priv_to_dev(priv));
    987
    988	return 0;
    989}
    990
    991static u32 rcar_i2c_func(struct i2c_adapter *adap)
    992{
    993	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
    994
    995	/*
    996	 * This HW can't do:
    997	 * I2C_SMBUS_QUICK (setting FSB during START didn't work)
    998	 * I2C_M_NOSTART (automatically sends address after START)
    999	 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK)
   1000	 */
   1001	u32 func = I2C_FUNC_I2C | I2C_FUNC_SLAVE |
   1002		   (I2C_FUNC_SMBUS_EMUL_ALL & ~I2C_FUNC_SMBUS_QUICK);
   1003
   1004	if (priv->flags & ID_P_HOST_NOTIFY)
   1005		func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
   1006
   1007	return func;
   1008}
   1009
   1010static const struct i2c_algorithm rcar_i2c_algo = {
   1011	.master_xfer	= rcar_i2c_master_xfer,
   1012	.master_xfer_atomic = rcar_i2c_master_xfer_atomic,
   1013	.functionality	= rcar_i2c_func,
   1014	.reg_slave	= rcar_reg_slave,
   1015	.unreg_slave	= rcar_unreg_slave,
   1016};
   1017
   1018static const struct i2c_adapter_quirks rcar_i2c_quirks = {
   1019	.flags = I2C_AQ_NO_ZERO_LEN,
   1020};
   1021
   1022static const struct of_device_id rcar_i2c_dt_ids[] = {
   1023	{ .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
   1024	{ .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
   1025	{ .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
   1026	{ .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
   1027	{ .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
   1028	{ .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
   1029	{ .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
   1030	{ .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
   1031	{ .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 },
   1032	{ .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 },
   1033	{ .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 },
   1034	{ .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 },
   1035	{ .compatible = "renesas,rcar-gen4-i2c", .data = (void *)I2C_RCAR_GEN3 },
   1036	{},
   1037};
   1038MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
   1039
   1040static int rcar_i2c_probe(struct platform_device *pdev)
   1041{
   1042	struct rcar_i2c_priv *priv;
   1043	struct i2c_adapter *adap;
   1044	struct device *dev = &pdev->dev;
   1045	unsigned long irqflags = 0;
   1046	irqreturn_t (*irqhandler)(int irq, void *ptr) = rcar_i2c_gen3_irq;
   1047	int ret;
   1048
   1049	/* Otherwise logic will break because some bytes must always use PIO */
   1050	BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length");
   1051
   1052	priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
   1053	if (!priv)
   1054		return -ENOMEM;
   1055
   1056	priv->clk = devm_clk_get(dev, NULL);
   1057	if (IS_ERR(priv->clk)) {
   1058		dev_err(dev, "cannot get clock\n");
   1059		return PTR_ERR(priv->clk);
   1060	}
   1061
   1062	priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res);
   1063	if (IS_ERR(priv->io))
   1064		return PTR_ERR(priv->io);
   1065
   1066	priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev);
   1067	init_waitqueue_head(&priv->wait);
   1068
   1069	adap = &priv->adap;
   1070	adap->nr = pdev->id;
   1071	adap->algo = &rcar_i2c_algo;
   1072	adap->class = I2C_CLASS_DEPRECATED;
   1073	adap->retries = 3;
   1074	adap->dev.parent = dev;
   1075	adap->dev.of_node = dev->of_node;
   1076	adap->bus_recovery_info = &rcar_i2c_bri;
   1077	adap->quirks = &rcar_i2c_quirks;
   1078	i2c_set_adapdata(adap, priv);
   1079	strlcpy(adap->name, pdev->name, sizeof(adap->name));
   1080
   1081	/* Init DMA */
   1082	sg_init_table(&priv->sg, 1);
   1083	priv->dma_direction = DMA_NONE;
   1084	priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
   1085
   1086	/* Activate device for clock calculation */
   1087	pm_runtime_enable(dev);
   1088	pm_runtime_get_sync(dev);
   1089	ret = rcar_i2c_clock_calculate(priv);
   1090	if (ret < 0) {
   1091		pm_runtime_put(dev);
   1092		goto out_pm_disable;
   1093	}
   1094
   1095	rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */
   1096
   1097	if (priv->devtype < I2C_RCAR_GEN3) {
   1098		irqflags |= IRQF_NO_THREAD;
   1099		irqhandler = rcar_i2c_gen2_irq;
   1100	}
   1101
   1102	if (priv->devtype == I2C_RCAR_GEN3) {
   1103		priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
   1104		if (!IS_ERR(priv->rstc)) {
   1105			ret = reset_control_status(priv->rstc);
   1106			if (ret < 0)
   1107				priv->rstc = ERR_PTR(-ENOTSUPP);
   1108		}
   1109	}
   1110
   1111	/* Stay always active when multi-master to keep arbitration working */
   1112	if (of_property_read_bool(dev->of_node, "multi-master"))
   1113		priv->flags |= ID_P_PM_BLOCKED;
   1114	else
   1115		pm_runtime_put(dev);
   1116
   1117	if (of_property_read_bool(dev->of_node, "smbus"))
   1118		priv->flags |= ID_P_HOST_NOTIFY;
   1119
   1120	ret = platform_get_irq(pdev, 0);
   1121	if (ret < 0)
   1122		goto out_pm_put;
   1123	priv->irq = ret;
   1124	ret = devm_request_irq(dev, priv->irq, irqhandler, irqflags, dev_name(dev), priv);
   1125	if (ret < 0) {
   1126		dev_err(dev, "cannot get irq %d\n", priv->irq);
   1127		goto out_pm_put;
   1128	}
   1129
   1130	platform_set_drvdata(pdev, priv);
   1131
   1132	ret = i2c_add_numbered_adapter(adap);
   1133	if (ret < 0)
   1134		goto out_pm_put;
   1135
   1136	if (priv->flags & ID_P_HOST_NOTIFY) {
   1137		priv->host_notify_client = i2c_new_slave_host_notify_device(adap);
   1138		if (IS_ERR(priv->host_notify_client)) {
   1139			ret = PTR_ERR(priv->host_notify_client);
   1140			goto out_del_device;
   1141		}
   1142	}
   1143
   1144	dev_info(dev, "probed\n");
   1145
   1146	return 0;
   1147
   1148 out_del_device:
   1149	i2c_del_adapter(&priv->adap);
   1150 out_pm_put:
   1151	if (priv->flags & ID_P_PM_BLOCKED)
   1152		pm_runtime_put(dev);
   1153 out_pm_disable:
   1154	pm_runtime_disable(dev);
   1155	return ret;
   1156}
   1157
   1158static int rcar_i2c_remove(struct platform_device *pdev)
   1159{
   1160	struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
   1161	struct device *dev = &pdev->dev;
   1162
   1163	if (priv->host_notify_client)
   1164		i2c_free_slave_host_notify_device(priv->host_notify_client);
   1165	i2c_del_adapter(&priv->adap);
   1166	rcar_i2c_release_dma(priv);
   1167	if (priv->flags & ID_P_PM_BLOCKED)
   1168		pm_runtime_put(dev);
   1169	pm_runtime_disable(dev);
   1170
   1171	return 0;
   1172}
   1173
   1174#ifdef CONFIG_PM_SLEEP
   1175static int rcar_i2c_suspend(struct device *dev)
   1176{
   1177	struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
   1178
   1179	i2c_mark_adapter_suspended(&priv->adap);
   1180	return 0;
   1181}
   1182
   1183static int rcar_i2c_resume(struct device *dev)
   1184{
   1185	struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
   1186
   1187	i2c_mark_adapter_resumed(&priv->adap);
   1188	return 0;
   1189}
   1190
   1191static const struct dev_pm_ops rcar_i2c_pm_ops = {
   1192	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume)
   1193};
   1194
   1195#define DEV_PM_OPS (&rcar_i2c_pm_ops)
   1196#else
   1197#define DEV_PM_OPS NULL
   1198#endif /* CONFIG_PM_SLEEP */
   1199
   1200static struct platform_driver rcar_i2c_driver = {
   1201	.driver	= {
   1202		.name	= "i2c-rcar",
   1203		.of_match_table = rcar_i2c_dt_ids,
   1204		.pm	= DEV_PM_OPS,
   1205	},
   1206	.probe		= rcar_i2c_probe,
   1207	.remove		= rcar_i2c_remove,
   1208};
   1209
   1210module_platform_driver(rcar_i2c_driver);
   1211
   1212MODULE_LICENSE("GPL v2");
   1213MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
   1214MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");