cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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i2c-sis96x.c (8066B)


      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3    Copyright (c) 2003 Mark M. Hoffman <mhoffman@lightlink.com>
      4
      5*/
      6
      7/*
      8    This module must be considered BETA unless and until
      9    the chipset manufacturer releases a datasheet.
     10    The register definitions are based on the SiS630.
     11
     12    This module relies on quirk_sis_96x_smbus (drivers/pci/quirks.c)
     13    for just about every machine for which users have reported.
     14    If this module isn't detecting your 96x south bridge, have a 
     15    look there.
     16
     17    We assume there can only be one SiS96x with one SMBus interface.
     18*/
     19
     20#include <linux/module.h>
     21#include <linux/pci.h>
     22#include <linux/kernel.h>
     23#include <linux/delay.h>
     24#include <linux/stddef.h>
     25#include <linux/ioport.h>
     26#include <linux/i2c.h>
     27#include <linux/acpi.h>
     28#include <linux/io.h>
     29
     30/* base address register in PCI config space */
     31#define SIS96x_BAR 0x04
     32
     33/* SiS96x SMBus registers */
     34#define SMB_STS      0x00
     35#define SMB_EN       0x01
     36#define SMB_CNT      0x02
     37#define SMB_HOST_CNT 0x03
     38#define SMB_ADDR     0x04
     39#define SMB_CMD      0x05
     40#define SMB_PCOUNT   0x06
     41#define SMB_COUNT    0x07
     42#define SMB_BYTE     0x08
     43#define SMB_DEV_ADDR 0x10
     44#define SMB_DB0      0x11
     45#define SMB_DB1      0x12
     46#define SMB_SAA      0x13
     47
     48/* register count for request_region */
     49#define SMB_IOSIZE 0x20
     50
     51/* Other settings */
     52#define MAX_TIMEOUT 500
     53
     54/* SiS96x SMBus constants */
     55#define SIS96x_QUICK      0x00
     56#define SIS96x_BYTE       0x01
     57#define SIS96x_BYTE_DATA  0x02
     58#define SIS96x_WORD_DATA  0x03
     59#define SIS96x_PROC_CALL  0x04
     60#define SIS96x_BLOCK_DATA 0x05
     61
     62static struct pci_driver sis96x_driver;
     63static struct i2c_adapter sis96x_adapter;
     64static u16 sis96x_smbus_base;
     65
     66static inline u8 sis96x_read(u8 reg)
     67{
     68	return inb(sis96x_smbus_base + reg) ;
     69}
     70
     71static inline void sis96x_write(u8 reg, u8 data)
     72{
     73	outb(data, sis96x_smbus_base + reg) ;
     74}
     75
     76/* Execute a SMBus transaction.
     77   int size is from SIS96x_QUICK to SIS96x_BLOCK_DATA
     78 */
     79static int sis96x_transaction(int size)
     80{
     81	int temp;
     82	int result = 0;
     83	int timeout = 0;
     84
     85	dev_dbg(&sis96x_adapter.dev, "SMBus transaction %d\n", size);
     86
     87	/* Make sure the SMBus host is ready to start transmitting */
     88	if (((temp = sis96x_read(SMB_CNT)) & 0x03) != 0x00) {
     89
     90		dev_dbg(&sis96x_adapter.dev, "SMBus busy (0x%02x). "
     91			"Resetting...\n", temp);
     92
     93		/* kill the transaction */
     94		sis96x_write(SMB_HOST_CNT, 0x20);
     95
     96		/* check it again */
     97		if (((temp = sis96x_read(SMB_CNT)) & 0x03) != 0x00) {
     98			dev_dbg(&sis96x_adapter.dev, "Failed (0x%02x)\n", temp);
     99			return -EBUSY;
    100		} else {
    101			dev_dbg(&sis96x_adapter.dev, "Successful\n");
    102		}
    103	}
    104
    105	/* Turn off timeout interrupts, set fast host clock */
    106	sis96x_write(SMB_CNT, 0x20);
    107
    108	/* clear all (sticky) status flags */
    109	temp = sis96x_read(SMB_STS);
    110	sis96x_write(SMB_STS, temp & 0x1e);
    111
    112	/* start the transaction by setting bit 4 and size bits */
    113	sis96x_write(SMB_HOST_CNT, 0x10 | (size & 0x07));
    114
    115	/* We will always wait for a fraction of a second! */
    116	do {
    117		msleep(1);
    118		temp = sis96x_read(SMB_STS);
    119	} while (!(temp & 0x0e) && (timeout++ < MAX_TIMEOUT));
    120
    121	/* If the SMBus is still busy, we give up */
    122	if (timeout > MAX_TIMEOUT) {
    123		dev_dbg(&sis96x_adapter.dev, "SMBus Timeout! (0x%02x)\n", temp);
    124		result = -ETIMEDOUT;
    125	}
    126
    127	/* device error - probably missing ACK */
    128	if (temp & 0x02) {
    129		dev_dbg(&sis96x_adapter.dev, "Failed bus transaction!\n");
    130		result = -ENXIO;
    131	}
    132
    133	/* bus collision */
    134	if (temp & 0x04) {
    135		dev_dbg(&sis96x_adapter.dev, "Bus collision!\n");
    136		result = -EIO;
    137	}
    138
    139	/* Finish up by resetting the bus */
    140	sis96x_write(SMB_STS, temp);
    141	if ((temp = sis96x_read(SMB_STS))) {
    142		dev_dbg(&sis96x_adapter.dev, "Failed reset at "
    143			"end of transaction! (0x%02x)\n", temp);
    144	}
    145
    146	return result;
    147}
    148
    149/* Return negative errno on error. */
    150static s32 sis96x_access(struct i2c_adapter * adap, u16 addr,
    151			 unsigned short flags, char read_write,
    152			 u8 command, int size, union i2c_smbus_data * data)
    153{
    154	int status;
    155
    156	switch (size) {
    157	case I2C_SMBUS_QUICK:
    158		sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
    159		size = SIS96x_QUICK;
    160		break;
    161
    162	case I2C_SMBUS_BYTE:
    163		sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
    164		if (read_write == I2C_SMBUS_WRITE)
    165			sis96x_write(SMB_CMD, command);
    166		size = SIS96x_BYTE;
    167		break;
    168
    169	case I2C_SMBUS_BYTE_DATA:
    170		sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
    171		sis96x_write(SMB_CMD, command);
    172		if (read_write == I2C_SMBUS_WRITE)
    173			sis96x_write(SMB_BYTE, data->byte);
    174		size = SIS96x_BYTE_DATA;
    175		break;
    176
    177	case I2C_SMBUS_PROC_CALL:
    178	case I2C_SMBUS_WORD_DATA:
    179		sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
    180		sis96x_write(SMB_CMD, command);
    181		if (read_write == I2C_SMBUS_WRITE) {
    182			sis96x_write(SMB_BYTE, data->word & 0xff);
    183			sis96x_write(SMB_BYTE + 1, (data->word & 0xff00) >> 8);
    184		}
    185		size = (size == I2C_SMBUS_PROC_CALL ? 
    186			SIS96x_PROC_CALL : SIS96x_WORD_DATA);
    187		break;
    188
    189	default:
    190		dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
    191		return -EOPNOTSUPP;
    192	}
    193
    194	status = sis96x_transaction(size);
    195	if (status)
    196		return status;
    197
    198	if ((size != SIS96x_PROC_CALL) &&
    199		((read_write == I2C_SMBUS_WRITE) || (size == SIS96x_QUICK)))
    200		return 0;
    201
    202	switch (size) {
    203	case SIS96x_BYTE:
    204	case SIS96x_BYTE_DATA:
    205		data->byte = sis96x_read(SMB_BYTE);
    206		break;
    207
    208	case SIS96x_WORD_DATA:
    209	case SIS96x_PROC_CALL:
    210		data->word = sis96x_read(SMB_BYTE) +
    211				(sis96x_read(SMB_BYTE + 1) << 8);
    212		break;
    213	}
    214	return 0;
    215}
    216
    217static u32 sis96x_func(struct i2c_adapter *adapter)
    218{
    219	return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
    220	    I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
    221	    I2C_FUNC_SMBUS_PROC_CALL;
    222}
    223
    224static const struct i2c_algorithm smbus_algorithm = {
    225	.smbus_xfer	= sis96x_access,
    226	.functionality	= sis96x_func,
    227};
    228
    229static struct i2c_adapter sis96x_adapter = {
    230	.owner		= THIS_MODULE,
    231	.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD,
    232	.algo		= &smbus_algorithm,
    233};
    234
    235static const struct pci_device_id sis96x_ids[] = {
    236	{ PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_SMBUS) },
    237	{ 0, }
    238};
    239
    240MODULE_DEVICE_TABLE (pci, sis96x_ids);
    241
    242static int sis96x_probe(struct pci_dev *dev,
    243				const struct pci_device_id *id)
    244{
    245	u16 ww = 0;
    246	int retval;
    247
    248	if (sis96x_smbus_base) {
    249		dev_err(&dev->dev, "Only one device supported.\n");
    250		return -EBUSY;
    251	}
    252
    253	pci_read_config_word(dev, PCI_CLASS_DEVICE, &ww);
    254	if (PCI_CLASS_SERIAL_SMBUS != ww) {
    255		dev_err(&dev->dev, "Unsupported device class 0x%04x!\n", ww);
    256		return -ENODEV;
    257	}
    258
    259	sis96x_smbus_base = pci_resource_start(dev, SIS96x_BAR);
    260	if (!sis96x_smbus_base) {
    261		dev_err(&dev->dev, "SiS96x SMBus base address "
    262			"not initialized!\n");
    263		return -EINVAL;
    264	}
    265	dev_info(&dev->dev, "SiS96x SMBus base address: 0x%04x\n",
    266			sis96x_smbus_base);
    267
    268	retval = acpi_check_resource_conflict(&dev->resource[SIS96x_BAR]);
    269	if (retval)
    270		return -ENODEV;
    271
    272	/* Everything is happy, let's grab the memory and set things up. */
    273	if (!request_region(sis96x_smbus_base, SMB_IOSIZE,
    274			    sis96x_driver.name)) {
    275		dev_err(&dev->dev, "SMBus registers 0x%04x-0x%04x "
    276			"already in use!\n", sis96x_smbus_base,
    277			sis96x_smbus_base + SMB_IOSIZE - 1);
    278
    279		sis96x_smbus_base = 0;
    280		return -EINVAL;
    281	}
    282
    283	/* set up the sysfs linkage to our parent device */
    284	sis96x_adapter.dev.parent = &dev->dev;
    285
    286	snprintf(sis96x_adapter.name, sizeof(sis96x_adapter.name),
    287		"SiS96x SMBus adapter at 0x%04x", sis96x_smbus_base);
    288
    289	if ((retval = i2c_add_adapter(&sis96x_adapter))) {
    290		dev_err(&dev->dev, "Couldn't register adapter!\n");
    291		release_region(sis96x_smbus_base, SMB_IOSIZE);
    292		sis96x_smbus_base = 0;
    293	}
    294
    295	return retval;
    296}
    297
    298static void sis96x_remove(struct pci_dev *dev)
    299{
    300	if (sis96x_smbus_base) {
    301		i2c_del_adapter(&sis96x_adapter);
    302		release_region(sis96x_smbus_base, SMB_IOSIZE);
    303		sis96x_smbus_base = 0;
    304	}
    305}
    306
    307static struct pci_driver sis96x_driver = {
    308	.name		= "sis96x_smbus",
    309	.id_table	= sis96x_ids,
    310	.probe		= sis96x_probe,
    311	.remove		= sis96x_remove,
    312};
    313
    314module_pci_driver(sis96x_driver);
    315
    316MODULE_AUTHOR("Mark M. Hoffman <mhoffman@lightlink.com>");
    317MODULE_DESCRIPTION("SiS96x SMBus driver");
    318MODULE_LICENSE("GPL");