cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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i2c-sun6i-p2wi.c (8715B)


      1/*
      2 * P2WI (Push-Pull Two Wire Interface) bus driver.
      3 *
      4 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
      5 *
      6 * This file is licensed under the terms of the GNU General Public License
      7 * version 2.  This program is licensed "as is" without any warranty of any
      8 * kind, whether express or implied.
      9 *
     10 * The P2WI controller looks like an SMBus controller which only supports byte
     11 * data transfers. But, it differs from standard SMBus protocol on several
     12 * aspects:
     13 * - it supports only one slave device, and thus drop the address field
     14 * - it adds a parity bit every 8bits of data
     15 * - only one read access is required to read a byte (instead of a write
     16 *   followed by a read access in standard SMBus protocol)
     17 * - there's no Ack bit after each byte transfer
     18 *
     19 * This means this bus cannot be used to interface with standard SMBus
     20 * devices (the only known device to support this interface is the AXP221
     21 * PMIC).
     22 *
     23 */
     24#include <linux/clk.h>
     25#include <linux/i2c.h>
     26#include <linux/io.h>
     27#include <linux/interrupt.h>
     28#include <linux/module.h>
     29#include <linux/of.h>
     30#include <linux/platform_device.h>
     31#include <linux/reset.h>
     32
     33
     34/* P2WI registers */
     35#define P2WI_CTRL		0x0
     36#define P2WI_CCR		0x4
     37#define P2WI_INTE		0x8
     38#define P2WI_INTS		0xc
     39#define P2WI_DADDR0		0x10
     40#define P2WI_DADDR1		0x14
     41#define P2WI_DLEN		0x18
     42#define P2WI_DATA0		0x1c
     43#define P2WI_DATA1		0x20
     44#define P2WI_LCR		0x24
     45#define P2WI_PMCR		0x28
     46
     47/* CTRL fields */
     48#define P2WI_CTRL_START_TRANS		BIT(7)
     49#define P2WI_CTRL_ABORT_TRANS		BIT(6)
     50#define P2WI_CTRL_GLOBAL_INT_ENB	BIT(1)
     51#define P2WI_CTRL_SOFT_RST		BIT(0)
     52
     53/* CLK CTRL fields */
     54#define P2WI_CCR_SDA_OUT_DELAY(v)	(((v) & 0x7) << 8)
     55#define P2WI_CCR_MAX_CLK_DIV		0xff
     56#define P2WI_CCR_CLK_DIV(v)		((v) & P2WI_CCR_MAX_CLK_DIV)
     57
     58/* STATUS fields */
     59#define P2WI_INTS_TRANS_ERR_ID(v)	(((v) >> 8) & 0xff)
     60#define P2WI_INTS_LOAD_BSY		BIT(2)
     61#define P2WI_INTS_TRANS_ERR		BIT(1)
     62#define P2WI_INTS_TRANS_OVER		BIT(0)
     63
     64/* DATA LENGTH fields*/
     65#define P2WI_DLEN_READ			BIT(4)
     66#define P2WI_DLEN_DATA_LENGTH(v)	((v - 1) & 0x7)
     67
     68/* LINE CTRL fields*/
     69#define P2WI_LCR_SCL_STATE		BIT(5)
     70#define P2WI_LCR_SDA_STATE		BIT(4)
     71#define P2WI_LCR_SCL_CTL		BIT(3)
     72#define P2WI_LCR_SCL_CTL_EN		BIT(2)
     73#define P2WI_LCR_SDA_CTL		BIT(1)
     74#define P2WI_LCR_SDA_CTL_EN		BIT(0)
     75
     76/* PMU MODE CTRL fields */
     77#define P2WI_PMCR_PMU_INIT_SEND		BIT(31)
     78#define P2WI_PMCR_PMU_INIT_DATA(v)	(((v) & 0xff) << 16)
     79#define P2WI_PMCR_PMU_MODE_REG(v)	(((v) & 0xff) << 8)
     80#define P2WI_PMCR_PMU_DEV_ADDR(v)	((v) & 0xff)
     81
     82#define P2WI_MAX_FREQ			6000000
     83
     84struct p2wi {
     85	struct i2c_adapter adapter;
     86	struct completion complete;
     87	unsigned int status;
     88	void __iomem *regs;
     89	struct clk *clk;
     90	struct reset_control *rstc;
     91	int slave_addr;
     92};
     93
     94static irqreturn_t p2wi_interrupt(int irq, void *dev_id)
     95{
     96	struct p2wi *p2wi = dev_id;
     97	unsigned long status;
     98
     99	status = readl(p2wi->regs + P2WI_INTS);
    100	p2wi->status = status;
    101
    102	/* Clear interrupts */
    103	status &= (P2WI_INTS_LOAD_BSY | P2WI_INTS_TRANS_ERR |
    104		   P2WI_INTS_TRANS_OVER);
    105	writel(status, p2wi->regs + P2WI_INTS);
    106
    107	complete(&p2wi->complete);
    108
    109	return IRQ_HANDLED;
    110}
    111
    112static u32 p2wi_functionality(struct i2c_adapter *adap)
    113{
    114	return I2C_FUNC_SMBUS_BYTE_DATA;
    115}
    116
    117static int p2wi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
    118			   unsigned short flags, char read_write,
    119			   u8 command, int size, union i2c_smbus_data *data)
    120{
    121	struct p2wi *p2wi = i2c_get_adapdata(adap);
    122	unsigned long dlen = P2WI_DLEN_DATA_LENGTH(1);
    123
    124	if (p2wi->slave_addr >= 0 && addr != p2wi->slave_addr) {
    125		dev_err(&adap->dev, "invalid P2WI address\n");
    126		return -EINVAL;
    127	}
    128
    129	if (!data)
    130		return -EINVAL;
    131
    132	writel(command, p2wi->regs + P2WI_DADDR0);
    133
    134	if (read_write == I2C_SMBUS_READ)
    135		dlen |= P2WI_DLEN_READ;
    136	else
    137		writel(data->byte, p2wi->regs + P2WI_DATA0);
    138
    139	writel(dlen, p2wi->regs + P2WI_DLEN);
    140
    141	if (readl(p2wi->regs + P2WI_CTRL) & P2WI_CTRL_START_TRANS) {
    142		dev_err(&adap->dev, "P2WI bus busy\n");
    143		return -EBUSY;
    144	}
    145
    146	reinit_completion(&p2wi->complete);
    147
    148	writel(P2WI_INTS_LOAD_BSY | P2WI_INTS_TRANS_ERR | P2WI_INTS_TRANS_OVER,
    149	       p2wi->regs + P2WI_INTE);
    150
    151	writel(P2WI_CTRL_START_TRANS | P2WI_CTRL_GLOBAL_INT_ENB,
    152	       p2wi->regs + P2WI_CTRL);
    153
    154	wait_for_completion(&p2wi->complete);
    155
    156	if (p2wi->status & P2WI_INTS_LOAD_BSY) {
    157		dev_err(&adap->dev, "P2WI bus busy\n");
    158		return -EBUSY;
    159	}
    160
    161	if (p2wi->status & P2WI_INTS_TRANS_ERR) {
    162		dev_err(&adap->dev, "P2WI bus xfer error\n");
    163		return -ENXIO;
    164	}
    165
    166	if (read_write == I2C_SMBUS_READ)
    167		data->byte = readl(p2wi->regs + P2WI_DATA0);
    168
    169	return 0;
    170}
    171
    172static const struct i2c_algorithm p2wi_algo = {
    173	.smbus_xfer = p2wi_smbus_xfer,
    174	.functionality = p2wi_functionality,
    175};
    176
    177static const struct of_device_id p2wi_of_match_table[] = {
    178	{ .compatible = "allwinner,sun6i-a31-p2wi" },
    179	{}
    180};
    181MODULE_DEVICE_TABLE(of, p2wi_of_match_table);
    182
    183static int p2wi_probe(struct platform_device *pdev)
    184{
    185	struct device *dev = &pdev->dev;
    186	struct device_node *np = dev->of_node;
    187	struct device_node *childnp;
    188	unsigned long parent_clk_freq;
    189	u32 clk_freq = I2C_MAX_STANDARD_MODE_FREQ;
    190	struct p2wi *p2wi;
    191	u32 slave_addr;
    192	int clk_div;
    193	int irq;
    194	int ret;
    195
    196	of_property_read_u32(np, "clock-frequency", &clk_freq);
    197	if (clk_freq > P2WI_MAX_FREQ) {
    198		dev_err(dev,
    199			"required clock-frequency (%u Hz) is too high (max = 6MHz)",
    200			clk_freq);
    201		return -EINVAL;
    202	}
    203
    204	if (of_get_child_count(np) > 1) {
    205		dev_err(dev, "P2WI only supports one slave device\n");
    206		return -EINVAL;
    207	}
    208
    209	p2wi = devm_kzalloc(dev, sizeof(struct p2wi), GFP_KERNEL);
    210	if (!p2wi)
    211		return -ENOMEM;
    212
    213	p2wi->slave_addr = -1;
    214
    215	/*
    216	 * Authorize a p2wi node without any children to be able to use an
    217	 * i2c-dev from userpace.
    218	 * In this case the slave_addr is set to -1 and won't be checked when
    219	 * launching a P2WI transfer.
    220	 */
    221	childnp = of_get_next_available_child(np, NULL);
    222	if (childnp) {
    223		ret = of_property_read_u32(childnp, "reg", &slave_addr);
    224		if (ret) {
    225			dev_err(dev, "invalid slave address on node %pOF\n",
    226				childnp);
    227			return -EINVAL;
    228		}
    229
    230		p2wi->slave_addr = slave_addr;
    231	}
    232
    233	p2wi->regs = devm_platform_ioremap_resource(pdev, 0);
    234	if (IS_ERR(p2wi->regs))
    235		return PTR_ERR(p2wi->regs);
    236
    237	strscpy(p2wi->adapter.name, pdev->name, sizeof(p2wi->adapter.name));
    238	irq = platform_get_irq(pdev, 0);
    239	if (irq < 0)
    240		return irq;
    241
    242	p2wi->clk = devm_clk_get(dev, NULL);
    243	if (IS_ERR(p2wi->clk)) {
    244		ret = PTR_ERR(p2wi->clk);
    245		dev_err(dev, "failed to retrieve clk: %d\n", ret);
    246		return ret;
    247	}
    248
    249	ret = clk_prepare_enable(p2wi->clk);
    250	if (ret) {
    251		dev_err(dev, "failed to enable clk: %d\n", ret);
    252		return ret;
    253	}
    254
    255	parent_clk_freq = clk_get_rate(p2wi->clk);
    256
    257	p2wi->rstc = devm_reset_control_get_exclusive(dev, NULL);
    258	if (IS_ERR(p2wi->rstc)) {
    259		ret = PTR_ERR(p2wi->rstc);
    260		dev_err(dev, "failed to retrieve reset controller: %d\n", ret);
    261		goto err_clk_disable;
    262	}
    263
    264	ret = reset_control_deassert(p2wi->rstc);
    265	if (ret) {
    266		dev_err(dev, "failed to deassert reset line: %d\n", ret);
    267		goto err_clk_disable;
    268	}
    269
    270	init_completion(&p2wi->complete);
    271	p2wi->adapter.dev.parent = dev;
    272	p2wi->adapter.algo = &p2wi_algo;
    273	p2wi->adapter.owner = THIS_MODULE;
    274	p2wi->adapter.dev.of_node = pdev->dev.of_node;
    275	platform_set_drvdata(pdev, p2wi);
    276	i2c_set_adapdata(&p2wi->adapter, p2wi);
    277
    278	ret = devm_request_irq(dev, irq, p2wi_interrupt, 0, pdev->name, p2wi);
    279	if (ret) {
    280		dev_err(dev, "can't register interrupt handler irq%d: %d\n",
    281			irq, ret);
    282		goto err_reset_assert;
    283	}
    284
    285	writel(P2WI_CTRL_SOFT_RST, p2wi->regs + P2WI_CTRL);
    286
    287	clk_div = parent_clk_freq / clk_freq;
    288	if (!clk_div) {
    289		dev_warn(dev,
    290			 "clock-frequency is too high, setting it to %lu Hz\n",
    291			 parent_clk_freq);
    292		clk_div = 1;
    293	} else if (clk_div > P2WI_CCR_MAX_CLK_DIV) {
    294		dev_warn(dev,
    295			 "clock-frequency is too low, setting it to %lu Hz\n",
    296			 parent_clk_freq / P2WI_CCR_MAX_CLK_DIV);
    297		clk_div = P2WI_CCR_MAX_CLK_DIV;
    298	}
    299
    300	writel(P2WI_CCR_SDA_OUT_DELAY(1) | P2WI_CCR_CLK_DIV(clk_div),
    301	       p2wi->regs + P2WI_CCR);
    302
    303	ret = i2c_add_adapter(&p2wi->adapter);
    304	if (!ret)
    305		return 0;
    306
    307err_reset_assert:
    308	reset_control_assert(p2wi->rstc);
    309
    310err_clk_disable:
    311	clk_disable_unprepare(p2wi->clk);
    312
    313	return ret;
    314}
    315
    316static int p2wi_remove(struct platform_device *dev)
    317{
    318	struct p2wi *p2wi = platform_get_drvdata(dev);
    319
    320	reset_control_assert(p2wi->rstc);
    321	clk_disable_unprepare(p2wi->clk);
    322	i2c_del_adapter(&p2wi->adapter);
    323
    324	return 0;
    325}
    326
    327static struct platform_driver p2wi_driver = {
    328	.probe	= p2wi_probe,
    329	.remove	= p2wi_remove,
    330	.driver	= {
    331		.name = "i2c-sunxi-p2wi",
    332		.of_match_table = p2wi_of_match_table,
    333	},
    334};
    335module_platform_driver(p2wi_driver);
    336
    337MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
    338MODULE_DESCRIPTION("Allwinner P2WI driver");
    339MODULE_LICENSE("GPL v2");