cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

cmd.h (1896B)

      1/* SPDX-License-Identifier: BSD-3-Clause */
      2/*
      3 * Copyright (c) 2020, MIPI Alliance, Inc.
      4 *
      5 * Author: Nicolas Pitre <npitre@baylibre.com>
      6 *
      7 * Common command/response related stuff
      8 */
      9
     10#ifndef CMD_H
     11#define CMD_H
     12
     13/*
     14 * Those bits are common to all descriptor formats and
     15 * may be manipulated by the core code.
     16 */
     17#define CMD_0_TOC			W0_BIT_(31)
     18#define CMD_0_ROC			W0_BIT_(30)
     19#define CMD_0_ATTR			W0_MASK(2, 0)
     20
     21/*
     22 * Response Descriptor Structure
     23 */
     24#define RESP_STATUS(resp)		FIELD_GET(GENMASK(31, 28), resp)
     25#define RESP_TID(resp)			FIELD_GET(GENMASK(27, 24), resp)
     26#define RESP_DATA_LENGTH(resp)		FIELD_GET(GENMASK(21,  0), resp)
     27
     28#define RESP_ERR_FIELD			GENMASK(31, 28)
     29
     30enum hci_resp_err {
     31	RESP_SUCCESS			= 0x0,
     32	RESP_ERR_CRC			= 0x1,
     33	RESP_ERR_PARITY			= 0x2,
     34	RESP_ERR_FRAME			= 0x3,
     35	RESP_ERR_ADDR_HEADER		= 0x4,
     36	RESP_ERR_BCAST_NACK_7E		= 0x4,
     37	RESP_ERR_NACK			= 0x5,
     38	RESP_ERR_OVL			= 0x6,
     39	RESP_ERR_I3C_SHORT_READ		= 0x7,
     40	RESP_ERR_HC_TERMINATED		= 0x8,
     41	RESP_ERR_I2C_WR_DATA_NACK	= 0x9,
     42	RESP_ERR_BUS_XFER_ABORTED	= 0x9,
     43	RESP_ERR_NOT_SUPPORTED		= 0xa,
     44	RESP_ERR_ABORTED_WITH_CRC	= 0xb,
     45	/* 0xc to 0xf are reserved for transfer specific errors */
     46};
     47
     48/* TID generation (4 bits wide in all cases) */
     49#define hci_get_tid(bits) \
     50	(atomic_inc_return_relaxed(&hci->next_cmd_tid) % (1U << 4))
     51
     52/* This abstracts operations with our command descriptor formats */
     53struct hci_cmd_ops {
     54	int (*prep_ccc)(struct i3c_hci *hci, struct hci_xfer *xfer,
     55			u8 ccc_addr, u8 ccc_cmd, bool raw);
     56	void (*prep_i3c_xfer)(struct i3c_hci *hci, struct i3c_dev_desc *dev,
     57			      struct hci_xfer *xfer);
     58	void (*prep_i2c_xfer)(struct i3c_hci *hci, struct i2c_dev_desc *dev,
     59			      struct hci_xfer *xfer);
     60	int (*perform_daa)(struct i3c_hci *hci);
     61};
     62
     63/* Our various instances */
     64extern const struct hci_cmd_ops mipi_i3c_hci_cmd_v1;
     65extern const struct hci_cmd_ops mipi_i3c_hci_cmd_v2;
     66
     67#endif