cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ad7298.c (8893B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * AD7298 SPI ADC driver
      4 *
      5 * Copyright 2011 Analog Devices Inc.
      6 */
      7
      8#include <linux/device.h>
      9#include <linux/kernel.h>
     10#include <linux/slab.h>
     11#include <linux/sysfs.h>
     12#include <linux/spi/spi.h>
     13#include <linux/regulator/consumer.h>
     14#include <linux/err.h>
     15#include <linux/delay.h>
     16#include <linux/mod_devicetable.h>
     17#include <linux/module.h>
     18#include <linux/interrupt.h>
     19#include <linux/bitops.h>
     20
     21#include <linux/iio/iio.h>
     22#include <linux/iio/sysfs.h>
     23#include <linux/iio/buffer.h>
     24#include <linux/iio/trigger_consumer.h>
     25#include <linux/iio/triggered_buffer.h>
     26
     27#define AD7298_WRITE	BIT(15) /* write to the control register */
     28#define AD7298_REPEAT	BIT(14) /* repeated conversion enable */
     29#define AD7298_CH(x)	BIT(13 - (x)) /* channel select */
     30#define AD7298_TSENSE	BIT(5) /* temperature conversion enable */
     31#define AD7298_EXTREF	BIT(2) /* external reference enable */
     32#define AD7298_TAVG	BIT(1) /* temperature sensor averaging enable */
     33#define AD7298_PDD	BIT(0) /* partial power down enable */
     34
     35#define AD7298_MAX_CHAN		8
     36#define AD7298_INTREF_mV	2500
     37
     38#define AD7298_CH_TEMP		9
     39
     40struct ad7298_state {
     41	struct spi_device		*spi;
     42	struct regulator		*reg;
     43	unsigned			ext_ref;
     44	struct spi_transfer		ring_xfer[10];
     45	struct spi_transfer		scan_single_xfer[3];
     46	struct spi_message		ring_msg;
     47	struct spi_message		scan_single_msg;
     48	/*
     49	 * DMA (thus cache coherency maintenance) requires the
     50	 * transfer buffers to live in their own cache lines.
     51	 */
     52	__be16				rx_buf[12] ____cacheline_aligned;
     53	__be16				tx_buf[2];
     54};
     55
     56#define AD7298_V_CHAN(index)						\
     57	{								\
     58		.type = IIO_VOLTAGE,					\
     59		.indexed = 1,						\
     60		.channel = index,					\
     61		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
     62		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
     63		.address = index,					\
     64		.scan_index = index,					\
     65		.scan_type = {						\
     66			.sign = 'u',					\
     67			.realbits = 12,					\
     68			.storagebits = 16,				\
     69			.endianness = IIO_BE,				\
     70		},							\
     71	}
     72
     73static const struct iio_chan_spec ad7298_channels[] = {
     74	{
     75		.type = IIO_TEMP,
     76		.indexed = 1,
     77		.channel = 0,
     78		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
     79			BIT(IIO_CHAN_INFO_SCALE) |
     80			BIT(IIO_CHAN_INFO_OFFSET),
     81		.address = AD7298_CH_TEMP,
     82		.scan_index = -1,
     83		.scan_type = {
     84			.sign = 's',
     85			.realbits = 32,
     86			.storagebits = 32,
     87		},
     88	},
     89	AD7298_V_CHAN(0),
     90	AD7298_V_CHAN(1),
     91	AD7298_V_CHAN(2),
     92	AD7298_V_CHAN(3),
     93	AD7298_V_CHAN(4),
     94	AD7298_V_CHAN(5),
     95	AD7298_V_CHAN(6),
     96	AD7298_V_CHAN(7),
     97	IIO_CHAN_SOFT_TIMESTAMP(8),
     98};
     99
    100/*
    101 * ad7298_update_scan_mode() setup the spi transfer buffer for the new scan mask
    102 */
    103static int ad7298_update_scan_mode(struct iio_dev *indio_dev,
    104	const unsigned long *active_scan_mask)
    105{
    106	struct ad7298_state *st = iio_priv(indio_dev);
    107	int i, m;
    108	unsigned short command;
    109	int scan_count;
    110
    111	/* Now compute overall size */
    112	scan_count = bitmap_weight(active_scan_mask, indio_dev->masklength);
    113
    114	command = AD7298_WRITE | st->ext_ref;
    115
    116	for (i = 0, m = AD7298_CH(0); i < AD7298_MAX_CHAN; i++, m >>= 1)
    117		if (test_bit(i, active_scan_mask))
    118			command |= m;
    119
    120	st->tx_buf[0] = cpu_to_be16(command);
    121
    122	/* build spi ring message */
    123	st->ring_xfer[0].tx_buf = &st->tx_buf[0];
    124	st->ring_xfer[0].len = 2;
    125	st->ring_xfer[0].cs_change = 1;
    126	st->ring_xfer[1].tx_buf = &st->tx_buf[1];
    127	st->ring_xfer[1].len = 2;
    128	st->ring_xfer[1].cs_change = 1;
    129
    130	spi_message_init(&st->ring_msg);
    131	spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
    132	spi_message_add_tail(&st->ring_xfer[1], &st->ring_msg);
    133
    134	for (i = 0; i < scan_count; i++) {
    135		st->ring_xfer[i + 2].rx_buf = &st->rx_buf[i];
    136		st->ring_xfer[i + 2].len = 2;
    137		st->ring_xfer[i + 2].cs_change = 1;
    138		spi_message_add_tail(&st->ring_xfer[i + 2], &st->ring_msg);
    139	}
    140	/* make sure last transfer cs_change is not set */
    141	st->ring_xfer[i + 1].cs_change = 0;
    142
    143	return 0;
    144}
    145
    146static irqreturn_t ad7298_trigger_handler(int irq, void *p)
    147{
    148	struct iio_poll_func *pf = p;
    149	struct iio_dev *indio_dev = pf->indio_dev;
    150	struct ad7298_state *st = iio_priv(indio_dev);
    151	int b_sent;
    152
    153	b_sent = spi_sync(st->spi, &st->ring_msg);
    154	if (b_sent)
    155		goto done;
    156
    157	iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
    158		iio_get_time_ns(indio_dev));
    159
    160done:
    161	iio_trigger_notify_done(indio_dev->trig);
    162
    163	return IRQ_HANDLED;
    164}
    165
    166static int ad7298_scan_direct(struct ad7298_state *st, unsigned ch)
    167{
    168	int ret;
    169	st->tx_buf[0] = cpu_to_be16(AD7298_WRITE | st->ext_ref |
    170				   (AD7298_CH(0) >> ch));
    171
    172	ret = spi_sync(st->spi, &st->scan_single_msg);
    173	if (ret)
    174		return ret;
    175
    176	return be16_to_cpu(st->rx_buf[0]);
    177}
    178
    179static int ad7298_scan_temp(struct ad7298_state *st, int *val)
    180{
    181	int ret;
    182	__be16 buf;
    183
    184	buf = cpu_to_be16(AD7298_WRITE | AD7298_TSENSE |
    185			  AD7298_TAVG | st->ext_ref);
    186
    187	ret = spi_write(st->spi, (u8 *)&buf, 2);
    188	if (ret)
    189		return ret;
    190
    191	buf = cpu_to_be16(0);
    192
    193	ret = spi_write(st->spi, (u8 *)&buf, 2);
    194	if (ret)
    195		return ret;
    196
    197	usleep_range(101, 1000); /* sleep > 100us */
    198
    199	ret = spi_read(st->spi, (u8 *)&buf, 2);
    200	if (ret)
    201		return ret;
    202
    203	*val = sign_extend32(be16_to_cpu(buf), 11);
    204
    205	return 0;
    206}
    207
    208static int ad7298_get_ref_voltage(struct ad7298_state *st)
    209{
    210	int vref;
    211
    212	if (st->reg) {
    213		vref = regulator_get_voltage(st->reg);
    214		if (vref < 0)
    215			return vref;
    216
    217		return vref / 1000;
    218	} else {
    219		return AD7298_INTREF_mV;
    220	}
    221}
    222
    223static int ad7298_read_raw(struct iio_dev *indio_dev,
    224			   struct iio_chan_spec const *chan,
    225			   int *val,
    226			   int *val2,
    227			   long m)
    228{
    229	int ret;
    230	struct ad7298_state *st = iio_priv(indio_dev);
    231
    232	switch (m) {
    233	case IIO_CHAN_INFO_RAW:
    234		ret = iio_device_claim_direct_mode(indio_dev);
    235		if (ret)
    236			return ret;
    237
    238		if (chan->address == AD7298_CH_TEMP)
    239			ret = ad7298_scan_temp(st, val);
    240		else
    241			ret = ad7298_scan_direct(st, chan->address);
    242
    243		iio_device_release_direct_mode(indio_dev);
    244
    245		if (ret < 0)
    246			return ret;
    247
    248		if (chan->address != AD7298_CH_TEMP)
    249			*val = ret & GENMASK(chan->scan_type.realbits - 1, 0);
    250
    251		return IIO_VAL_INT;
    252	case IIO_CHAN_INFO_SCALE:
    253		switch (chan->type) {
    254		case IIO_VOLTAGE:
    255			*val = ad7298_get_ref_voltage(st);
    256			*val2 = chan->scan_type.realbits;
    257			return IIO_VAL_FRACTIONAL_LOG2;
    258		case IIO_TEMP:
    259			*val = ad7298_get_ref_voltage(st);
    260			*val2 = 10;
    261			return IIO_VAL_FRACTIONAL;
    262		default:
    263			return -EINVAL;
    264		}
    265	case IIO_CHAN_INFO_OFFSET:
    266		*val = 1093 - 2732500 / ad7298_get_ref_voltage(st);
    267		return IIO_VAL_INT;
    268	}
    269	return -EINVAL;
    270}
    271
    272static const struct iio_info ad7298_info = {
    273	.read_raw = &ad7298_read_raw,
    274	.update_scan_mode = ad7298_update_scan_mode,
    275};
    276
    277static void ad7298_reg_disable(void *data)
    278{
    279	struct regulator *reg = data;
    280
    281	regulator_disable(reg);
    282}
    283
    284static int ad7298_probe(struct spi_device *spi)
    285{
    286	struct ad7298_state *st;
    287	struct iio_dev *indio_dev;
    288	int ret;
    289
    290	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
    291	if (indio_dev == NULL)
    292		return -ENOMEM;
    293
    294	st = iio_priv(indio_dev);
    295
    296	st->reg = devm_regulator_get_optional(&spi->dev, "vref");
    297	if (!IS_ERR(st->reg)) {
    298		st->ext_ref = AD7298_EXTREF;
    299	} else {
    300		ret = PTR_ERR(st->reg);
    301		if (ret != -ENODEV)
    302			return ret;
    303
    304		st->reg = NULL;
    305	}
    306
    307	if (st->reg) {
    308		ret = regulator_enable(st->reg);
    309		if (ret)
    310			return ret;
    311
    312		ret = devm_add_action_or_reset(&spi->dev, ad7298_reg_disable,
    313					       st->reg);
    314		if (ret)
    315			return ret;
    316	}
    317
    318	st->spi = spi;
    319
    320	indio_dev->name = spi_get_device_id(spi)->name;
    321	indio_dev->modes = INDIO_DIRECT_MODE;
    322	indio_dev->channels = ad7298_channels;
    323	indio_dev->num_channels = ARRAY_SIZE(ad7298_channels);
    324	indio_dev->info = &ad7298_info;
    325
    326	/* Setup default message */
    327
    328	st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
    329	st->scan_single_xfer[0].len = 2;
    330	st->scan_single_xfer[0].cs_change = 1;
    331	st->scan_single_xfer[1].tx_buf = &st->tx_buf[1];
    332	st->scan_single_xfer[1].len = 2;
    333	st->scan_single_xfer[1].cs_change = 1;
    334	st->scan_single_xfer[2].rx_buf = &st->rx_buf[0];
    335	st->scan_single_xfer[2].len = 2;
    336
    337	spi_message_init(&st->scan_single_msg);
    338	spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
    339	spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
    340	spi_message_add_tail(&st->scan_single_xfer[2], &st->scan_single_msg);
    341
    342	ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
    343			&ad7298_trigger_handler, NULL);
    344	if (ret)
    345		return ret;
    346
    347	return devm_iio_device_register(&spi->dev, indio_dev);
    348}
    349
    350static const struct acpi_device_id ad7298_acpi_ids[] = {
    351	{ "INT3494", 0 },
    352	{ }
    353};
    354MODULE_DEVICE_TABLE(acpi, ad7298_acpi_ids);
    355
    356static const struct spi_device_id ad7298_id[] = {
    357	{"ad7298", 0},
    358	{}
    359};
    360MODULE_DEVICE_TABLE(spi, ad7298_id);
    361
    362static struct spi_driver ad7298_driver = {
    363	.driver = {
    364		.name	= "ad7298",
    365		.acpi_match_table = ad7298_acpi_ids,
    366	},
    367	.probe		= ad7298_probe,
    368	.id_table	= ad7298_id,
    369};
    370module_spi_driver(ad7298_driver);
    371
    372MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
    373MODULE_DESCRIPTION("Analog Devices AD7298 ADC");
    374MODULE_LICENSE("GPL v2");