cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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lpc18xx_adc.c (5336B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * IIO ADC driver for NXP LPC18xx ADC
      4 *
      5 * Copyright (C) 2016 Joachim Eastwood <manabian@gmail.com>
      6 *
      7 * UNSUPPORTED hardware features:
      8 *  - Hardware triggers
      9 *  - Burst mode
     10 *  - Interrupts
     11 *  - DMA
     12 */
     13
     14#include <linux/clk.h>
     15#include <linux/err.h>
     16#include <linux/iio/iio.h>
     17#include <linux/iio/driver.h>
     18#include <linux/io.h>
     19#include <linux/iopoll.h>
     20#include <linux/module.h>
     21#include <linux/mutex.h>
     22#include <linux/of.h>
     23#include <linux/of_device.h>
     24#include <linux/platform_device.h>
     25#include <linux/regulator/consumer.h>
     26
     27/* LPC18XX ADC registers and bits */
     28#define LPC18XX_ADC_CR			0x000
     29#define  LPC18XX_ADC_CR_CLKDIV_SHIFT	8
     30#define  LPC18XX_ADC_CR_PDN		BIT(21)
     31#define  LPC18XX_ADC_CR_START_NOW	(0x1 << 24)
     32#define LPC18XX_ADC_GDR			0x004
     33
     34/* Data register bits */
     35#define LPC18XX_ADC_SAMPLE_SHIFT	6
     36#define LPC18XX_ADC_SAMPLE_MASK		0x3ff
     37#define LPC18XX_ADC_CONV_DONE		BIT(31)
     38
     39/* Clock should be 4.5 MHz or less */
     40#define LPC18XX_ADC_CLK_TARGET		4500000
     41
     42struct lpc18xx_adc {
     43	struct regulator *vref;
     44	void __iomem *base;
     45	struct device *dev;
     46	struct mutex lock;
     47	struct clk *clk;
     48	u32 cr_reg;
     49};
     50
     51#define LPC18XX_ADC_CHAN(_idx) {				\
     52	.type = IIO_VOLTAGE,					\
     53	.indexed = 1,						\
     54	.channel = _idx,					\
     55	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
     56	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
     57}
     58
     59static const struct iio_chan_spec lpc18xx_adc_iio_channels[] = {
     60	LPC18XX_ADC_CHAN(0),
     61	LPC18XX_ADC_CHAN(1),
     62	LPC18XX_ADC_CHAN(2),
     63	LPC18XX_ADC_CHAN(3),
     64	LPC18XX_ADC_CHAN(4),
     65	LPC18XX_ADC_CHAN(5),
     66	LPC18XX_ADC_CHAN(6),
     67	LPC18XX_ADC_CHAN(7),
     68};
     69
     70static int lpc18xx_adc_read_chan(struct lpc18xx_adc *adc, unsigned int ch)
     71{
     72	int ret;
     73	u32 reg;
     74
     75	reg = adc->cr_reg | BIT(ch) | LPC18XX_ADC_CR_START_NOW;
     76	writel(reg, adc->base + LPC18XX_ADC_CR);
     77
     78	ret = readl_poll_timeout(adc->base + LPC18XX_ADC_GDR, reg,
     79				 reg & LPC18XX_ADC_CONV_DONE, 3, 9);
     80	if (ret) {
     81		dev_warn(adc->dev, "adc read timed out\n");
     82		return ret;
     83	}
     84
     85	return (reg >> LPC18XX_ADC_SAMPLE_SHIFT) & LPC18XX_ADC_SAMPLE_MASK;
     86}
     87
     88static int lpc18xx_adc_read_raw(struct iio_dev *indio_dev,
     89				struct iio_chan_spec const *chan,
     90				int *val, int *val2, long mask)
     91{
     92	struct lpc18xx_adc *adc = iio_priv(indio_dev);
     93
     94	switch (mask) {
     95	case IIO_CHAN_INFO_RAW:
     96		mutex_lock(&adc->lock);
     97		*val = lpc18xx_adc_read_chan(adc, chan->channel);
     98		mutex_unlock(&adc->lock);
     99		if (*val < 0)
    100			return *val;
    101
    102		return IIO_VAL_INT;
    103
    104	case IIO_CHAN_INFO_SCALE:
    105		*val = regulator_get_voltage(adc->vref) / 1000;
    106		*val2 = 10;
    107
    108		return IIO_VAL_FRACTIONAL_LOG2;
    109	}
    110
    111	return -EINVAL;
    112}
    113
    114static const struct iio_info lpc18xx_adc_info = {
    115	.read_raw = lpc18xx_adc_read_raw,
    116};
    117
    118static void lpc18xx_clear_cr_reg(void *data)
    119{
    120	struct lpc18xx_adc *adc = data;
    121
    122	writel(0, adc->base + LPC18XX_ADC_CR);
    123}
    124
    125static void lpc18xx_clk_disable(void *clk)
    126{
    127	clk_disable_unprepare(clk);
    128}
    129
    130static void lpc18xx_regulator_disable(void *vref)
    131{
    132	regulator_disable(vref);
    133}
    134
    135static int lpc18xx_adc_probe(struct platform_device *pdev)
    136{
    137	struct iio_dev *indio_dev;
    138	struct lpc18xx_adc *adc;
    139	unsigned int clkdiv;
    140	unsigned long rate;
    141	int ret;
    142
    143	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
    144	if (!indio_dev)
    145		return -ENOMEM;
    146
    147	adc = iio_priv(indio_dev);
    148	adc->dev = &pdev->dev;
    149	mutex_init(&adc->lock);
    150
    151	adc->base = devm_platform_ioremap_resource(pdev, 0);
    152	if (IS_ERR(adc->base))
    153		return PTR_ERR(adc->base);
    154
    155	adc->clk = devm_clk_get(&pdev->dev, NULL);
    156	if (IS_ERR(adc->clk))
    157		return dev_err_probe(&pdev->dev, PTR_ERR(adc->clk),
    158				     "error getting clock\n");
    159
    160	adc->vref = devm_regulator_get(&pdev->dev, "vref");
    161	if (IS_ERR(adc->vref))
    162		return dev_err_probe(&pdev->dev, PTR_ERR(adc->vref),
    163				     "error getting regulator\n");
    164
    165	indio_dev->name = dev_name(&pdev->dev);
    166	indio_dev->info = &lpc18xx_adc_info;
    167	indio_dev->modes = INDIO_DIRECT_MODE;
    168	indio_dev->channels = lpc18xx_adc_iio_channels;
    169	indio_dev->num_channels = ARRAY_SIZE(lpc18xx_adc_iio_channels);
    170
    171	ret = regulator_enable(adc->vref);
    172	if (ret) {
    173		dev_err(&pdev->dev, "unable to enable regulator\n");
    174		return ret;
    175	}
    176
    177	ret = devm_add_action_or_reset(&pdev->dev, lpc18xx_regulator_disable, adc->vref);
    178	if (ret)
    179		return ret;
    180
    181	ret = clk_prepare_enable(adc->clk);
    182	if (ret) {
    183		dev_err(&pdev->dev, "unable to enable clock\n");
    184		return ret;
    185	}
    186
    187	ret = devm_add_action_or_reset(&pdev->dev, lpc18xx_clk_disable,
    188				       adc->clk);
    189	if (ret)
    190		return ret;
    191
    192	rate = clk_get_rate(adc->clk);
    193	clkdiv = DIV_ROUND_UP(rate, LPC18XX_ADC_CLK_TARGET);
    194
    195	adc->cr_reg = (clkdiv << LPC18XX_ADC_CR_CLKDIV_SHIFT) |
    196			LPC18XX_ADC_CR_PDN;
    197	writel(adc->cr_reg, adc->base + LPC18XX_ADC_CR);
    198
    199	ret = devm_add_action_or_reset(&pdev->dev, lpc18xx_clear_cr_reg, adc);
    200	if (ret)
    201		return ret;
    202
    203	return devm_iio_device_register(&pdev->dev, indio_dev);
    204}
    205
    206static const struct of_device_id lpc18xx_adc_match[] = {
    207	{ .compatible = "nxp,lpc1850-adc" },
    208	{ /* sentinel */ }
    209};
    210MODULE_DEVICE_TABLE(of, lpc18xx_adc_match);
    211
    212static struct platform_driver lpc18xx_adc_driver = {
    213	.probe	= lpc18xx_adc_probe,
    214	.driver	= {
    215		.name = "lpc18xx-adc",
    216		.of_match_table = lpc18xx_adc_match,
    217	},
    218};
    219module_platform_driver(lpc18xx_adc_driver);
    220
    221MODULE_DESCRIPTION("LPC18xx ADC driver");
    222MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
    223MODULE_LICENSE("GPL v2");