cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

stm32-adc-core.h (6260B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * This file is part of STM32 ADC driver
      4 *
      5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
      6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
      7 *
      8 */
      9
     10#ifndef __STM32_ADC_H
     11#define __STM32_ADC_H
     12
     13/*
     14 * STM32 - ADC global register map
     15 * ________________________________________________________
     16 * | Offset |                 Register                    |
     17 * --------------------------------------------------------
     18 * | 0x000  |                Master ADC1                  |
     19 * --------------------------------------------------------
     20 * | 0x100  |                Slave ADC2                   |
     21 * --------------------------------------------------------
     22 * | 0x200  |                Slave ADC3                   |
     23 * --------------------------------------------------------
     24 * | 0x300  |         Master & Slave common regs          |
     25 * --------------------------------------------------------
     26 */
     27#define STM32_ADC_MAX_ADCS		3
     28#define STM32_ADC_OFFSET		0x100
     29#define STM32_ADCX_COMN_OFFSET		0x300
     30
     31/* STM32F4 - Registers for each ADC instance */
     32#define STM32F4_ADC_SR			0x00
     33#define STM32F4_ADC_CR1			0x04
     34#define STM32F4_ADC_CR2			0x08
     35#define STM32F4_ADC_SMPR1		0x0C
     36#define STM32F4_ADC_SMPR2		0x10
     37#define STM32F4_ADC_HTR			0x24
     38#define STM32F4_ADC_LTR			0x28
     39#define STM32F4_ADC_SQR1		0x2C
     40#define STM32F4_ADC_SQR2		0x30
     41#define STM32F4_ADC_SQR3		0x34
     42#define STM32F4_ADC_JSQR		0x38
     43#define STM32F4_ADC_JDR1		0x3C
     44#define STM32F4_ADC_JDR2		0x40
     45#define STM32F4_ADC_JDR3		0x44
     46#define STM32F4_ADC_JDR4		0x48
     47#define STM32F4_ADC_DR			0x4C
     48
     49/* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
     50#define STM32F4_ADC_CSR			(STM32_ADCX_COMN_OFFSET + 0x00)
     51#define STM32F4_ADC_CCR			(STM32_ADCX_COMN_OFFSET + 0x04)
     52
     53/* STM32F4_ADC_SR - bit fields */
     54#define STM32F4_OVR			BIT(5)
     55#define STM32F4_STRT			BIT(4)
     56#define STM32F4_EOC			BIT(1)
     57
     58/* STM32F4_ADC_CR1 - bit fields */
     59#define STM32F4_OVRIE			BIT(26)
     60#define STM32F4_RES_SHIFT		24
     61#define STM32F4_RES_MASK		GENMASK(25, 24)
     62#define STM32F4_SCAN			BIT(8)
     63#define STM32F4_EOCIE			BIT(5)
     64
     65/* STM32F4_ADC_CR2 - bit fields */
     66#define STM32F4_SWSTART			BIT(30)
     67#define STM32F4_EXTEN_SHIFT		28
     68#define STM32F4_EXTEN_MASK		GENMASK(29, 28)
     69#define STM32F4_EXTSEL_SHIFT		24
     70#define STM32F4_EXTSEL_MASK		GENMASK(27, 24)
     71#define STM32F4_EOCS			BIT(10)
     72#define STM32F4_DDS			BIT(9)
     73#define STM32F4_DMA			BIT(8)
     74#define STM32F4_ADON			BIT(0)
     75
     76/* STM32F4_ADC_CSR - bit fields */
     77#define STM32F4_OVR3			BIT(21)
     78#define STM32F4_EOC3			BIT(17)
     79#define STM32F4_OVR2			BIT(13)
     80#define STM32F4_EOC2			BIT(9)
     81#define STM32F4_OVR1			BIT(5)
     82#define STM32F4_EOC1			BIT(1)
     83
     84/* STM32F4_ADC_CCR - bit fields */
     85#define STM32F4_ADC_ADCPRE_SHIFT	16
     86#define STM32F4_ADC_ADCPRE_MASK		GENMASK(17, 16)
     87
     88/* STM32H7 - Registers for each ADC instance */
     89#define STM32H7_ADC_ISR			0x00
     90#define STM32H7_ADC_IER			0x04
     91#define STM32H7_ADC_CR			0x08
     92#define STM32H7_ADC_CFGR		0x0C
     93#define STM32H7_ADC_SMPR1		0x14
     94#define STM32H7_ADC_SMPR2		0x18
     95#define STM32H7_ADC_PCSEL		0x1C
     96#define STM32H7_ADC_SQR1		0x30
     97#define STM32H7_ADC_SQR2		0x34
     98#define STM32H7_ADC_SQR3		0x38
     99#define STM32H7_ADC_SQR4		0x3C
    100#define STM32H7_ADC_DR			0x40
    101#define STM32H7_ADC_DIFSEL		0xC0
    102#define STM32H7_ADC_CALFACT		0xC4
    103#define STM32H7_ADC_CALFACT2		0xC8
    104
    105/* STM32MP1 - ADC2 instance option register */
    106#define STM32MP1_ADC2_OR		0xD0
    107
    108/* STM32H7 - common registers for all ADC instances */
    109#define STM32H7_ADC_CSR			(STM32_ADCX_COMN_OFFSET + 0x00)
    110#define STM32H7_ADC_CCR			(STM32_ADCX_COMN_OFFSET + 0x08)
    111
    112/* STM32H7_ADC_ISR - bit fields */
    113#define STM32MP1_VREGREADY		BIT(12)
    114#define STM32H7_OVR			BIT(4)
    115#define STM32H7_EOC			BIT(2)
    116#define STM32H7_ADRDY			BIT(0)
    117
    118/* STM32H7_ADC_IER - bit fields */
    119#define STM32H7_OVRIE			STM32H7_OVR
    120#define STM32H7_EOCIE			STM32H7_EOC
    121
    122/* STM32H7_ADC_CR - bit fields */
    123#define STM32H7_ADCAL			BIT(31)
    124#define STM32H7_ADCALDIF		BIT(30)
    125#define STM32H7_DEEPPWD			BIT(29)
    126#define STM32H7_ADVREGEN		BIT(28)
    127#define STM32H7_LINCALRDYW6		BIT(27)
    128#define STM32H7_LINCALRDYW5		BIT(26)
    129#define STM32H7_LINCALRDYW4		BIT(25)
    130#define STM32H7_LINCALRDYW3		BIT(24)
    131#define STM32H7_LINCALRDYW2		BIT(23)
    132#define STM32H7_LINCALRDYW1		BIT(22)
    133#define STM32H7_ADCALLIN		BIT(16)
    134#define STM32H7_BOOST			BIT(8)
    135#define STM32H7_ADSTP			BIT(4)
    136#define STM32H7_ADSTART			BIT(2)
    137#define STM32H7_ADDIS			BIT(1)
    138#define STM32H7_ADEN			BIT(0)
    139
    140/* STM32H7_ADC_CFGR bit fields */
    141#define STM32H7_EXTEN_SHIFT		10
    142#define STM32H7_EXTEN_MASK		GENMASK(11, 10)
    143#define STM32H7_EXTSEL_SHIFT		5
    144#define STM32H7_EXTSEL_MASK		GENMASK(9, 5)
    145#define STM32H7_RES_SHIFT		2
    146#define STM32H7_RES_MASK		GENMASK(4, 2)
    147#define STM32H7_DMNGT_SHIFT		0
    148#define STM32H7_DMNGT_MASK		GENMASK(1, 0)
    149
    150enum stm32h7_adc_dmngt {
    151	STM32H7_DMNGT_DR_ONLY,		/* Regular data in DR only */
    152	STM32H7_DMNGT_DMA_ONESHOT,	/* DMA one shot mode */
    153	STM32H7_DMNGT_DFSDM,		/* DFSDM mode */
    154	STM32H7_DMNGT_DMA_CIRC,		/* DMA circular mode */
    155};
    156
    157/* STM32H7_ADC_CALFACT - bit fields */
    158#define STM32H7_CALFACT_D_SHIFT		16
    159#define STM32H7_CALFACT_D_MASK		GENMASK(26, 16)
    160#define STM32H7_CALFACT_S_SHIFT		0
    161#define STM32H7_CALFACT_S_MASK		GENMASK(10, 0)
    162
    163/* STM32H7_ADC_CALFACT2 - bit fields */
    164#define STM32H7_LINCALFACT_SHIFT	0
    165#define STM32H7_LINCALFACT_MASK		GENMASK(29, 0)
    166
    167/* STM32H7_ADC_CSR - bit fields */
    168#define STM32H7_OVR_SLV			BIT(20)
    169#define STM32H7_EOC_SLV			BIT(18)
    170#define STM32H7_OVR_MST			BIT(4)
    171#define STM32H7_EOC_MST			BIT(2)
    172
    173/* STM32H7_ADC_CCR - bit fields */
    174#define STM32H7_VBATEN			BIT(24)
    175#define STM32H7_VREFEN			BIT(22)
    176#define STM32H7_PRESC_SHIFT		18
    177#define STM32H7_PRESC_MASK		GENMASK(21, 18)
    178#define STM32H7_CKMODE_SHIFT		16
    179#define STM32H7_CKMODE_MASK		GENMASK(17, 16)
    180
    181/* STM32MP1_ADC2_OR - bit fields */
    182#define STM32MP1_VDDCOREEN		BIT(0)
    183
    184/**
    185 * struct stm32_adc_common - stm32 ADC driver common data (for all instances)
    186 * @base:		control registers base cpu addr
    187 * @phys_base:		control registers base physical addr
    188 * @rate:		clock rate used for analog circuitry
    189 * @vref_mv:		vref voltage (mv)
    190 * @lock:		spinlock
    191 */
    192struct stm32_adc_common {
    193	void __iomem			*base;
    194	phys_addr_t			phys_base;
    195	unsigned long			rate;
    196	int				vref_mv;
    197	spinlock_t			lock;		/* lock for common register */
    198};
    199
    200#endif