qib_7322_regs.h (163315B)
1/* 2 * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33/* This file is mechanically generated from RTL. Any hand-edits will be lost! */ 34 35#define QIB_7322_Revision_OFFS 0x0 36#define QIB_7322_Revision_DEF 0x0000000002010601 37#define QIB_7322_Revision_R_Simulator_LSB 0x3F 38#define QIB_7322_Revision_R_Simulator_MSB 0x3F 39#define QIB_7322_Revision_R_Simulator_RMASK 0x1 40#define QIB_7322_Revision_R_Emulation_LSB 0x3E 41#define QIB_7322_Revision_R_Emulation_MSB 0x3E 42#define QIB_7322_Revision_R_Emulation_RMASK 0x1 43#define QIB_7322_Revision_R_Emulation_Revcode_LSB 0x28 44#define QIB_7322_Revision_R_Emulation_Revcode_MSB 0x3D 45#define QIB_7322_Revision_R_Emulation_Revcode_RMASK 0x3FFFFF 46#define QIB_7322_Revision_BoardID_LSB 0x20 47#define QIB_7322_Revision_BoardID_MSB 0x27 48#define QIB_7322_Revision_BoardID_RMASK 0xFF 49#define QIB_7322_Revision_R_SW_LSB 0x18 50#define QIB_7322_Revision_R_SW_MSB 0x1F 51#define QIB_7322_Revision_R_SW_RMASK 0xFF 52#define QIB_7322_Revision_R_Arch_LSB 0x10 53#define QIB_7322_Revision_R_Arch_MSB 0x17 54#define QIB_7322_Revision_R_Arch_RMASK 0xFF 55#define QIB_7322_Revision_R_ChipRevMajor_LSB 0x8 56#define QIB_7322_Revision_R_ChipRevMajor_MSB 0xF 57#define QIB_7322_Revision_R_ChipRevMajor_RMASK 0xFF 58#define QIB_7322_Revision_R_ChipRevMinor_LSB 0x0 59#define QIB_7322_Revision_R_ChipRevMinor_MSB 0x7 60#define QIB_7322_Revision_R_ChipRevMinor_RMASK 0xFF 61 62#define QIB_7322_Control_OFFS 0x8 63#define QIB_7322_Control_DEF 0x0000000000000000 64#define QIB_7322_Control_PCIECplQDiagEn_LSB 0x6 65#define QIB_7322_Control_PCIECplQDiagEn_MSB 0x6 66#define QIB_7322_Control_PCIECplQDiagEn_RMASK 0x1 67#define QIB_7322_Control_PCIEPostQDiagEn_LSB 0x5 68#define QIB_7322_Control_PCIEPostQDiagEn_MSB 0x5 69#define QIB_7322_Control_PCIEPostQDiagEn_RMASK 0x1 70#define QIB_7322_Control_SDmaDescFetchPriorityEn_LSB 0x4 71#define QIB_7322_Control_SDmaDescFetchPriorityEn_MSB 0x4 72#define QIB_7322_Control_SDmaDescFetchPriorityEn_RMASK 0x1 73#define QIB_7322_Control_PCIERetryBufDiagEn_LSB 0x3 74#define QIB_7322_Control_PCIERetryBufDiagEn_MSB 0x3 75#define QIB_7322_Control_PCIERetryBufDiagEn_RMASK 0x1 76#define QIB_7322_Control_FreezeMode_LSB 0x1 77#define QIB_7322_Control_FreezeMode_MSB 0x1 78#define QIB_7322_Control_FreezeMode_RMASK 0x1 79#define QIB_7322_Control_SyncReset_LSB 0x0 80#define QIB_7322_Control_SyncReset_MSB 0x0 81#define QIB_7322_Control_SyncReset_RMASK 0x1 82 83#define QIB_7322_PageAlign_OFFS 0x10 84#define QIB_7322_PageAlign_DEF 0x0000000000001000 85 86#define QIB_7322_ContextCnt_OFFS 0x18 87#define QIB_7322_ContextCnt_DEF 0x0000000000000012 88 89#define QIB_7322_Scratch_OFFS 0x20 90#define QIB_7322_Scratch_DEF 0x0000000000000000 91 92#define QIB_7322_CntrRegBase_OFFS 0x28 93#define QIB_7322_CntrRegBase_DEF 0x0000000000011000 94 95#define QIB_7322_SendRegBase_OFFS 0x30 96#define QIB_7322_SendRegBase_DEF 0x0000000000003000 97 98#define QIB_7322_UserRegBase_OFFS 0x38 99#define QIB_7322_UserRegBase_DEF 0x0000000000200000 100 101#define QIB_7322_IntMask_OFFS 0x68 102#define QIB_7322_IntMask_DEF 0x0000000000000000 103#define QIB_7322_IntMask_SDmaIntMask_1_LSB 0x3F 104#define QIB_7322_IntMask_SDmaIntMask_1_MSB 0x3F 105#define QIB_7322_IntMask_SDmaIntMask_1_RMASK 0x1 106#define QIB_7322_IntMask_SDmaIntMask_0_LSB 0x3E 107#define QIB_7322_IntMask_SDmaIntMask_0_MSB 0x3E 108#define QIB_7322_IntMask_SDmaIntMask_0_RMASK 0x1 109#define QIB_7322_IntMask_SDmaProgressIntMask_1_LSB 0x3D 110#define QIB_7322_IntMask_SDmaProgressIntMask_1_MSB 0x3D 111#define QIB_7322_IntMask_SDmaProgressIntMask_1_RMASK 0x1 112#define QIB_7322_IntMask_SDmaProgressIntMask_0_LSB 0x3C 113#define QIB_7322_IntMask_SDmaProgressIntMask_0_MSB 0x3C 114#define QIB_7322_IntMask_SDmaProgressIntMask_0_RMASK 0x1 115#define QIB_7322_IntMask_SDmaIdleIntMask_1_LSB 0x3B 116#define QIB_7322_IntMask_SDmaIdleIntMask_1_MSB 0x3B 117#define QIB_7322_IntMask_SDmaIdleIntMask_1_RMASK 0x1 118#define QIB_7322_IntMask_SDmaIdleIntMask_0_LSB 0x3A 119#define QIB_7322_IntMask_SDmaIdleIntMask_0_MSB 0x3A 120#define QIB_7322_IntMask_SDmaIdleIntMask_0_RMASK 0x1 121#define QIB_7322_IntMask_SDmaCleanupDoneMask_1_LSB 0x39 122#define QIB_7322_IntMask_SDmaCleanupDoneMask_1_MSB 0x39 123#define QIB_7322_IntMask_SDmaCleanupDoneMask_1_RMASK 0x1 124#define QIB_7322_IntMask_SDmaCleanupDoneMask_0_LSB 0x38 125#define QIB_7322_IntMask_SDmaCleanupDoneMask_0_MSB 0x38 126#define QIB_7322_IntMask_SDmaCleanupDoneMask_0_RMASK 0x1 127#define QIB_7322_IntMask_RcvUrg17IntMask_LSB 0x31 128#define QIB_7322_IntMask_RcvUrg17IntMask_MSB 0x31 129#define QIB_7322_IntMask_RcvUrg17IntMask_RMASK 0x1 130#define QIB_7322_IntMask_RcvUrg16IntMask_LSB 0x30 131#define QIB_7322_IntMask_RcvUrg16IntMask_MSB 0x30 132#define QIB_7322_IntMask_RcvUrg16IntMask_RMASK 0x1 133#define QIB_7322_IntMask_RcvUrg15IntMask_LSB 0x2F 134#define QIB_7322_IntMask_RcvUrg15IntMask_MSB 0x2F 135#define QIB_7322_IntMask_RcvUrg15IntMask_RMASK 0x1 136#define QIB_7322_IntMask_RcvUrg14IntMask_LSB 0x2E 137#define QIB_7322_IntMask_RcvUrg14IntMask_MSB 0x2E 138#define QIB_7322_IntMask_RcvUrg14IntMask_RMASK 0x1 139#define QIB_7322_IntMask_RcvUrg13IntMask_LSB 0x2D 140#define QIB_7322_IntMask_RcvUrg13IntMask_MSB 0x2D 141#define QIB_7322_IntMask_RcvUrg13IntMask_RMASK 0x1 142#define QIB_7322_IntMask_RcvUrg12IntMask_LSB 0x2C 143#define QIB_7322_IntMask_RcvUrg12IntMask_MSB 0x2C 144#define QIB_7322_IntMask_RcvUrg12IntMask_RMASK 0x1 145#define QIB_7322_IntMask_RcvUrg11IntMask_LSB 0x2B 146#define QIB_7322_IntMask_RcvUrg11IntMask_MSB 0x2B 147#define QIB_7322_IntMask_RcvUrg11IntMask_RMASK 0x1 148#define QIB_7322_IntMask_RcvUrg10IntMask_LSB 0x2A 149#define QIB_7322_IntMask_RcvUrg10IntMask_MSB 0x2A 150#define QIB_7322_IntMask_RcvUrg10IntMask_RMASK 0x1 151#define QIB_7322_IntMask_RcvUrg9IntMask_LSB 0x29 152#define QIB_7322_IntMask_RcvUrg9IntMask_MSB 0x29 153#define QIB_7322_IntMask_RcvUrg9IntMask_RMASK 0x1 154#define QIB_7322_IntMask_RcvUrg8IntMask_LSB 0x28 155#define QIB_7322_IntMask_RcvUrg8IntMask_MSB 0x28 156#define QIB_7322_IntMask_RcvUrg8IntMask_RMASK 0x1 157#define QIB_7322_IntMask_RcvUrg7IntMask_LSB 0x27 158#define QIB_7322_IntMask_RcvUrg7IntMask_MSB 0x27 159#define QIB_7322_IntMask_RcvUrg7IntMask_RMASK 0x1 160#define QIB_7322_IntMask_RcvUrg6IntMask_LSB 0x26 161#define QIB_7322_IntMask_RcvUrg6IntMask_MSB 0x26 162#define QIB_7322_IntMask_RcvUrg6IntMask_RMASK 0x1 163#define QIB_7322_IntMask_RcvUrg5IntMask_LSB 0x25 164#define QIB_7322_IntMask_RcvUrg5IntMask_MSB 0x25 165#define QIB_7322_IntMask_RcvUrg5IntMask_RMASK 0x1 166#define QIB_7322_IntMask_RcvUrg4IntMask_LSB 0x24 167#define QIB_7322_IntMask_RcvUrg4IntMask_MSB 0x24 168#define QIB_7322_IntMask_RcvUrg4IntMask_RMASK 0x1 169#define QIB_7322_IntMask_RcvUrg3IntMask_LSB 0x23 170#define QIB_7322_IntMask_RcvUrg3IntMask_MSB 0x23 171#define QIB_7322_IntMask_RcvUrg3IntMask_RMASK 0x1 172#define QIB_7322_IntMask_RcvUrg2IntMask_LSB 0x22 173#define QIB_7322_IntMask_RcvUrg2IntMask_MSB 0x22 174#define QIB_7322_IntMask_RcvUrg2IntMask_RMASK 0x1 175#define QIB_7322_IntMask_RcvUrg1IntMask_LSB 0x21 176#define QIB_7322_IntMask_RcvUrg1IntMask_MSB 0x21 177#define QIB_7322_IntMask_RcvUrg1IntMask_RMASK 0x1 178#define QIB_7322_IntMask_RcvUrg0IntMask_LSB 0x20 179#define QIB_7322_IntMask_RcvUrg0IntMask_MSB 0x20 180#define QIB_7322_IntMask_RcvUrg0IntMask_RMASK 0x1 181#define QIB_7322_IntMask_ErrIntMask_1_LSB 0x1F 182#define QIB_7322_IntMask_ErrIntMask_1_MSB 0x1F 183#define QIB_7322_IntMask_ErrIntMask_1_RMASK 0x1 184#define QIB_7322_IntMask_ErrIntMask_0_LSB 0x1E 185#define QIB_7322_IntMask_ErrIntMask_0_MSB 0x1E 186#define QIB_7322_IntMask_ErrIntMask_0_RMASK 0x1 187#define QIB_7322_IntMask_ErrIntMask_LSB 0x1D 188#define QIB_7322_IntMask_ErrIntMask_MSB 0x1D 189#define QIB_7322_IntMask_ErrIntMask_RMASK 0x1 190#define QIB_7322_IntMask_AssertGPIOIntMask_LSB 0x1C 191#define QIB_7322_IntMask_AssertGPIOIntMask_MSB 0x1C 192#define QIB_7322_IntMask_AssertGPIOIntMask_RMASK 0x1 193#define QIB_7322_IntMask_SendDoneIntMask_1_LSB 0x19 194#define QIB_7322_IntMask_SendDoneIntMask_1_MSB 0x19 195#define QIB_7322_IntMask_SendDoneIntMask_1_RMASK 0x1 196#define QIB_7322_IntMask_SendDoneIntMask_0_LSB 0x18 197#define QIB_7322_IntMask_SendDoneIntMask_0_MSB 0x18 198#define QIB_7322_IntMask_SendDoneIntMask_0_RMASK 0x1 199#define QIB_7322_IntMask_SendBufAvailIntMask_LSB 0x17 200#define QIB_7322_IntMask_SendBufAvailIntMask_MSB 0x17 201#define QIB_7322_IntMask_SendBufAvailIntMask_RMASK 0x1 202#define QIB_7322_IntMask_RcvAvail17IntMask_LSB 0x11 203#define QIB_7322_IntMask_RcvAvail17IntMask_MSB 0x11 204#define QIB_7322_IntMask_RcvAvail17IntMask_RMASK 0x1 205#define QIB_7322_IntMask_RcvAvail16IntMask_LSB 0x10 206#define QIB_7322_IntMask_RcvAvail16IntMask_MSB 0x10 207#define QIB_7322_IntMask_RcvAvail16IntMask_RMASK 0x1 208#define QIB_7322_IntMask_RcvAvail15IntMask_LSB 0xF 209#define QIB_7322_IntMask_RcvAvail15IntMask_MSB 0xF 210#define QIB_7322_IntMask_RcvAvail15IntMask_RMASK 0x1 211#define QIB_7322_IntMask_RcvAvail14IntMask_LSB 0xE 212#define QIB_7322_IntMask_RcvAvail14IntMask_MSB 0xE 213#define QIB_7322_IntMask_RcvAvail14IntMask_RMASK 0x1 214#define QIB_7322_IntMask_RcvAvail13IntMask_LSB 0xD 215#define QIB_7322_IntMask_RcvAvail13IntMask_MSB 0xD 216#define QIB_7322_IntMask_RcvAvail13IntMask_RMASK 0x1 217#define QIB_7322_IntMask_RcvAvail12IntMask_LSB 0xC 218#define QIB_7322_IntMask_RcvAvail12IntMask_MSB 0xC 219#define QIB_7322_IntMask_RcvAvail12IntMask_RMASK 0x1 220#define QIB_7322_IntMask_RcvAvail11IntMask_LSB 0xB 221#define QIB_7322_IntMask_RcvAvail11IntMask_MSB 0xB 222#define QIB_7322_IntMask_RcvAvail11IntMask_RMASK 0x1 223#define QIB_7322_IntMask_RcvAvail10IntMask_LSB 0xA 224#define QIB_7322_IntMask_RcvAvail10IntMask_MSB 0xA 225#define QIB_7322_IntMask_RcvAvail10IntMask_RMASK 0x1 226#define QIB_7322_IntMask_RcvAvail9IntMask_LSB 0x9 227#define QIB_7322_IntMask_RcvAvail9IntMask_MSB 0x9 228#define QIB_7322_IntMask_RcvAvail9IntMask_RMASK 0x1 229#define QIB_7322_IntMask_RcvAvail8IntMask_LSB 0x8 230#define QIB_7322_IntMask_RcvAvail8IntMask_MSB 0x8 231#define QIB_7322_IntMask_RcvAvail8IntMask_RMASK 0x1 232#define QIB_7322_IntMask_RcvAvail7IntMask_LSB 0x7 233#define QIB_7322_IntMask_RcvAvail7IntMask_MSB 0x7 234#define QIB_7322_IntMask_RcvAvail7IntMask_RMASK 0x1 235#define QIB_7322_IntMask_RcvAvail6IntMask_LSB 0x6 236#define QIB_7322_IntMask_RcvAvail6IntMask_MSB 0x6 237#define QIB_7322_IntMask_RcvAvail6IntMask_RMASK 0x1 238#define QIB_7322_IntMask_RcvAvail5IntMask_LSB 0x5 239#define QIB_7322_IntMask_RcvAvail5IntMask_MSB 0x5 240#define QIB_7322_IntMask_RcvAvail5IntMask_RMASK 0x1 241#define QIB_7322_IntMask_RcvAvail4IntMask_LSB 0x4 242#define QIB_7322_IntMask_RcvAvail4IntMask_MSB 0x4 243#define QIB_7322_IntMask_RcvAvail4IntMask_RMASK 0x1 244#define QIB_7322_IntMask_RcvAvail3IntMask_LSB 0x3 245#define QIB_7322_IntMask_RcvAvail3IntMask_MSB 0x3 246#define QIB_7322_IntMask_RcvAvail3IntMask_RMASK 0x1 247#define QIB_7322_IntMask_RcvAvail2IntMask_LSB 0x2 248#define QIB_7322_IntMask_RcvAvail2IntMask_MSB 0x2 249#define QIB_7322_IntMask_RcvAvail2IntMask_RMASK 0x1 250#define QIB_7322_IntMask_RcvAvail1IntMask_LSB 0x1 251#define QIB_7322_IntMask_RcvAvail1IntMask_MSB 0x1 252#define QIB_7322_IntMask_RcvAvail1IntMask_RMASK 0x1 253#define QIB_7322_IntMask_RcvAvail0IntMask_LSB 0x0 254#define QIB_7322_IntMask_RcvAvail0IntMask_MSB 0x0 255#define QIB_7322_IntMask_RcvAvail0IntMask_RMASK 0x1 256 257#define QIB_7322_IntStatus_OFFS 0x70 258#define QIB_7322_IntStatus_DEF 0x0000000000000000 259#define QIB_7322_IntStatus_SDmaInt_1_LSB 0x3F 260#define QIB_7322_IntStatus_SDmaInt_1_MSB 0x3F 261#define QIB_7322_IntStatus_SDmaInt_1_RMASK 0x1 262#define QIB_7322_IntStatus_SDmaInt_0_LSB 0x3E 263#define QIB_7322_IntStatus_SDmaInt_0_MSB 0x3E 264#define QIB_7322_IntStatus_SDmaInt_0_RMASK 0x1 265#define QIB_7322_IntStatus_SDmaProgressInt_1_LSB 0x3D 266#define QIB_7322_IntStatus_SDmaProgressInt_1_MSB 0x3D 267#define QIB_7322_IntStatus_SDmaProgressInt_1_RMASK 0x1 268#define QIB_7322_IntStatus_SDmaProgressInt_0_LSB 0x3C 269#define QIB_7322_IntStatus_SDmaProgressInt_0_MSB 0x3C 270#define QIB_7322_IntStatus_SDmaProgressInt_0_RMASK 0x1 271#define QIB_7322_IntStatus_SDmaIdleInt_1_LSB 0x3B 272#define QIB_7322_IntStatus_SDmaIdleInt_1_MSB 0x3B 273#define QIB_7322_IntStatus_SDmaIdleInt_1_RMASK 0x1 274#define QIB_7322_IntStatus_SDmaIdleInt_0_LSB 0x3A 275#define QIB_7322_IntStatus_SDmaIdleInt_0_MSB 0x3A 276#define QIB_7322_IntStatus_SDmaIdleInt_0_RMASK 0x1 277#define QIB_7322_IntStatus_SDmaCleanupDone_1_LSB 0x39 278#define QIB_7322_IntStatus_SDmaCleanupDone_1_MSB 0x39 279#define QIB_7322_IntStatus_SDmaCleanupDone_1_RMASK 0x1 280#define QIB_7322_IntStatus_SDmaCleanupDone_0_LSB 0x38 281#define QIB_7322_IntStatus_SDmaCleanupDone_0_MSB 0x38 282#define QIB_7322_IntStatus_SDmaCleanupDone_0_RMASK 0x1 283#define QIB_7322_IntStatus_RcvUrg17_LSB 0x31 284#define QIB_7322_IntStatus_RcvUrg17_MSB 0x31 285#define QIB_7322_IntStatus_RcvUrg17_RMASK 0x1 286#define QIB_7322_IntStatus_RcvUrg16_LSB 0x30 287#define QIB_7322_IntStatus_RcvUrg16_MSB 0x30 288#define QIB_7322_IntStatus_RcvUrg16_RMASK 0x1 289#define QIB_7322_IntStatus_RcvUrg15_LSB 0x2F 290#define QIB_7322_IntStatus_RcvUrg15_MSB 0x2F 291#define QIB_7322_IntStatus_RcvUrg15_RMASK 0x1 292#define QIB_7322_IntStatus_RcvUrg14_LSB 0x2E 293#define QIB_7322_IntStatus_RcvUrg14_MSB 0x2E 294#define QIB_7322_IntStatus_RcvUrg14_RMASK 0x1 295#define QIB_7322_IntStatus_RcvUrg13_LSB 0x2D 296#define QIB_7322_IntStatus_RcvUrg13_MSB 0x2D 297#define QIB_7322_IntStatus_RcvUrg13_RMASK 0x1 298#define QIB_7322_IntStatus_RcvUrg12_LSB 0x2C 299#define QIB_7322_IntStatus_RcvUrg12_MSB 0x2C 300#define QIB_7322_IntStatus_RcvUrg12_RMASK 0x1 301#define QIB_7322_IntStatus_RcvUrg11_LSB 0x2B 302#define QIB_7322_IntStatus_RcvUrg11_MSB 0x2B 303#define QIB_7322_IntStatus_RcvUrg11_RMASK 0x1 304#define QIB_7322_IntStatus_RcvUrg10_LSB 0x2A 305#define QIB_7322_IntStatus_RcvUrg10_MSB 0x2A 306#define QIB_7322_IntStatus_RcvUrg10_RMASK 0x1 307#define QIB_7322_IntStatus_RcvUrg9_LSB 0x29 308#define QIB_7322_IntStatus_RcvUrg9_MSB 0x29 309#define QIB_7322_IntStatus_RcvUrg9_RMASK 0x1 310#define QIB_7322_IntStatus_RcvUrg8_LSB 0x28 311#define QIB_7322_IntStatus_RcvUrg8_MSB 0x28 312#define QIB_7322_IntStatus_RcvUrg8_RMASK 0x1 313#define QIB_7322_IntStatus_RcvUrg7_LSB 0x27 314#define QIB_7322_IntStatus_RcvUrg7_MSB 0x27 315#define QIB_7322_IntStatus_RcvUrg7_RMASK 0x1 316#define QIB_7322_IntStatus_RcvUrg6_LSB 0x26 317#define QIB_7322_IntStatus_RcvUrg6_MSB 0x26 318#define QIB_7322_IntStatus_RcvUrg6_RMASK 0x1 319#define QIB_7322_IntStatus_RcvUrg5_LSB 0x25 320#define QIB_7322_IntStatus_RcvUrg5_MSB 0x25 321#define QIB_7322_IntStatus_RcvUrg5_RMASK 0x1 322#define QIB_7322_IntStatus_RcvUrg4_LSB 0x24 323#define QIB_7322_IntStatus_RcvUrg4_MSB 0x24 324#define QIB_7322_IntStatus_RcvUrg4_RMASK 0x1 325#define QIB_7322_IntStatus_RcvUrg3_LSB 0x23 326#define QIB_7322_IntStatus_RcvUrg3_MSB 0x23 327#define QIB_7322_IntStatus_RcvUrg3_RMASK 0x1 328#define QIB_7322_IntStatus_RcvUrg2_LSB 0x22 329#define QIB_7322_IntStatus_RcvUrg2_MSB 0x22 330#define QIB_7322_IntStatus_RcvUrg2_RMASK 0x1 331#define QIB_7322_IntStatus_RcvUrg1_LSB 0x21 332#define QIB_7322_IntStatus_RcvUrg1_MSB 0x21 333#define QIB_7322_IntStatus_RcvUrg1_RMASK 0x1 334#define QIB_7322_IntStatus_RcvUrg0_LSB 0x20 335#define QIB_7322_IntStatus_RcvUrg0_MSB 0x20 336#define QIB_7322_IntStatus_RcvUrg0_RMASK 0x1 337#define QIB_7322_IntStatus_Err_1_LSB 0x1F 338#define QIB_7322_IntStatus_Err_1_MSB 0x1F 339#define QIB_7322_IntStatus_Err_1_RMASK 0x1 340#define QIB_7322_IntStatus_Err_0_LSB 0x1E 341#define QIB_7322_IntStatus_Err_0_MSB 0x1E 342#define QIB_7322_IntStatus_Err_0_RMASK 0x1 343#define QIB_7322_IntStatus_Err_LSB 0x1D 344#define QIB_7322_IntStatus_Err_MSB 0x1D 345#define QIB_7322_IntStatus_Err_RMASK 0x1 346#define QIB_7322_IntStatus_AssertGPIO_LSB 0x1C 347#define QIB_7322_IntStatus_AssertGPIO_MSB 0x1C 348#define QIB_7322_IntStatus_AssertGPIO_RMASK 0x1 349#define QIB_7322_IntStatus_SendDone_1_LSB 0x19 350#define QIB_7322_IntStatus_SendDone_1_MSB 0x19 351#define QIB_7322_IntStatus_SendDone_1_RMASK 0x1 352#define QIB_7322_IntStatus_SendDone_0_LSB 0x18 353#define QIB_7322_IntStatus_SendDone_0_MSB 0x18 354#define QIB_7322_IntStatus_SendDone_0_RMASK 0x1 355#define QIB_7322_IntStatus_SendBufAvail_LSB 0x17 356#define QIB_7322_IntStatus_SendBufAvail_MSB 0x17 357#define QIB_7322_IntStatus_SendBufAvail_RMASK 0x1 358#define QIB_7322_IntStatus_RcvAvail17_LSB 0x11 359#define QIB_7322_IntStatus_RcvAvail17_MSB 0x11 360#define QIB_7322_IntStatus_RcvAvail17_RMASK 0x1 361#define QIB_7322_IntStatus_RcvAvail16_LSB 0x10 362#define QIB_7322_IntStatus_RcvAvail16_MSB 0x10 363#define QIB_7322_IntStatus_RcvAvail16_RMASK 0x1 364#define QIB_7322_IntStatus_RcvAvail15_LSB 0xF 365#define QIB_7322_IntStatus_RcvAvail15_MSB 0xF 366#define QIB_7322_IntStatus_RcvAvail15_RMASK 0x1 367#define QIB_7322_IntStatus_RcvAvail14_LSB 0xE 368#define QIB_7322_IntStatus_RcvAvail14_MSB 0xE 369#define QIB_7322_IntStatus_RcvAvail14_RMASK 0x1 370#define QIB_7322_IntStatus_RcvAvail13_LSB 0xD 371#define QIB_7322_IntStatus_RcvAvail13_MSB 0xD 372#define QIB_7322_IntStatus_RcvAvail13_RMASK 0x1 373#define QIB_7322_IntStatus_RcvAvail12_LSB 0xC 374#define QIB_7322_IntStatus_RcvAvail12_MSB 0xC 375#define QIB_7322_IntStatus_RcvAvail12_RMASK 0x1 376#define QIB_7322_IntStatus_RcvAvail11_LSB 0xB 377#define QIB_7322_IntStatus_RcvAvail11_MSB 0xB 378#define QIB_7322_IntStatus_RcvAvail11_RMASK 0x1 379#define QIB_7322_IntStatus_RcvAvail10_LSB 0xA 380#define QIB_7322_IntStatus_RcvAvail10_MSB 0xA 381#define QIB_7322_IntStatus_RcvAvail10_RMASK 0x1 382#define QIB_7322_IntStatus_RcvAvail9_LSB 0x9 383#define QIB_7322_IntStatus_RcvAvail9_MSB 0x9 384#define QIB_7322_IntStatus_RcvAvail9_RMASK 0x1 385#define QIB_7322_IntStatus_RcvAvail8_LSB 0x8 386#define QIB_7322_IntStatus_RcvAvail8_MSB 0x8 387#define QIB_7322_IntStatus_RcvAvail8_RMASK 0x1 388#define QIB_7322_IntStatus_RcvAvail7_LSB 0x7 389#define QIB_7322_IntStatus_RcvAvail7_MSB 0x7 390#define QIB_7322_IntStatus_RcvAvail7_RMASK 0x1 391#define QIB_7322_IntStatus_RcvAvail6_LSB 0x6 392#define QIB_7322_IntStatus_RcvAvail6_MSB 0x6 393#define QIB_7322_IntStatus_RcvAvail6_RMASK 0x1 394#define QIB_7322_IntStatus_RcvAvail5_LSB 0x5 395#define QIB_7322_IntStatus_RcvAvail5_MSB 0x5 396#define QIB_7322_IntStatus_RcvAvail5_RMASK 0x1 397#define QIB_7322_IntStatus_RcvAvail4_LSB 0x4 398#define QIB_7322_IntStatus_RcvAvail4_MSB 0x4 399#define QIB_7322_IntStatus_RcvAvail4_RMASK 0x1 400#define QIB_7322_IntStatus_RcvAvail3_LSB 0x3 401#define QIB_7322_IntStatus_RcvAvail3_MSB 0x3 402#define QIB_7322_IntStatus_RcvAvail3_RMASK 0x1 403#define QIB_7322_IntStatus_RcvAvail2_LSB 0x2 404#define QIB_7322_IntStatus_RcvAvail2_MSB 0x2 405#define QIB_7322_IntStatus_RcvAvail2_RMASK 0x1 406#define QIB_7322_IntStatus_RcvAvail1_LSB 0x1 407#define QIB_7322_IntStatus_RcvAvail1_MSB 0x1 408#define QIB_7322_IntStatus_RcvAvail1_RMASK 0x1 409#define QIB_7322_IntStatus_RcvAvail0_LSB 0x0 410#define QIB_7322_IntStatus_RcvAvail0_MSB 0x0 411#define QIB_7322_IntStatus_RcvAvail0_RMASK 0x1 412 413#define QIB_7322_IntClear_OFFS 0x78 414#define QIB_7322_IntClear_DEF 0x0000000000000000 415#define QIB_7322_IntClear_SDmaIntClear_1_LSB 0x3F 416#define QIB_7322_IntClear_SDmaIntClear_1_MSB 0x3F 417#define QIB_7322_IntClear_SDmaIntClear_1_RMASK 0x1 418#define QIB_7322_IntClear_SDmaIntClear_0_LSB 0x3E 419#define QIB_7322_IntClear_SDmaIntClear_0_MSB 0x3E 420#define QIB_7322_IntClear_SDmaIntClear_0_RMASK 0x1 421#define QIB_7322_IntClear_SDmaProgressIntClear_1_LSB 0x3D 422#define QIB_7322_IntClear_SDmaProgressIntClear_1_MSB 0x3D 423#define QIB_7322_IntClear_SDmaProgressIntClear_1_RMASK 0x1 424#define QIB_7322_IntClear_SDmaProgressIntClear_0_LSB 0x3C 425#define QIB_7322_IntClear_SDmaProgressIntClear_0_MSB 0x3C 426#define QIB_7322_IntClear_SDmaProgressIntClear_0_RMASK 0x1 427#define QIB_7322_IntClear_SDmaIdleIntClear_1_LSB 0x3B 428#define QIB_7322_IntClear_SDmaIdleIntClear_1_MSB 0x3B 429#define QIB_7322_IntClear_SDmaIdleIntClear_1_RMASK 0x1 430#define QIB_7322_IntClear_SDmaIdleIntClear_0_LSB 0x3A 431#define QIB_7322_IntClear_SDmaIdleIntClear_0_MSB 0x3A 432#define QIB_7322_IntClear_SDmaIdleIntClear_0_RMASK 0x1 433#define QIB_7322_IntClear_SDmaCleanupDoneClear_1_LSB 0x39 434#define QIB_7322_IntClear_SDmaCleanupDoneClear_1_MSB 0x39 435#define QIB_7322_IntClear_SDmaCleanupDoneClear_1_RMASK 0x1 436#define QIB_7322_IntClear_SDmaCleanupDoneClear_0_LSB 0x38 437#define QIB_7322_IntClear_SDmaCleanupDoneClear_0_MSB 0x38 438#define QIB_7322_IntClear_SDmaCleanupDoneClear_0_RMASK 0x1 439#define QIB_7322_IntClear_RcvUrg17IntClear_LSB 0x31 440#define QIB_7322_IntClear_RcvUrg17IntClear_MSB 0x31 441#define QIB_7322_IntClear_RcvUrg17IntClear_RMASK 0x1 442#define QIB_7322_IntClear_RcvUrg16IntClear_LSB 0x30 443#define QIB_7322_IntClear_RcvUrg16IntClear_MSB 0x30 444#define QIB_7322_IntClear_RcvUrg16IntClear_RMASK 0x1 445#define QIB_7322_IntClear_RcvUrg15IntClear_LSB 0x2F 446#define QIB_7322_IntClear_RcvUrg15IntClear_MSB 0x2F 447#define QIB_7322_IntClear_RcvUrg15IntClear_RMASK 0x1 448#define QIB_7322_IntClear_RcvUrg14IntClear_LSB 0x2E 449#define QIB_7322_IntClear_RcvUrg14IntClear_MSB 0x2E 450#define QIB_7322_IntClear_RcvUrg14IntClear_RMASK 0x1 451#define QIB_7322_IntClear_RcvUrg13IntClear_LSB 0x2D 452#define QIB_7322_IntClear_RcvUrg13IntClear_MSB 0x2D 453#define QIB_7322_IntClear_RcvUrg13IntClear_RMASK 0x1 454#define QIB_7322_IntClear_RcvUrg12IntClear_LSB 0x2C 455#define QIB_7322_IntClear_RcvUrg12IntClear_MSB 0x2C 456#define QIB_7322_IntClear_RcvUrg12IntClear_RMASK 0x1 457#define QIB_7322_IntClear_RcvUrg11IntClear_LSB 0x2B 458#define QIB_7322_IntClear_RcvUrg11IntClear_MSB 0x2B 459#define QIB_7322_IntClear_RcvUrg11IntClear_RMASK 0x1 460#define QIB_7322_IntClear_RcvUrg10IntClear_LSB 0x2A 461#define QIB_7322_IntClear_RcvUrg10IntClear_MSB 0x2A 462#define QIB_7322_IntClear_RcvUrg10IntClear_RMASK 0x1 463#define QIB_7322_IntClear_RcvUrg9IntClear_LSB 0x29 464#define QIB_7322_IntClear_RcvUrg9IntClear_MSB 0x29 465#define QIB_7322_IntClear_RcvUrg9IntClear_RMASK 0x1 466#define QIB_7322_IntClear_RcvUrg8IntClear_LSB 0x28 467#define QIB_7322_IntClear_RcvUrg8IntClear_MSB 0x28 468#define QIB_7322_IntClear_RcvUrg8IntClear_RMASK 0x1 469#define QIB_7322_IntClear_RcvUrg7IntClear_LSB 0x27 470#define QIB_7322_IntClear_RcvUrg7IntClear_MSB 0x27 471#define QIB_7322_IntClear_RcvUrg7IntClear_RMASK 0x1 472#define QIB_7322_IntClear_RcvUrg6IntClear_LSB 0x26 473#define QIB_7322_IntClear_RcvUrg6IntClear_MSB 0x26 474#define QIB_7322_IntClear_RcvUrg6IntClear_RMASK 0x1 475#define QIB_7322_IntClear_RcvUrg5IntClear_LSB 0x25 476#define QIB_7322_IntClear_RcvUrg5IntClear_MSB 0x25 477#define QIB_7322_IntClear_RcvUrg5IntClear_RMASK 0x1 478#define QIB_7322_IntClear_RcvUrg4IntClear_LSB 0x24 479#define QIB_7322_IntClear_RcvUrg4IntClear_MSB 0x24 480#define QIB_7322_IntClear_RcvUrg4IntClear_RMASK 0x1 481#define QIB_7322_IntClear_RcvUrg3IntClear_LSB 0x23 482#define QIB_7322_IntClear_RcvUrg3IntClear_MSB 0x23 483#define QIB_7322_IntClear_RcvUrg3IntClear_RMASK 0x1 484#define QIB_7322_IntClear_RcvUrg2IntClear_LSB 0x22 485#define QIB_7322_IntClear_RcvUrg2IntClear_MSB 0x22 486#define QIB_7322_IntClear_RcvUrg2IntClear_RMASK 0x1 487#define QIB_7322_IntClear_RcvUrg1IntClear_LSB 0x21 488#define QIB_7322_IntClear_RcvUrg1IntClear_MSB 0x21 489#define QIB_7322_IntClear_RcvUrg1IntClear_RMASK 0x1 490#define QIB_7322_IntClear_RcvUrg0IntClear_LSB 0x20 491#define QIB_7322_IntClear_RcvUrg0IntClear_MSB 0x20 492#define QIB_7322_IntClear_RcvUrg0IntClear_RMASK 0x1 493#define QIB_7322_IntClear_ErrIntClear_1_LSB 0x1F 494#define QIB_7322_IntClear_ErrIntClear_1_MSB 0x1F 495#define QIB_7322_IntClear_ErrIntClear_1_RMASK 0x1 496#define QIB_7322_IntClear_ErrIntClear_0_LSB 0x1E 497#define QIB_7322_IntClear_ErrIntClear_0_MSB 0x1E 498#define QIB_7322_IntClear_ErrIntClear_0_RMASK 0x1 499#define QIB_7322_IntClear_ErrIntClear_LSB 0x1D 500#define QIB_7322_IntClear_ErrIntClear_MSB 0x1D 501#define QIB_7322_IntClear_ErrIntClear_RMASK 0x1 502#define QIB_7322_IntClear_AssertGPIOIntClear_LSB 0x1C 503#define QIB_7322_IntClear_AssertGPIOIntClear_MSB 0x1C 504#define QIB_7322_IntClear_AssertGPIOIntClear_RMASK 0x1 505#define QIB_7322_IntClear_SendDoneIntClear_1_LSB 0x19 506#define QIB_7322_IntClear_SendDoneIntClear_1_MSB 0x19 507#define QIB_7322_IntClear_SendDoneIntClear_1_RMASK 0x1 508#define QIB_7322_IntClear_SendDoneIntClear_0_LSB 0x18 509#define QIB_7322_IntClear_SendDoneIntClear_0_MSB 0x18 510#define QIB_7322_IntClear_SendDoneIntClear_0_RMASK 0x1 511#define QIB_7322_IntClear_SendBufAvailIntClear_LSB 0x17 512#define QIB_7322_IntClear_SendBufAvailIntClear_MSB 0x17 513#define QIB_7322_IntClear_SendBufAvailIntClear_RMASK 0x1 514#define QIB_7322_IntClear_RcvAvail17IntClear_LSB 0x11 515#define QIB_7322_IntClear_RcvAvail17IntClear_MSB 0x11 516#define QIB_7322_IntClear_RcvAvail17IntClear_RMASK 0x1 517#define QIB_7322_IntClear_RcvAvail16IntClear_LSB 0x10 518#define QIB_7322_IntClear_RcvAvail16IntClear_MSB 0x10 519#define QIB_7322_IntClear_RcvAvail16IntClear_RMASK 0x1 520#define QIB_7322_IntClear_RcvAvail15IntClear_LSB 0xF 521#define QIB_7322_IntClear_RcvAvail15IntClear_MSB 0xF 522#define QIB_7322_IntClear_RcvAvail15IntClear_RMASK 0x1 523#define QIB_7322_IntClear_RcvAvail14IntClear_LSB 0xE 524#define QIB_7322_IntClear_RcvAvail14IntClear_MSB 0xE 525#define QIB_7322_IntClear_RcvAvail14IntClear_RMASK 0x1 526#define QIB_7322_IntClear_RcvAvail13IntClear_LSB 0xD 527#define QIB_7322_IntClear_RcvAvail13IntClear_MSB 0xD 528#define QIB_7322_IntClear_RcvAvail13IntClear_RMASK 0x1 529#define QIB_7322_IntClear_RcvAvail12IntClear_LSB 0xC 530#define QIB_7322_IntClear_RcvAvail12IntClear_MSB 0xC 531#define QIB_7322_IntClear_RcvAvail12IntClear_RMASK 0x1 532#define QIB_7322_IntClear_RcvAvail11IntClear_LSB 0xB 533#define QIB_7322_IntClear_RcvAvail11IntClear_MSB 0xB 534#define QIB_7322_IntClear_RcvAvail11IntClear_RMASK 0x1 535#define QIB_7322_IntClear_RcvAvail10IntClear_LSB 0xA 536#define QIB_7322_IntClear_RcvAvail10IntClear_MSB 0xA 537#define QIB_7322_IntClear_RcvAvail10IntClear_RMASK 0x1 538#define QIB_7322_IntClear_RcvAvail9IntClear_LSB 0x9 539#define QIB_7322_IntClear_RcvAvail9IntClear_MSB 0x9 540#define QIB_7322_IntClear_RcvAvail9IntClear_RMASK 0x1 541#define QIB_7322_IntClear_RcvAvail8IntClear_LSB 0x8 542#define QIB_7322_IntClear_RcvAvail8IntClear_MSB 0x8 543#define QIB_7322_IntClear_RcvAvail8IntClear_RMASK 0x1 544#define QIB_7322_IntClear_RcvAvail7IntClear_LSB 0x7 545#define QIB_7322_IntClear_RcvAvail7IntClear_MSB 0x7 546#define QIB_7322_IntClear_RcvAvail7IntClear_RMASK 0x1 547#define QIB_7322_IntClear_RcvAvail6IntClear_LSB 0x6 548#define QIB_7322_IntClear_RcvAvail6IntClear_MSB 0x6 549#define QIB_7322_IntClear_RcvAvail6IntClear_RMASK 0x1 550#define QIB_7322_IntClear_RcvAvail5IntClear_LSB 0x5 551#define QIB_7322_IntClear_RcvAvail5IntClear_MSB 0x5 552#define QIB_7322_IntClear_RcvAvail5IntClear_RMASK 0x1 553#define QIB_7322_IntClear_RcvAvail4IntClear_LSB 0x4 554#define QIB_7322_IntClear_RcvAvail4IntClear_MSB 0x4 555#define QIB_7322_IntClear_RcvAvail4IntClear_RMASK 0x1 556#define QIB_7322_IntClear_RcvAvail3IntClear_LSB 0x3 557#define QIB_7322_IntClear_RcvAvail3IntClear_MSB 0x3 558#define QIB_7322_IntClear_RcvAvail3IntClear_RMASK 0x1 559#define QIB_7322_IntClear_RcvAvail2IntClear_LSB 0x2 560#define QIB_7322_IntClear_RcvAvail2IntClear_MSB 0x2 561#define QIB_7322_IntClear_RcvAvail2IntClear_RMASK 0x1 562#define QIB_7322_IntClear_RcvAvail1IntClear_LSB 0x1 563#define QIB_7322_IntClear_RcvAvail1IntClear_MSB 0x1 564#define QIB_7322_IntClear_RcvAvail1IntClear_RMASK 0x1 565#define QIB_7322_IntClear_RcvAvail0IntClear_LSB 0x0 566#define QIB_7322_IntClear_RcvAvail0IntClear_MSB 0x0 567#define QIB_7322_IntClear_RcvAvail0IntClear_RMASK 0x1 568 569#define QIB_7322_ErrMask_OFFS 0x80 570#define QIB_7322_ErrMask_DEF 0x0000000000000000 571#define QIB_7322_ErrMask_ResetNegatedMask_LSB 0x3F 572#define QIB_7322_ErrMask_ResetNegatedMask_MSB 0x3F 573#define QIB_7322_ErrMask_ResetNegatedMask_RMASK 0x1 574#define QIB_7322_ErrMask_HardwareErrMask_LSB 0x3E 575#define QIB_7322_ErrMask_HardwareErrMask_MSB 0x3E 576#define QIB_7322_ErrMask_HardwareErrMask_RMASK 0x1 577#define QIB_7322_ErrMask_InvalidAddrErrMask_LSB 0x3D 578#define QIB_7322_ErrMask_InvalidAddrErrMask_MSB 0x3D 579#define QIB_7322_ErrMask_InvalidAddrErrMask_RMASK 0x1 580#define QIB_7322_ErrMask_SDmaVL15ErrMask_LSB 0x38 581#define QIB_7322_ErrMask_SDmaVL15ErrMask_MSB 0x38 582#define QIB_7322_ErrMask_SDmaVL15ErrMask_RMASK 0x1 583#define QIB_7322_ErrMask_SBufVL15MisUseErrMask_LSB 0x37 584#define QIB_7322_ErrMask_SBufVL15MisUseErrMask_MSB 0x37 585#define QIB_7322_ErrMask_SBufVL15MisUseErrMask_RMASK 0x1 586#define QIB_7322_ErrMask_InvalidEEPCmdMask_LSB 0x35 587#define QIB_7322_ErrMask_InvalidEEPCmdMask_MSB 0x35 588#define QIB_7322_ErrMask_InvalidEEPCmdMask_RMASK 0x1 589#define QIB_7322_ErrMask_RcvContextShareErrMask_LSB 0x34 590#define QIB_7322_ErrMask_RcvContextShareErrMask_MSB 0x34 591#define QIB_7322_ErrMask_RcvContextShareErrMask_RMASK 0x1 592#define QIB_7322_ErrMask_SendVLMismatchErrMask_LSB 0x24 593#define QIB_7322_ErrMask_SendVLMismatchErrMask_MSB 0x24 594#define QIB_7322_ErrMask_SendVLMismatchErrMask_RMASK 0x1 595#define QIB_7322_ErrMask_SendArmLaunchErrMask_LSB 0x23 596#define QIB_7322_ErrMask_SendArmLaunchErrMask_MSB 0x23 597#define QIB_7322_ErrMask_SendArmLaunchErrMask_RMASK 0x1 598#define QIB_7322_ErrMask_SendSpecialTriggerErrMask_LSB 0x1B 599#define QIB_7322_ErrMask_SendSpecialTriggerErrMask_MSB 0x1B 600#define QIB_7322_ErrMask_SendSpecialTriggerErrMask_RMASK 0x1 601#define QIB_7322_ErrMask_SDmaWrongPortErrMask_LSB 0x1A 602#define QIB_7322_ErrMask_SDmaWrongPortErrMask_MSB 0x1A 603#define QIB_7322_ErrMask_SDmaWrongPortErrMask_RMASK 0x1 604#define QIB_7322_ErrMask_SDmaBufMaskDuplicateErrMask_LSB 0x19 605#define QIB_7322_ErrMask_SDmaBufMaskDuplicateErrMask_MSB 0x19 606#define QIB_7322_ErrMask_SDmaBufMaskDuplicateErrMask_RMASK 0x1 607#define QIB_7322_ErrMask_RcvHdrFullErrMask_LSB 0xD 608#define QIB_7322_ErrMask_RcvHdrFullErrMask_MSB 0xD 609#define QIB_7322_ErrMask_RcvHdrFullErrMask_RMASK 0x1 610#define QIB_7322_ErrMask_RcvEgrFullErrMask_LSB 0xC 611#define QIB_7322_ErrMask_RcvEgrFullErrMask_MSB 0xC 612#define QIB_7322_ErrMask_RcvEgrFullErrMask_RMASK 0x1 613 614#define QIB_7322_ErrStatus_OFFS 0x88 615#define QIB_7322_ErrStatus_DEF 0x0000000000000000 616#define QIB_7322_ErrStatus_ResetNegated_LSB 0x3F 617#define QIB_7322_ErrStatus_ResetNegated_MSB 0x3F 618#define QIB_7322_ErrStatus_ResetNegated_RMASK 0x1 619#define QIB_7322_ErrStatus_HardwareErr_LSB 0x3E 620#define QIB_7322_ErrStatus_HardwareErr_MSB 0x3E 621#define QIB_7322_ErrStatus_HardwareErr_RMASK 0x1 622#define QIB_7322_ErrStatus_InvalidAddrErr_LSB 0x3D 623#define QIB_7322_ErrStatus_InvalidAddrErr_MSB 0x3D 624#define QIB_7322_ErrStatus_InvalidAddrErr_RMASK 0x1 625#define QIB_7322_ErrStatus_SDmaVL15Err_LSB 0x38 626#define QIB_7322_ErrStatus_SDmaVL15Err_MSB 0x38 627#define QIB_7322_ErrStatus_SDmaVL15Err_RMASK 0x1 628#define QIB_7322_ErrStatus_SBufVL15MisUseErr_LSB 0x37 629#define QIB_7322_ErrStatus_SBufVL15MisUseErr_MSB 0x37 630#define QIB_7322_ErrStatus_SBufVL15MisUseErr_RMASK 0x1 631#define QIB_7322_ErrStatus_InvalidEEPCmdErr_LSB 0x35 632#define QIB_7322_ErrStatus_InvalidEEPCmdErr_MSB 0x35 633#define QIB_7322_ErrStatus_InvalidEEPCmdErr_RMASK 0x1 634#define QIB_7322_ErrStatus_RcvContextShareErr_LSB 0x34 635#define QIB_7322_ErrStatus_RcvContextShareErr_MSB 0x34 636#define QIB_7322_ErrStatus_RcvContextShareErr_RMASK 0x1 637#define QIB_7322_ErrStatus_SendVLMismatchErr_LSB 0x24 638#define QIB_7322_ErrStatus_SendVLMismatchErr_MSB 0x24 639#define QIB_7322_ErrStatus_SendVLMismatchErr_RMASK 0x1 640#define QIB_7322_ErrStatus_SendArmLaunchErr_LSB 0x23 641#define QIB_7322_ErrStatus_SendArmLaunchErr_MSB 0x23 642#define QIB_7322_ErrStatus_SendArmLaunchErr_RMASK 0x1 643#define QIB_7322_ErrStatus_SendSpecialTriggerErr_LSB 0x1B 644#define QIB_7322_ErrStatus_SendSpecialTriggerErr_MSB 0x1B 645#define QIB_7322_ErrStatus_SendSpecialTriggerErr_RMASK 0x1 646#define QIB_7322_ErrStatus_SDmaWrongPortErr_LSB 0x1A 647#define QIB_7322_ErrStatus_SDmaWrongPortErr_MSB 0x1A 648#define QIB_7322_ErrStatus_SDmaWrongPortErr_RMASK 0x1 649#define QIB_7322_ErrStatus_SDmaBufMaskDuplicateErr_LSB 0x19 650#define QIB_7322_ErrStatus_SDmaBufMaskDuplicateErr_MSB 0x19 651#define QIB_7322_ErrStatus_SDmaBufMaskDuplicateErr_RMASK 0x1 652#define QIB_7322_ErrStatus_RcvHdrFullErr_LSB 0xD 653#define QIB_7322_ErrStatus_RcvHdrFullErr_MSB 0xD 654#define QIB_7322_ErrStatus_RcvHdrFullErr_RMASK 0x1 655#define QIB_7322_ErrStatus_RcvEgrFullErr_LSB 0xC 656#define QIB_7322_ErrStatus_RcvEgrFullErr_MSB 0xC 657#define QIB_7322_ErrStatus_RcvEgrFullErr_RMASK 0x1 658 659#define QIB_7322_ErrClear_OFFS 0x90 660#define QIB_7322_ErrClear_DEF 0x0000000000000000 661#define QIB_7322_ErrClear_ResetNegatedClear_LSB 0x3F 662#define QIB_7322_ErrClear_ResetNegatedClear_MSB 0x3F 663#define QIB_7322_ErrClear_ResetNegatedClear_RMASK 0x1 664#define QIB_7322_ErrClear_HardwareErrClear_LSB 0x3E 665#define QIB_7322_ErrClear_HardwareErrClear_MSB 0x3E 666#define QIB_7322_ErrClear_HardwareErrClear_RMASK 0x1 667#define QIB_7322_ErrClear_InvalidAddrErrClear_LSB 0x3D 668#define QIB_7322_ErrClear_InvalidAddrErrClear_MSB 0x3D 669#define QIB_7322_ErrClear_InvalidAddrErrClear_RMASK 0x1 670#define QIB_7322_ErrClear_SDmaVL15ErrClear_LSB 0x38 671#define QIB_7322_ErrClear_SDmaVL15ErrClear_MSB 0x38 672#define QIB_7322_ErrClear_SDmaVL15ErrClear_RMASK 0x1 673#define QIB_7322_ErrClear_SBufVL15MisUseErrClear_LSB 0x37 674#define QIB_7322_ErrClear_SBufVL15MisUseErrClear_MSB 0x37 675#define QIB_7322_ErrClear_SBufVL15MisUseErrClear_RMASK 0x1 676#define QIB_7322_ErrClear_InvalidEEPCmdErrClear_LSB 0x35 677#define QIB_7322_ErrClear_InvalidEEPCmdErrClear_MSB 0x35 678#define QIB_7322_ErrClear_InvalidEEPCmdErrClear_RMASK 0x1 679#define QIB_7322_ErrClear_RcvContextShareErrClear_LSB 0x34 680#define QIB_7322_ErrClear_RcvContextShareErrClear_MSB 0x34 681#define QIB_7322_ErrClear_RcvContextShareErrClear_RMASK 0x1 682#define QIB_7322_ErrClear_SendVLMismatchErrMask_LSB 0x24 683#define QIB_7322_ErrClear_SendVLMismatchErrMask_MSB 0x24 684#define QIB_7322_ErrClear_SendVLMismatchErrMask_RMASK 0x1 685#define QIB_7322_ErrClear_SendArmLaunchErrClear_LSB 0x23 686#define QIB_7322_ErrClear_SendArmLaunchErrClear_MSB 0x23 687#define QIB_7322_ErrClear_SendArmLaunchErrClear_RMASK 0x1 688#define QIB_7322_ErrClear_SendSpecialTriggerErrClear_LSB 0x1B 689#define QIB_7322_ErrClear_SendSpecialTriggerErrClear_MSB 0x1B 690#define QIB_7322_ErrClear_SendSpecialTriggerErrClear_RMASK 0x1 691#define QIB_7322_ErrClear_SDmaWrongPortErrClear_LSB 0x1A 692#define QIB_7322_ErrClear_SDmaWrongPortErrClear_MSB 0x1A 693#define QIB_7322_ErrClear_SDmaWrongPortErrClear_RMASK 0x1 694#define QIB_7322_ErrClear_SDmaBufMaskDuplicateErrClear_LSB 0x19 695#define QIB_7322_ErrClear_SDmaBufMaskDuplicateErrClear_MSB 0x19 696#define QIB_7322_ErrClear_SDmaBufMaskDuplicateErrClear_RMASK 0x1 697#define QIB_7322_ErrClear_RcvHdrFullErrClear_LSB 0xD 698#define QIB_7322_ErrClear_RcvHdrFullErrClear_MSB 0xD 699#define QIB_7322_ErrClear_RcvHdrFullErrClear_RMASK 0x1 700#define QIB_7322_ErrClear_RcvEgrFullErrClear_LSB 0xC 701#define QIB_7322_ErrClear_RcvEgrFullErrClear_MSB 0xC 702#define QIB_7322_ErrClear_RcvEgrFullErrClear_RMASK 0x1 703 704#define QIB_7322_HwErrMask_OFFS 0x98 705#define QIB_7322_HwErrMask_DEF 0x0000000000000000 706#define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_1_LSB 0x3F 707#define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_1_MSB 0x3F 708#define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_1_RMASK 0x1 709#define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_0_LSB 0x3E 710#define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_0_MSB 0x3E 711#define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_0_RMASK 0x1 712#define QIB_7322_HwErrMask_PCIESerdesPClkNotDetectMask_LSB 0x37 713#define QIB_7322_HwErrMask_PCIESerdesPClkNotDetectMask_MSB 0x37 714#define QIB_7322_HwErrMask_PCIESerdesPClkNotDetectMask_RMASK 0x1 715#define QIB_7322_HwErrMask_PowerOnBISTFailedMask_LSB 0x36 716#define QIB_7322_HwErrMask_PowerOnBISTFailedMask_MSB 0x36 717#define QIB_7322_HwErrMask_PowerOnBISTFailedMask_RMASK 0x1 718#define QIB_7322_HwErrMask_TempsenseTholdReachedMask_LSB 0x35 719#define QIB_7322_HwErrMask_TempsenseTholdReachedMask_MSB 0x35 720#define QIB_7322_HwErrMask_TempsenseTholdReachedMask_RMASK 0x1 721#define QIB_7322_HwErrMask_MemoryErrMask_LSB 0x30 722#define QIB_7322_HwErrMask_MemoryErrMask_MSB 0x30 723#define QIB_7322_HwErrMask_MemoryErrMask_RMASK 0x1 724#define QIB_7322_HwErrMask_pcie_phy_txParityErr_LSB 0x22 725#define QIB_7322_HwErrMask_pcie_phy_txParityErr_MSB 0x22 726#define QIB_7322_HwErrMask_pcie_phy_txParityErr_RMASK 0x1 727#define QIB_7322_HwErrMask_PCIeBusParityErrMask_LSB 0x1F 728#define QIB_7322_HwErrMask_PCIeBusParityErrMask_MSB 0x21 729#define QIB_7322_HwErrMask_PCIeBusParityErrMask_RMASK 0x7 730#define QIB_7322_HwErrMask_PcieCplTimeoutMask_LSB 0x1E 731#define QIB_7322_HwErrMask_PcieCplTimeoutMask_MSB 0x1E 732#define QIB_7322_HwErrMask_PcieCplTimeoutMask_RMASK 0x1 733#define QIB_7322_HwErrMask_PciePoisonedTLPMask_LSB 0x1D 734#define QIB_7322_HwErrMask_PciePoisonedTLPMask_MSB 0x1D 735#define QIB_7322_HwErrMask_PciePoisonedTLPMask_RMASK 0x1 736#define QIB_7322_HwErrMask_SDmaMemReadErrMask_1_LSB 0x1C 737#define QIB_7322_HwErrMask_SDmaMemReadErrMask_1_MSB 0x1C 738#define QIB_7322_HwErrMask_SDmaMemReadErrMask_1_RMASK 0x1 739#define QIB_7322_HwErrMask_SDmaMemReadErrMask_0_LSB 0x1B 740#define QIB_7322_HwErrMask_SDmaMemReadErrMask_0_MSB 0x1B 741#define QIB_7322_HwErrMask_SDmaMemReadErrMask_0_RMASK 0x1 742#define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_1_LSB 0xF 743#define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_1_MSB 0xF 744#define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_1_RMASK 0x1 745#define QIB_7322_HwErrMask_IBCBusToSPCParityErrMask_1_LSB 0xE 746#define QIB_7322_HwErrMask_IBCBusToSPCParityErrMask_1_MSB 0xE 747#define QIB_7322_HwErrMask_IBCBusToSPCParityErrMask_1_RMASK 0x1 748#define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_0_LSB 0xD 749#define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_0_MSB 0xD 750#define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_0_RMASK 0x1 751#define QIB_7322_HwErrMask_statusValidNoEopMask_LSB 0xC 752#define QIB_7322_HwErrMask_statusValidNoEopMask_MSB 0xC 753#define QIB_7322_HwErrMask_statusValidNoEopMask_RMASK 0x1 754#define QIB_7322_HwErrMask_LATriggeredMask_LSB 0xB 755#define QIB_7322_HwErrMask_LATriggeredMask_MSB 0xB 756#define QIB_7322_HwErrMask_LATriggeredMask_RMASK 0x1 757 758#define QIB_7322_HwErrStatus_OFFS 0xA0 759#define QIB_7322_HwErrStatus_DEF 0x0000000000000000 760#define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_1_LSB 0x3F 761#define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_1_MSB 0x3F 762#define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_1_RMASK 0x1 763#define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_0_LSB 0x3E 764#define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_0_MSB 0x3E 765#define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_0_RMASK 0x1 766#define QIB_7322_HwErrStatus_PCIESerdesPClkNotDetect_LSB 0x37 767#define QIB_7322_HwErrStatus_PCIESerdesPClkNotDetect_MSB 0x37 768#define QIB_7322_HwErrStatus_PCIESerdesPClkNotDetect_RMASK 0x1 769#define QIB_7322_HwErrStatus_PowerOnBISTFailed_LSB 0x36 770#define QIB_7322_HwErrStatus_PowerOnBISTFailed_MSB 0x36 771#define QIB_7322_HwErrStatus_PowerOnBISTFailed_RMASK 0x1 772#define QIB_7322_HwErrStatus_TempsenseTholdReached_LSB 0x35 773#define QIB_7322_HwErrStatus_TempsenseTholdReached_MSB 0x35 774#define QIB_7322_HwErrStatus_TempsenseTholdReached_RMASK 0x1 775#define QIB_7322_HwErrStatus_MemoryErr_LSB 0x30 776#define QIB_7322_HwErrStatus_MemoryErr_MSB 0x30 777#define QIB_7322_HwErrStatus_MemoryErr_RMASK 0x1 778#define QIB_7322_HwErrStatus_pcie_phy_txParityErr_LSB 0x22 779#define QIB_7322_HwErrStatus_pcie_phy_txParityErr_MSB 0x22 780#define QIB_7322_HwErrStatus_pcie_phy_txParityErr_RMASK 0x1 781#define QIB_7322_HwErrStatus_PCIeBusParity_LSB 0x1F 782#define QIB_7322_HwErrStatus_PCIeBusParity_MSB 0x21 783#define QIB_7322_HwErrStatus_PCIeBusParity_RMASK 0x7 784#define QIB_7322_HwErrStatus_PcieCplTimeout_LSB 0x1E 785#define QIB_7322_HwErrStatus_PcieCplTimeout_MSB 0x1E 786#define QIB_7322_HwErrStatus_PcieCplTimeout_RMASK 0x1 787#define QIB_7322_HwErrStatus_PciePoisonedTLP_LSB 0x1D 788#define QIB_7322_HwErrStatus_PciePoisonedTLP_MSB 0x1D 789#define QIB_7322_HwErrStatus_PciePoisonedTLP_RMASK 0x1 790#define QIB_7322_HwErrStatus_SDmaMemReadErr_1_LSB 0x1C 791#define QIB_7322_HwErrStatus_SDmaMemReadErr_1_MSB 0x1C 792#define QIB_7322_HwErrStatus_SDmaMemReadErr_1_RMASK 0x1 793#define QIB_7322_HwErrStatus_SDmaMemReadErr_0_LSB 0x1B 794#define QIB_7322_HwErrStatus_SDmaMemReadErr_0_MSB 0x1B 795#define QIB_7322_HwErrStatus_SDmaMemReadErr_0_RMASK 0x1 796#define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_1_LSB 0xF 797#define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_1_MSB 0xF 798#define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_1_RMASK 0x1 799#define QIB_7322_HwErrStatus_IBCBusToSPCParityErr_1_LSB 0xE 800#define QIB_7322_HwErrStatus_IBCBusToSPCParityErr_1_MSB 0xE 801#define QIB_7322_HwErrStatus_IBCBusToSPCParityErr_1_RMASK 0x1 802#define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_0_LSB 0xD 803#define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_0_MSB 0xD 804#define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_0_RMASK 0x1 805#define QIB_7322_HwErrStatus_statusValidNoEop_LSB 0xC 806#define QIB_7322_HwErrStatus_statusValidNoEop_MSB 0xC 807#define QIB_7322_HwErrStatus_statusValidNoEop_RMASK 0x1 808#define QIB_7322_HwErrStatus_LATriggered_LSB 0xB 809#define QIB_7322_HwErrStatus_LATriggered_MSB 0xB 810#define QIB_7322_HwErrStatus_LATriggered_RMASK 0x1 811 812#define QIB_7322_HwErrClear_OFFS 0xA8 813#define QIB_7322_HwErrClear_DEF 0x0000000000000000 814#define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_1_LSB 0x3F 815#define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_1_MSB 0x3F 816#define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_1_RMASK 0x1 817#define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_0_LSB 0x3E 818#define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_0_MSB 0x3E 819#define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_0_RMASK 0x1 820#define QIB_7322_HwErrClear_PCIESerdesPClkNotDetectClear_LSB 0x37 821#define QIB_7322_HwErrClear_PCIESerdesPClkNotDetectClear_MSB 0x37 822#define QIB_7322_HwErrClear_PCIESerdesPClkNotDetectClear_RMASK 0x1 823#define QIB_7322_HwErrClear_PowerOnBISTFailedClear_LSB 0x36 824#define QIB_7322_HwErrClear_PowerOnBISTFailedClear_MSB 0x36 825#define QIB_7322_HwErrClear_PowerOnBISTFailedClear_RMASK 0x1 826#define QIB_7322_HwErrClear_TempsenseTholdReachedClear_LSB 0x35 827#define QIB_7322_HwErrClear_TempsenseTholdReachedClear_MSB 0x35 828#define QIB_7322_HwErrClear_TempsenseTholdReachedClear_RMASK 0x1 829#define QIB_7322_HwErrClear_MemoryErrClear_LSB 0x30 830#define QIB_7322_HwErrClear_MemoryErrClear_MSB 0x30 831#define QIB_7322_HwErrClear_MemoryErrClear_RMASK 0x1 832#define QIB_7322_HwErrClear_pcie_phy_txParityErr_LSB 0x22 833#define QIB_7322_HwErrClear_pcie_phy_txParityErr_MSB 0x22 834#define QIB_7322_HwErrClear_pcie_phy_txParityErr_RMASK 0x1 835#define QIB_7322_HwErrClear_PCIeBusParityClear_LSB 0x1F 836#define QIB_7322_HwErrClear_PCIeBusParityClear_MSB 0x21 837#define QIB_7322_HwErrClear_PCIeBusParityClear_RMASK 0x7 838#define QIB_7322_HwErrClear_PcieCplTimeoutClear_LSB 0x1E 839#define QIB_7322_HwErrClear_PcieCplTimeoutClear_MSB 0x1E 840#define QIB_7322_HwErrClear_PcieCplTimeoutClear_RMASK 0x1 841#define QIB_7322_HwErrClear_PciePoisonedTLPClear_LSB 0x1D 842#define QIB_7322_HwErrClear_PciePoisonedTLPClear_MSB 0x1D 843#define QIB_7322_HwErrClear_PciePoisonedTLPClear_RMASK 0x1 844#define QIB_7322_HwErrClear_SDmaMemReadErrClear_1_LSB 0x1C 845#define QIB_7322_HwErrClear_SDmaMemReadErrClear_1_MSB 0x1C 846#define QIB_7322_HwErrClear_SDmaMemReadErrClear_1_RMASK 0x1 847#define QIB_7322_HwErrClear_SDmaMemReadErrClear_0_LSB 0x1B 848#define QIB_7322_HwErrClear_SDmaMemReadErrClear_0_MSB 0x1B 849#define QIB_7322_HwErrClear_SDmaMemReadErrClear_0_RMASK 0x1 850#define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_1_LSB 0xF 851#define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_1_MSB 0xF 852#define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_1_RMASK 0x1 853#define QIB_7322_HwErrClear_IBCBusToSPCParityErrClear_1_LSB 0xE 854#define QIB_7322_HwErrClear_IBCBusToSPCParityErrClear_1_MSB 0xE 855#define QIB_7322_HwErrClear_IBCBusToSPCParityErrClear_1_RMASK 0x1 856#define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_0_LSB 0xD 857#define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_0_MSB 0xD 858#define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_0_RMASK 0x1 859#define QIB_7322_HwErrClear_statusValidNoEopClear_LSB 0xC 860#define QIB_7322_HwErrClear_statusValidNoEopClear_MSB 0xC 861#define QIB_7322_HwErrClear_statusValidNoEopClear_RMASK 0x1 862#define QIB_7322_HwErrClear_LATriggeredClear_LSB 0xB 863#define QIB_7322_HwErrClear_LATriggeredClear_MSB 0xB 864#define QIB_7322_HwErrClear_LATriggeredClear_RMASK 0x1 865 866#define QIB_7322_HwDiagCtrl_OFFS 0xB0 867#define QIB_7322_HwDiagCtrl_DEF 0x0000000000000000 868#define QIB_7322_HwDiagCtrl_Diagnostic_LSB 0x3F 869#define QIB_7322_HwDiagCtrl_Diagnostic_MSB 0x3F 870#define QIB_7322_HwDiagCtrl_Diagnostic_RMASK 0x1 871#define QIB_7322_HwDiagCtrl_CounterWrEnable_LSB 0x3D 872#define QIB_7322_HwDiagCtrl_CounterWrEnable_MSB 0x3D 873#define QIB_7322_HwDiagCtrl_CounterWrEnable_RMASK 0x1 874#define QIB_7322_HwDiagCtrl_CounterDisable_LSB 0x3C 875#define QIB_7322_HwDiagCtrl_CounterDisable_MSB 0x3C 876#define QIB_7322_HwDiagCtrl_CounterDisable_RMASK 0x1 877#define QIB_7322_HwDiagCtrl_forcePCIeBusParity_LSB 0x1F 878#define QIB_7322_HwDiagCtrl_forcePCIeBusParity_MSB 0x22 879#define QIB_7322_HwDiagCtrl_forcePCIeBusParity_RMASK 0xF 880#define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_1_LSB 0xF 881#define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_1_MSB 0xF 882#define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_1_RMASK 0x1 883#define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_1_LSB 0xE 884#define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_1_MSB 0xE 885#define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_1_RMASK 0x1 886#define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_0_LSB 0xD 887#define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_0_MSB 0xD 888#define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_0_RMASK 0x1 889#define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_0_LSB 0xC 890#define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_0_MSB 0xC 891#define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_0_RMASK 0x1 892 893#define QIB_7322_EXTStatus_OFFS 0xC0 894#define QIB_7322_EXTStatus_DEF 0x000000000000X000 895#define QIB_7322_EXTStatus_GPIOIn_LSB 0x30 896#define QIB_7322_EXTStatus_GPIOIn_MSB 0x3F 897#define QIB_7322_EXTStatus_GPIOIn_RMASK 0xFFFF 898#define QIB_7322_EXTStatus_MemBISTDisabled_LSB 0xF 899#define QIB_7322_EXTStatus_MemBISTDisabled_MSB 0xF 900#define QIB_7322_EXTStatus_MemBISTDisabled_RMASK 0x1 901#define QIB_7322_EXTStatus_MemBISTEndTest_LSB 0xE 902#define QIB_7322_EXTStatus_MemBISTEndTest_MSB 0xE 903#define QIB_7322_EXTStatus_MemBISTEndTest_RMASK 0x1 904 905#define QIB_7322_EXTCtrl_OFFS 0xC8 906#define QIB_7322_EXTCtrl_DEF 0x0000000000000000 907#define QIB_7322_EXTCtrl_GPIOOe_LSB 0x30 908#define QIB_7322_EXTCtrl_GPIOOe_MSB 0x3F 909#define QIB_7322_EXTCtrl_GPIOOe_RMASK 0xFFFF 910#define QIB_7322_EXTCtrl_GPIOInvert_LSB 0x20 911#define QIB_7322_EXTCtrl_GPIOInvert_MSB 0x2F 912#define QIB_7322_EXTCtrl_GPIOInvert_RMASK 0xFFFF 913#define QIB_7322_EXTCtrl_LEDPort1GreenOn_LSB 0x3 914#define QIB_7322_EXTCtrl_LEDPort1GreenOn_MSB 0x3 915#define QIB_7322_EXTCtrl_LEDPort1GreenOn_RMASK 0x1 916#define QIB_7322_EXTCtrl_LEDPort1YellowOn_LSB 0x2 917#define QIB_7322_EXTCtrl_LEDPort1YellowOn_MSB 0x2 918#define QIB_7322_EXTCtrl_LEDPort1YellowOn_RMASK 0x1 919#define QIB_7322_EXTCtrl_LEDPort0GreenOn_LSB 0x1 920#define QIB_7322_EXTCtrl_LEDPort0GreenOn_MSB 0x1 921#define QIB_7322_EXTCtrl_LEDPort0GreenOn_RMASK 0x1 922#define QIB_7322_EXTCtrl_LEDPort0YellowOn_LSB 0x0 923#define QIB_7322_EXTCtrl_LEDPort0YellowOn_MSB 0x0 924#define QIB_7322_EXTCtrl_LEDPort0YellowOn_RMASK 0x1 925 926#define QIB_7322_GPIOOut_OFFS 0xE0 927#define QIB_7322_GPIOOut_DEF 0x0000000000000000 928 929#define QIB_7322_GPIOMask_OFFS 0xE8 930#define QIB_7322_GPIOMask_DEF 0x0000000000000000 931 932#define QIB_7322_GPIOStatus_OFFS 0xF0 933#define QIB_7322_GPIOStatus_DEF 0x0000000000000000 934 935#define QIB_7322_GPIOClear_OFFS 0xF8 936#define QIB_7322_GPIOClear_DEF 0x0000000000000000 937 938#define QIB_7322_RcvCtrl_OFFS 0x100 939#define QIB_7322_RcvCtrl_DEF 0x0000000000000000 940#define QIB_7322_RcvCtrl_TidReDirect_LSB 0x30 941#define QIB_7322_RcvCtrl_TidReDirect_MSB 0x3F 942#define QIB_7322_RcvCtrl_TidReDirect_RMASK 0xFFFF 943#define QIB_7322_RcvCtrl_TailUpd_LSB 0x2F 944#define QIB_7322_RcvCtrl_TailUpd_MSB 0x2F 945#define QIB_7322_RcvCtrl_TailUpd_RMASK 0x1 946#define QIB_7322_RcvCtrl_XrcTypeCode_LSB 0x2C 947#define QIB_7322_RcvCtrl_XrcTypeCode_MSB 0x2E 948#define QIB_7322_RcvCtrl_XrcTypeCode_RMASK 0x7 949#define QIB_7322_RcvCtrl_TidFlowEnable_LSB 0x2B 950#define QIB_7322_RcvCtrl_TidFlowEnable_MSB 0x2B 951#define QIB_7322_RcvCtrl_TidFlowEnable_RMASK 0x1 952#define QIB_7322_RcvCtrl_ContextCfg_LSB 0x29 953#define QIB_7322_RcvCtrl_ContextCfg_MSB 0x2A 954#define QIB_7322_RcvCtrl_ContextCfg_RMASK 0x3 955#define QIB_7322_RcvCtrl_IntrAvail_LSB 0x14 956#define QIB_7322_RcvCtrl_IntrAvail_MSB 0x25 957#define QIB_7322_RcvCtrl_IntrAvail_RMASK 0x3FFFF 958#define QIB_7322_RcvCtrl_dontDropRHQFull_LSB 0x0 959#define QIB_7322_RcvCtrl_dontDropRHQFull_MSB 0x11 960#define QIB_7322_RcvCtrl_dontDropRHQFull_RMASK 0x3FFFF 961 962#define QIB_7322_RcvHdrSize_OFFS 0x110 963#define QIB_7322_RcvHdrSize_DEF 0x0000000000000000 964 965#define QIB_7322_RcvHdrCnt_OFFS 0x118 966#define QIB_7322_RcvHdrCnt_DEF 0x0000000000000000 967 968#define QIB_7322_RcvHdrEntSize_OFFS 0x120 969#define QIB_7322_RcvHdrEntSize_DEF 0x0000000000000000 970 971#define QIB_7322_RcvTIDBase_OFFS 0x128 972#define QIB_7322_RcvTIDBase_DEF 0x0000000000050000 973 974#define QIB_7322_RcvTIDCnt_OFFS 0x130 975#define QIB_7322_RcvTIDCnt_DEF 0x0000000000000200 976 977#define QIB_7322_RcvEgrBase_OFFS 0x138 978#define QIB_7322_RcvEgrBase_DEF 0x0000000000014000 979 980#define QIB_7322_RcvEgrCnt_OFFS 0x140 981#define QIB_7322_RcvEgrCnt_DEF 0x0000000000001000 982 983#define QIB_7322_RcvBufBase_OFFS 0x148 984#define QIB_7322_RcvBufBase_DEF 0x0000000000080000 985 986#define QIB_7322_RcvBufSize_OFFS 0x150 987#define QIB_7322_RcvBufSize_DEF 0x0000000000005000 988 989#define QIB_7322_RxIntMemBase_OFFS 0x158 990#define QIB_7322_RxIntMemBase_DEF 0x0000000000077000 991 992#define QIB_7322_RxIntMemSize_OFFS 0x160 993#define QIB_7322_RxIntMemSize_DEF 0x0000000000007000 994 995#define QIB_7322_feature_mask_OFFS 0x190 996#define QIB_7322_feature_mask_DEF 0x00000000000000XX 997 998#define QIB_7322_active_feature_mask_OFFS 0x198 999#define QIB_7322_active_feature_mask_DEF 0x00000000000000XX 1000#define QIB_7322_active_feature_mask_Port1_QDR_Enabled_LSB 0x5 1001#define QIB_7322_active_feature_mask_Port1_QDR_Enabled_MSB 0x5 1002#define QIB_7322_active_feature_mask_Port1_QDR_Enabled_RMASK 0x1 1003#define QIB_7322_active_feature_mask_Port1_DDR_Enabled_LSB 0x4 1004#define QIB_7322_active_feature_mask_Port1_DDR_Enabled_MSB 0x4 1005#define QIB_7322_active_feature_mask_Port1_DDR_Enabled_RMASK 0x1 1006#define QIB_7322_active_feature_mask_Port1_SDR_Enabled_LSB 0x3 1007#define QIB_7322_active_feature_mask_Port1_SDR_Enabled_MSB 0x3 1008#define QIB_7322_active_feature_mask_Port1_SDR_Enabled_RMASK 0x1 1009#define QIB_7322_active_feature_mask_Port0_QDR_Enabled_LSB 0x2 1010#define QIB_7322_active_feature_mask_Port0_QDR_Enabled_MSB 0x2 1011#define QIB_7322_active_feature_mask_Port0_QDR_Enabled_RMASK 0x1 1012#define QIB_7322_active_feature_mask_Port0_DDR_Enabled_LSB 0x1 1013#define QIB_7322_active_feature_mask_Port0_DDR_Enabled_MSB 0x1 1014#define QIB_7322_active_feature_mask_Port0_DDR_Enabled_RMASK 0x1 1015#define QIB_7322_active_feature_mask_Port0_SDR_Enabled_LSB 0x0 1016#define QIB_7322_active_feature_mask_Port0_SDR_Enabled_MSB 0x0 1017#define QIB_7322_active_feature_mask_Port0_SDR_Enabled_RMASK 0x1 1018 1019#define QIB_7322_SendCtrl_OFFS 0x1C0 1020#define QIB_7322_SendCtrl_DEF 0x0000000000000000 1021#define QIB_7322_SendCtrl_Disarm_LSB 0x1F 1022#define QIB_7322_SendCtrl_Disarm_MSB 0x1F 1023#define QIB_7322_SendCtrl_Disarm_RMASK 0x1 1024#define QIB_7322_SendCtrl_SendBufAvailPad64Byte_LSB 0x1D 1025#define QIB_7322_SendCtrl_SendBufAvailPad64Byte_MSB 0x1D 1026#define QIB_7322_SendCtrl_SendBufAvailPad64Byte_RMASK 0x1 1027#define QIB_7322_SendCtrl_AvailUpdThld_LSB 0x18 1028#define QIB_7322_SendCtrl_AvailUpdThld_MSB 0x1C 1029#define QIB_7322_SendCtrl_AvailUpdThld_RMASK 0x1F 1030#define QIB_7322_SendCtrl_DisarmSendBuf_LSB 0x10 1031#define QIB_7322_SendCtrl_DisarmSendBuf_MSB 0x17 1032#define QIB_7322_SendCtrl_DisarmSendBuf_RMASK 0xFF 1033#define QIB_7322_SendCtrl_SpecialTriggerEn_LSB 0x4 1034#define QIB_7322_SendCtrl_SpecialTriggerEn_MSB 0x4 1035#define QIB_7322_SendCtrl_SpecialTriggerEn_RMASK 0x1 1036#define QIB_7322_SendCtrl_SendBufAvailUpd_LSB 0x2 1037#define QIB_7322_SendCtrl_SendBufAvailUpd_MSB 0x2 1038#define QIB_7322_SendCtrl_SendBufAvailUpd_RMASK 0x1 1039#define QIB_7322_SendCtrl_SendIntBufAvail_LSB 0x1 1040#define QIB_7322_SendCtrl_SendIntBufAvail_MSB 0x1 1041#define QIB_7322_SendCtrl_SendIntBufAvail_RMASK 0x1 1042 1043#define QIB_7322_SendBufBase_OFFS 0x1C8 1044#define QIB_7322_SendBufBase_DEF 0x0018000000100000 1045#define QIB_7322_SendBufBase_BaseAddr_LargePIO_LSB 0x20 1046#define QIB_7322_SendBufBase_BaseAddr_LargePIO_MSB 0x34 1047#define QIB_7322_SendBufBase_BaseAddr_LargePIO_RMASK 0x1FFFFF 1048#define QIB_7322_SendBufBase_BaseAddr_SmallPIO_LSB 0x0 1049#define QIB_7322_SendBufBase_BaseAddr_SmallPIO_MSB 0x14 1050#define QIB_7322_SendBufBase_BaseAddr_SmallPIO_RMASK 0x1FFFFF 1051 1052#define QIB_7322_SendBufSize_OFFS 0x1D0 1053#define QIB_7322_SendBufSize_DEF 0x0000108000000880 1054#define QIB_7322_SendBufSize_Size_LargePIO_LSB 0x20 1055#define QIB_7322_SendBufSize_Size_LargePIO_MSB 0x2C 1056#define QIB_7322_SendBufSize_Size_LargePIO_RMASK 0x1FFF 1057#define QIB_7322_SendBufSize_Size_SmallPIO_LSB 0x0 1058#define QIB_7322_SendBufSize_Size_SmallPIO_MSB 0xB 1059#define QIB_7322_SendBufSize_Size_SmallPIO_RMASK 0xFFF 1060 1061#define QIB_7322_SendBufCnt_OFFS 0x1D8 1062#define QIB_7322_SendBufCnt_DEF 0x0000002000000080 1063#define QIB_7322_SendBufCnt_Num_LargeBuffers_LSB 0x20 1064#define QIB_7322_SendBufCnt_Num_LargeBuffers_MSB 0x25 1065#define QIB_7322_SendBufCnt_Num_LargeBuffers_RMASK 0x3F 1066#define QIB_7322_SendBufCnt_Num_SmallBuffers_LSB 0x0 1067#define QIB_7322_SendBufCnt_Num_SmallBuffers_MSB 0x8 1068#define QIB_7322_SendBufCnt_Num_SmallBuffers_RMASK 0x1FF 1069 1070#define QIB_7322_SendBufAvailAddr_OFFS 0x1E0 1071#define QIB_7322_SendBufAvailAddr_DEF 0x0000000000000000 1072#define QIB_7322_SendBufAvailAddr_SendBufAvailAddr_LSB 0x6 1073#define QIB_7322_SendBufAvailAddr_SendBufAvailAddr_MSB 0x27 1074#define QIB_7322_SendBufAvailAddr_SendBufAvailAddr_RMASK 0x3FFFFFFFF 1075 1076#define QIB_7322_SendBufErr0_OFFS 0x240 1077#define QIB_7322_SendBufErr0_DEF 0x0000000000000000 1078#define QIB_7322_SendBufErr0_SendBufErr_63_0_LSB 0x0 1079#define QIB_7322_SendBufErr0_SendBufErr_63_0_MSB 0x3F 1080#define QIB_7322_SendBufErr0_SendBufErr_63_0_RMASK 0x0 1081 1082#define QIB_7322_AvailUpdCount_OFFS 0x268 1083#define QIB_7322_AvailUpdCount_DEF 0x0000000000000000 1084#define QIB_7322_AvailUpdCount_AvailUpdCount_LSB 0x0 1085#define QIB_7322_AvailUpdCount_AvailUpdCount_MSB 0x4 1086#define QIB_7322_AvailUpdCount_AvailUpdCount_RMASK 0x1F 1087 1088#define QIB_7322_RcvHdrAddr0_OFFS 0x280 1089#define QIB_7322_RcvHdrAddr0_DEF 0x0000000000000000 1090#define QIB_7322_RcvHdrAddr0_RcvHdrAddr_LSB 0x2 1091#define QIB_7322_RcvHdrAddr0_RcvHdrAddr_MSB 0x27 1092#define QIB_7322_RcvHdrAddr0_RcvHdrAddr_RMASK 0x3FFFFFFFFF 1093 1094#define QIB_7322_RcvHdrTailAddr0_OFFS 0x340 1095#define QIB_7322_RcvHdrTailAddr0_DEF 0x0000000000000000 1096#define QIB_7322_RcvHdrTailAddr0_RcvHdrTailAddr_LSB 0x2 1097#define QIB_7322_RcvHdrTailAddr0_RcvHdrTailAddr_MSB 0x27 1098#define QIB_7322_RcvHdrTailAddr0_RcvHdrTailAddr_RMASK 0x3FFFFFFFFF 1099 1100#define QIB_7322_ahb_access_ctrl_OFFS 0x460 1101#define QIB_7322_ahb_access_ctrl_DEF 0x0000000000000000 1102#define QIB_7322_ahb_access_ctrl_sw_sel_ahb_trgt_LSB 0x1 1103#define QIB_7322_ahb_access_ctrl_sw_sel_ahb_trgt_MSB 0x2 1104#define QIB_7322_ahb_access_ctrl_sw_sel_ahb_trgt_RMASK 0x3 1105#define QIB_7322_ahb_access_ctrl_sw_ahb_sel_LSB 0x0 1106#define QIB_7322_ahb_access_ctrl_sw_ahb_sel_MSB 0x0 1107#define QIB_7322_ahb_access_ctrl_sw_ahb_sel_RMASK 0x1 1108 1109#define QIB_7322_ahb_transaction_reg_OFFS 0x468 1110#define QIB_7322_ahb_transaction_reg_DEF 0x0000000080000000 1111#define QIB_7322_ahb_transaction_reg_ahb_data_LSB 0x20 1112#define QIB_7322_ahb_transaction_reg_ahb_data_MSB 0x3F 1113#define QIB_7322_ahb_transaction_reg_ahb_data_RMASK 0xFFFFFFFF 1114#define QIB_7322_ahb_transaction_reg_ahb_rdy_LSB 0x1F 1115#define QIB_7322_ahb_transaction_reg_ahb_rdy_MSB 0x1F 1116#define QIB_7322_ahb_transaction_reg_ahb_rdy_RMASK 0x1 1117#define QIB_7322_ahb_transaction_reg_ahb_req_err_LSB 0x1E 1118#define QIB_7322_ahb_transaction_reg_ahb_req_err_MSB 0x1E 1119#define QIB_7322_ahb_transaction_reg_ahb_req_err_RMASK 0x1 1120#define QIB_7322_ahb_transaction_reg_write_not_read_LSB 0x1B 1121#define QIB_7322_ahb_transaction_reg_write_not_read_MSB 0x1B 1122#define QIB_7322_ahb_transaction_reg_write_not_read_RMASK 0x1 1123#define QIB_7322_ahb_transaction_reg_ahb_address_LSB 0x10 1124#define QIB_7322_ahb_transaction_reg_ahb_address_MSB 0x1A 1125#define QIB_7322_ahb_transaction_reg_ahb_address_RMASK 0x7FF 1126 1127#define QIB_7322_SPC_JTAG_ACCESS_REG_OFFS 0x470 1128#define QIB_7322_SPC_JTAG_ACCESS_REG_DEF 0x0000000000000001 1129#define QIB_7322_SPC_JTAG_ACCESS_REG_SPC_JTAG_ACCESS_EN_LSB 0xA 1130#define QIB_7322_SPC_JTAG_ACCESS_REG_SPC_JTAG_ACCESS_EN_MSB 0xA 1131#define QIB_7322_SPC_JTAG_ACCESS_REG_SPC_JTAG_ACCESS_EN_RMASK 0x1 1132#define QIB_7322_SPC_JTAG_ACCESS_REG_bist_en_LSB 0x5 1133#define QIB_7322_SPC_JTAG_ACCESS_REG_bist_en_MSB 0x9 1134#define QIB_7322_SPC_JTAG_ACCESS_REG_bist_en_RMASK 0x1F 1135#define QIB_7322_SPC_JTAG_ACCESS_REG_opcode_LSB 0x3 1136#define QIB_7322_SPC_JTAG_ACCESS_REG_opcode_MSB 0x4 1137#define QIB_7322_SPC_JTAG_ACCESS_REG_opcode_RMASK 0x3 1138#define QIB_7322_SPC_JTAG_ACCESS_REG_tdi_LSB 0x2 1139#define QIB_7322_SPC_JTAG_ACCESS_REG_tdi_MSB 0x2 1140#define QIB_7322_SPC_JTAG_ACCESS_REG_tdi_RMASK 0x1 1141#define QIB_7322_SPC_JTAG_ACCESS_REG_tdo_LSB 0x1 1142#define QIB_7322_SPC_JTAG_ACCESS_REG_tdo_MSB 0x1 1143#define QIB_7322_SPC_JTAG_ACCESS_REG_tdo_RMASK 0x1 1144#define QIB_7322_SPC_JTAG_ACCESS_REG_rdy_LSB 0x0 1145#define QIB_7322_SPC_JTAG_ACCESS_REG_rdy_MSB 0x0 1146#define QIB_7322_SPC_JTAG_ACCESS_REG_rdy_RMASK 0x1 1147 1148#define QIB_7322_SendCheckMask0_OFFS 0x4C0 1149#define QIB_7322_SendCheckMask0_DEF 0x0000000000000000 1150#define QIB_7322_SendCheckMask0_SendCheckMask_63_32_LSB 0x0 1151#define QIB_7322_SendCheckMask0_SendCheckMask_63_32_MSB 0x3F 1152#define QIB_7322_SendCheckMask0_SendCheckMask_63_32_RMASK 0x0 1153 1154#define QIB_7322_SendGRHCheckMask0_OFFS 0x4E0 1155#define QIB_7322_SendGRHCheckMask0_DEF 0x0000000000000000 1156#define QIB_7322_SendGRHCheckMask0_SendGRHCheckMask_63_32_LSB 0x0 1157#define QIB_7322_SendGRHCheckMask0_SendGRHCheckMask_63_32_MSB 0x3F 1158#define QIB_7322_SendGRHCheckMask0_SendGRHCheckMask_63_32_RMASK 0x0 1159 1160#define QIB_7322_SendIBPacketMask0_OFFS 0x500 1161#define QIB_7322_SendIBPacketMask0_DEF 0x0000000000000000 1162#define QIB_7322_SendIBPacketMask0_SendIBPacketMask_63_32_LSB 0x0 1163#define QIB_7322_SendIBPacketMask0_SendIBPacketMask_63_32_MSB 0x3F 1164#define QIB_7322_SendIBPacketMask0_SendIBPacketMask_63_32_RMASK 0x0 1165 1166#define QIB_7322_IntRedirect0_OFFS 0x540 1167#define QIB_7322_IntRedirect0_DEF 0x0000000000000000 1168#define QIB_7322_IntRedirect0_vec11_LSB 0x37 1169#define QIB_7322_IntRedirect0_vec11_MSB 0x3B 1170#define QIB_7322_IntRedirect0_vec11_RMASK 0x1F 1171#define QIB_7322_IntRedirect0_vec10_LSB 0x32 1172#define QIB_7322_IntRedirect0_vec10_MSB 0x36 1173#define QIB_7322_IntRedirect0_vec10_RMASK 0x1F 1174#define QIB_7322_IntRedirect0_vec9_LSB 0x2D 1175#define QIB_7322_IntRedirect0_vec9_MSB 0x31 1176#define QIB_7322_IntRedirect0_vec9_RMASK 0x1F 1177#define QIB_7322_IntRedirect0_vec8_LSB 0x28 1178#define QIB_7322_IntRedirect0_vec8_MSB 0x2C 1179#define QIB_7322_IntRedirect0_vec8_RMASK 0x1F 1180#define QIB_7322_IntRedirect0_vec7_LSB 0x23 1181#define QIB_7322_IntRedirect0_vec7_MSB 0x27 1182#define QIB_7322_IntRedirect0_vec7_RMASK 0x1F 1183#define QIB_7322_IntRedirect0_vec6_LSB 0x1E 1184#define QIB_7322_IntRedirect0_vec6_MSB 0x22 1185#define QIB_7322_IntRedirect0_vec6_RMASK 0x1F 1186#define QIB_7322_IntRedirect0_vec5_LSB 0x19 1187#define QIB_7322_IntRedirect0_vec5_MSB 0x1D 1188#define QIB_7322_IntRedirect0_vec5_RMASK 0x1F 1189#define QIB_7322_IntRedirect0_vec4_LSB 0x14 1190#define QIB_7322_IntRedirect0_vec4_MSB 0x18 1191#define QIB_7322_IntRedirect0_vec4_RMASK 0x1F 1192#define QIB_7322_IntRedirect0_vec3_LSB 0xF 1193#define QIB_7322_IntRedirect0_vec3_MSB 0x13 1194#define QIB_7322_IntRedirect0_vec3_RMASK 0x1F 1195#define QIB_7322_IntRedirect0_vec2_LSB 0xA 1196#define QIB_7322_IntRedirect0_vec2_MSB 0xE 1197#define QIB_7322_IntRedirect0_vec2_RMASK 0x1F 1198#define QIB_7322_IntRedirect0_vec1_LSB 0x5 1199#define QIB_7322_IntRedirect0_vec1_MSB 0x9 1200#define QIB_7322_IntRedirect0_vec1_RMASK 0x1F 1201#define QIB_7322_IntRedirect0_vec0_LSB 0x0 1202#define QIB_7322_IntRedirect0_vec0_MSB 0x4 1203#define QIB_7322_IntRedirect0_vec0_RMASK 0x1F 1204 1205#define QIB_7322_Int_Granted_OFFS 0x570 1206#define QIB_7322_Int_Granted_DEF 0x0000000000000000 1207 1208#define QIB_7322_vec_clr_without_int_OFFS 0x578 1209#define QIB_7322_vec_clr_without_int_DEF 0x0000000000000000 1210 1211#define QIB_7322_DCACtrlA_OFFS 0x580 1212#define QIB_7322_DCACtrlA_DEF 0x0000000000000000 1213#define QIB_7322_DCACtrlA_SendDMAHead1DCAEnable_LSB 0x4 1214#define QIB_7322_DCACtrlA_SendDMAHead1DCAEnable_MSB 0x4 1215#define QIB_7322_DCACtrlA_SendDMAHead1DCAEnable_RMASK 0x1 1216#define QIB_7322_DCACtrlA_SendDMAHead0DCAEnable_LSB 0x3 1217#define QIB_7322_DCACtrlA_SendDMAHead0DCAEnable_MSB 0x3 1218#define QIB_7322_DCACtrlA_SendDMAHead0DCAEnable_RMASK 0x1 1219#define QIB_7322_DCACtrlA_RcvTailUpdDCAEnable_LSB 0x2 1220#define QIB_7322_DCACtrlA_RcvTailUpdDCAEnable_MSB 0x2 1221#define QIB_7322_DCACtrlA_RcvTailUpdDCAEnable_RMASK 0x1 1222#define QIB_7322_DCACtrlA_EagerDCAEnable_LSB 0x1 1223#define QIB_7322_DCACtrlA_EagerDCAEnable_MSB 0x1 1224#define QIB_7322_DCACtrlA_EagerDCAEnable_RMASK 0x1 1225#define QIB_7322_DCACtrlA_RcvHdrqDCAEnable_LSB 0x0 1226#define QIB_7322_DCACtrlA_RcvHdrqDCAEnable_MSB 0x0 1227#define QIB_7322_DCACtrlA_RcvHdrqDCAEnable_RMASK 0x1 1228 1229#define QIB_7322_DCACtrlB_OFFS 0x588 1230#define QIB_7322_DCACtrlB_DEF 0x0000000000000000 1231#define QIB_7322_DCACtrlB_RcvHdrq3DCAXfrCnt_LSB 0x36 1232#define QIB_7322_DCACtrlB_RcvHdrq3DCAXfrCnt_MSB 0x3B 1233#define QIB_7322_DCACtrlB_RcvHdrq3DCAXfrCnt_RMASK 0x3F 1234#define QIB_7322_DCACtrlB_RcvHdrq3DCAOPH_LSB 0x2E 1235#define QIB_7322_DCACtrlB_RcvHdrq3DCAOPH_MSB 0x35 1236#define QIB_7322_DCACtrlB_RcvHdrq3DCAOPH_RMASK 0xFF 1237#define QIB_7322_DCACtrlB_RcvHdrq2DCAXfrCnt_LSB 0x28 1238#define QIB_7322_DCACtrlB_RcvHdrq2DCAXfrCnt_MSB 0x2D 1239#define QIB_7322_DCACtrlB_RcvHdrq2DCAXfrCnt_RMASK 0x3F 1240#define QIB_7322_DCACtrlB_RcvHdrq2DCAOPH_LSB 0x20 1241#define QIB_7322_DCACtrlB_RcvHdrq2DCAOPH_MSB 0x27 1242#define QIB_7322_DCACtrlB_RcvHdrq2DCAOPH_RMASK 0xFF 1243#define QIB_7322_DCACtrlB_RcvHdrq1DCAXfrCnt_LSB 0x16 1244#define QIB_7322_DCACtrlB_RcvHdrq1DCAXfrCnt_MSB 0x1B 1245#define QIB_7322_DCACtrlB_RcvHdrq1DCAXfrCnt_RMASK 0x3F 1246#define QIB_7322_DCACtrlB_RcvHdrq1DCAOPH_LSB 0xE 1247#define QIB_7322_DCACtrlB_RcvHdrq1DCAOPH_MSB 0x15 1248#define QIB_7322_DCACtrlB_RcvHdrq1DCAOPH_RMASK 0xFF 1249#define QIB_7322_DCACtrlB_RcvHdrq0DCAXfrCnt_LSB 0x8 1250#define QIB_7322_DCACtrlB_RcvHdrq0DCAXfrCnt_MSB 0xD 1251#define QIB_7322_DCACtrlB_RcvHdrq0DCAXfrCnt_RMASK 0x3F 1252#define QIB_7322_DCACtrlB_RcvHdrq0DCAOPH_LSB 0x0 1253#define QIB_7322_DCACtrlB_RcvHdrq0DCAOPH_MSB 0x7 1254#define QIB_7322_DCACtrlB_RcvHdrq0DCAOPH_RMASK 0xFF 1255 1256#define QIB_7322_DCACtrlC_OFFS 0x590 1257#define QIB_7322_DCACtrlC_DEF 0x0000000000000000 1258#define QIB_7322_DCACtrlC_RcvHdrq7DCAXfrCnt_LSB 0x36 1259#define QIB_7322_DCACtrlC_RcvHdrq7DCAXfrCnt_MSB 0x3B 1260#define QIB_7322_DCACtrlC_RcvHdrq7DCAXfrCnt_RMASK 0x3F 1261#define QIB_7322_DCACtrlC_RcvHdrq7DCAOPH_LSB 0x2E 1262#define QIB_7322_DCACtrlC_RcvHdrq7DCAOPH_MSB 0x35 1263#define QIB_7322_DCACtrlC_RcvHdrq7DCAOPH_RMASK 0xFF 1264#define QIB_7322_DCACtrlC_RcvHdrq6DCAXfrCnt_LSB 0x28 1265#define QIB_7322_DCACtrlC_RcvHdrq6DCAXfrCnt_MSB 0x2D 1266#define QIB_7322_DCACtrlC_RcvHdrq6DCAXfrCnt_RMASK 0x3F 1267#define QIB_7322_DCACtrlC_RcvHdrq6DCAOPH_LSB 0x20 1268#define QIB_7322_DCACtrlC_RcvHdrq6DCAOPH_MSB 0x27 1269#define QIB_7322_DCACtrlC_RcvHdrq6DCAOPH_RMASK 0xFF 1270#define QIB_7322_DCACtrlC_RcvHdrq5DCAXfrCnt_LSB 0x16 1271#define QIB_7322_DCACtrlC_RcvHdrq5DCAXfrCnt_MSB 0x1B 1272#define QIB_7322_DCACtrlC_RcvHdrq5DCAXfrCnt_RMASK 0x3F 1273#define QIB_7322_DCACtrlC_RcvHdrq5DCAOPH_LSB 0xE 1274#define QIB_7322_DCACtrlC_RcvHdrq5DCAOPH_MSB 0x15 1275#define QIB_7322_DCACtrlC_RcvHdrq5DCAOPH_RMASK 0xFF 1276#define QIB_7322_DCACtrlC_RcvHdrq4DCAXfrCnt_LSB 0x8 1277#define QIB_7322_DCACtrlC_RcvHdrq4DCAXfrCnt_MSB 0xD 1278#define QIB_7322_DCACtrlC_RcvHdrq4DCAXfrCnt_RMASK 0x3F 1279#define QIB_7322_DCACtrlC_RcvHdrq4DCAOPH_LSB 0x0 1280#define QIB_7322_DCACtrlC_RcvHdrq4DCAOPH_MSB 0x7 1281#define QIB_7322_DCACtrlC_RcvHdrq4DCAOPH_RMASK 0xFF 1282 1283#define QIB_7322_DCACtrlD_OFFS 0x598 1284#define QIB_7322_DCACtrlD_DEF 0x0000000000000000 1285#define QIB_7322_DCACtrlD_RcvHdrq11DCAXfrCnt_LSB 0x36 1286#define QIB_7322_DCACtrlD_RcvHdrq11DCAXfrCnt_MSB 0x3B 1287#define QIB_7322_DCACtrlD_RcvHdrq11DCAXfrCnt_RMASK 0x3F 1288#define QIB_7322_DCACtrlD_RcvHdrq11DCAOPH_LSB 0x2E 1289#define QIB_7322_DCACtrlD_RcvHdrq11DCAOPH_MSB 0x35 1290#define QIB_7322_DCACtrlD_RcvHdrq11DCAOPH_RMASK 0xFF 1291#define QIB_7322_DCACtrlD_RcvHdrq10DCAXfrCnt_LSB 0x28 1292#define QIB_7322_DCACtrlD_RcvHdrq10DCAXfrCnt_MSB 0x2D 1293#define QIB_7322_DCACtrlD_RcvHdrq10DCAXfrCnt_RMASK 0x3F 1294#define QIB_7322_DCACtrlD_RcvHdrq10DCAOPH_LSB 0x20 1295#define QIB_7322_DCACtrlD_RcvHdrq10DCAOPH_MSB 0x27 1296#define QIB_7322_DCACtrlD_RcvHdrq10DCAOPH_RMASK 0xFF 1297#define QIB_7322_DCACtrlD_RcvHdrq9DCAXfrCnt_LSB 0x16 1298#define QIB_7322_DCACtrlD_RcvHdrq9DCAXfrCnt_MSB 0x1B 1299#define QIB_7322_DCACtrlD_RcvHdrq9DCAXfrCnt_RMASK 0x3F 1300#define QIB_7322_DCACtrlD_RcvHdrq9DCAOPH_LSB 0xE 1301#define QIB_7322_DCACtrlD_RcvHdrq9DCAOPH_MSB 0x15 1302#define QIB_7322_DCACtrlD_RcvHdrq9DCAOPH_RMASK 0xFF 1303#define QIB_7322_DCACtrlD_RcvHdrq8DCAXfrCnt_LSB 0x8 1304#define QIB_7322_DCACtrlD_RcvHdrq8DCAXfrCnt_MSB 0xD 1305#define QIB_7322_DCACtrlD_RcvHdrq8DCAXfrCnt_RMASK 0x3F 1306#define QIB_7322_DCACtrlD_RcvHdrq8DCAOPH_LSB 0x0 1307#define QIB_7322_DCACtrlD_RcvHdrq8DCAOPH_MSB 0x7 1308#define QIB_7322_DCACtrlD_RcvHdrq8DCAOPH_RMASK 0xFF 1309 1310#define QIB_7322_DCACtrlE_OFFS 0x5A0 1311#define QIB_7322_DCACtrlE_DEF 0x0000000000000000 1312#define QIB_7322_DCACtrlE_RcvHdrq15DCAXfrCnt_LSB 0x36 1313#define QIB_7322_DCACtrlE_RcvHdrq15DCAXfrCnt_MSB 0x3B 1314#define QIB_7322_DCACtrlE_RcvHdrq15DCAXfrCnt_RMASK 0x3F 1315#define QIB_7322_DCACtrlE_RcvHdrq15DCAOPH_LSB 0x2E 1316#define QIB_7322_DCACtrlE_RcvHdrq15DCAOPH_MSB 0x35 1317#define QIB_7322_DCACtrlE_RcvHdrq15DCAOPH_RMASK 0xFF 1318#define QIB_7322_DCACtrlE_RcvHdrq14DCAXfrCnt_LSB 0x28 1319#define QIB_7322_DCACtrlE_RcvHdrq14DCAXfrCnt_MSB 0x2D 1320#define QIB_7322_DCACtrlE_RcvHdrq14DCAXfrCnt_RMASK 0x3F 1321#define QIB_7322_DCACtrlE_RcvHdrq14DCAOPH_LSB 0x20 1322#define QIB_7322_DCACtrlE_RcvHdrq14DCAOPH_MSB 0x27 1323#define QIB_7322_DCACtrlE_RcvHdrq14DCAOPH_RMASK 0xFF 1324#define QIB_7322_DCACtrlE_RcvHdrq13DCAXfrCnt_LSB 0x16 1325#define QIB_7322_DCACtrlE_RcvHdrq13DCAXfrCnt_MSB 0x1B 1326#define QIB_7322_DCACtrlE_RcvHdrq13DCAXfrCnt_RMASK 0x3F 1327#define QIB_7322_DCACtrlE_RcvHdrq13DCAOPH_LSB 0xE 1328#define QIB_7322_DCACtrlE_RcvHdrq13DCAOPH_MSB 0x15 1329#define QIB_7322_DCACtrlE_RcvHdrq13DCAOPH_RMASK 0xFF 1330#define QIB_7322_DCACtrlE_RcvHdrq12DCAXfrCnt_LSB 0x8 1331#define QIB_7322_DCACtrlE_RcvHdrq12DCAXfrCnt_MSB 0xD 1332#define QIB_7322_DCACtrlE_RcvHdrq12DCAXfrCnt_RMASK 0x3F 1333#define QIB_7322_DCACtrlE_RcvHdrq12DCAOPH_LSB 0x0 1334#define QIB_7322_DCACtrlE_RcvHdrq12DCAOPH_MSB 0x7 1335#define QIB_7322_DCACtrlE_RcvHdrq12DCAOPH_RMASK 0xFF 1336 1337#define QIB_7322_DCACtrlF_OFFS 0x5A8 1338#define QIB_7322_DCACtrlF_DEF 0x0000000000000000 1339#define QIB_7322_DCACtrlF_SendDma1DCAOPH_LSB 0x28 1340#define QIB_7322_DCACtrlF_SendDma1DCAOPH_MSB 0x2F 1341#define QIB_7322_DCACtrlF_SendDma1DCAOPH_RMASK 0xFF 1342#define QIB_7322_DCACtrlF_SendDma0DCAOPH_LSB 0x20 1343#define QIB_7322_DCACtrlF_SendDma0DCAOPH_MSB 0x27 1344#define QIB_7322_DCACtrlF_SendDma0DCAOPH_RMASK 0xFF 1345#define QIB_7322_DCACtrlF_RcvHdrq17DCAXfrCnt_LSB 0x16 1346#define QIB_7322_DCACtrlF_RcvHdrq17DCAXfrCnt_MSB 0x1B 1347#define QIB_7322_DCACtrlF_RcvHdrq17DCAXfrCnt_RMASK 0x3F 1348#define QIB_7322_DCACtrlF_RcvHdrq17DCAOPH_LSB 0xE 1349#define QIB_7322_DCACtrlF_RcvHdrq17DCAOPH_MSB 0x15 1350#define QIB_7322_DCACtrlF_RcvHdrq17DCAOPH_RMASK 0xFF 1351#define QIB_7322_DCACtrlF_RcvHdrq16DCAXfrCnt_LSB 0x8 1352#define QIB_7322_DCACtrlF_RcvHdrq16DCAXfrCnt_MSB 0xD 1353#define QIB_7322_DCACtrlF_RcvHdrq16DCAXfrCnt_RMASK 0x3F 1354#define QIB_7322_DCACtrlF_RcvHdrq16DCAOPH_LSB 0x0 1355#define QIB_7322_DCACtrlF_RcvHdrq16DCAOPH_MSB 0x7 1356#define QIB_7322_DCACtrlF_RcvHdrq16DCAOPH_RMASK 0xFF 1357 1358#define QIB_7322_RcvAvailTimeOut0_OFFS 0xC00 1359#define QIB_7322_RcvAvailTimeOut0_DEF 0x0000000000000000 1360#define QIB_7322_RcvAvailTimeOut0_RcvAvailTOCount_LSB 0x10 1361#define QIB_7322_RcvAvailTimeOut0_RcvAvailTOCount_MSB 0x1F 1362#define QIB_7322_RcvAvailTimeOut0_RcvAvailTOCount_RMASK 0xFFFF 1363#define QIB_7322_RcvAvailTimeOut0_RcvAvailTOReload_LSB 0x0 1364#define QIB_7322_RcvAvailTimeOut0_RcvAvailTOReload_MSB 0xF 1365#define QIB_7322_RcvAvailTimeOut0_RcvAvailTOReload_RMASK 0xFFFF 1366 1367#define QIB_7322_CntrRegBase_0_OFFS 0x1028 1368#define QIB_7322_CntrRegBase_0_DEF 0x0000000000012000 1369 1370#define QIB_7322_ErrMask_0_OFFS 0x1080 1371#define QIB_7322_ErrMask_0_DEF 0x0000000000000000 1372#define QIB_7322_ErrMask_0_IBStatusChangedMask_LSB 0x3A 1373#define QIB_7322_ErrMask_0_IBStatusChangedMask_MSB 0x3A 1374#define QIB_7322_ErrMask_0_IBStatusChangedMask_RMASK 0x1 1375#define QIB_7322_ErrMask_0_SHeadersErrMask_LSB 0x39 1376#define QIB_7322_ErrMask_0_SHeadersErrMask_MSB 0x39 1377#define QIB_7322_ErrMask_0_SHeadersErrMask_RMASK 0x1 1378#define QIB_7322_ErrMask_0_VL15BufMisuseErrMask_LSB 0x36 1379#define QIB_7322_ErrMask_0_VL15BufMisuseErrMask_MSB 0x36 1380#define QIB_7322_ErrMask_0_VL15BufMisuseErrMask_RMASK 0x1 1381#define QIB_7322_ErrMask_0_SDmaHaltErrMask_LSB 0x31 1382#define QIB_7322_ErrMask_0_SDmaHaltErrMask_MSB 0x31 1383#define QIB_7322_ErrMask_0_SDmaHaltErrMask_RMASK 0x1 1384#define QIB_7322_ErrMask_0_SDmaDescAddrMisalignErrMask_LSB 0x30 1385#define QIB_7322_ErrMask_0_SDmaDescAddrMisalignErrMask_MSB 0x30 1386#define QIB_7322_ErrMask_0_SDmaDescAddrMisalignErrMask_RMASK 0x1 1387#define QIB_7322_ErrMask_0_SDmaUnexpDataErrMask_LSB 0x2F 1388#define QIB_7322_ErrMask_0_SDmaUnexpDataErrMask_MSB 0x2F 1389#define QIB_7322_ErrMask_0_SDmaUnexpDataErrMask_RMASK 0x1 1390#define QIB_7322_ErrMask_0_SDmaMissingDwErrMask_LSB 0x2E 1391#define QIB_7322_ErrMask_0_SDmaMissingDwErrMask_MSB 0x2E 1392#define QIB_7322_ErrMask_0_SDmaMissingDwErrMask_RMASK 0x1 1393#define QIB_7322_ErrMask_0_SDmaDwEnErrMask_LSB 0x2D 1394#define QIB_7322_ErrMask_0_SDmaDwEnErrMask_MSB 0x2D 1395#define QIB_7322_ErrMask_0_SDmaDwEnErrMask_RMASK 0x1 1396#define QIB_7322_ErrMask_0_SDmaRpyTagErrMask_LSB 0x2C 1397#define QIB_7322_ErrMask_0_SDmaRpyTagErrMask_MSB 0x2C 1398#define QIB_7322_ErrMask_0_SDmaRpyTagErrMask_RMASK 0x1 1399#define QIB_7322_ErrMask_0_SDma1stDescErrMask_LSB 0x2B 1400#define QIB_7322_ErrMask_0_SDma1stDescErrMask_MSB 0x2B 1401#define QIB_7322_ErrMask_0_SDma1stDescErrMask_RMASK 0x1 1402#define QIB_7322_ErrMask_0_SDmaBaseErrMask_LSB 0x2A 1403#define QIB_7322_ErrMask_0_SDmaBaseErrMask_MSB 0x2A 1404#define QIB_7322_ErrMask_0_SDmaBaseErrMask_RMASK 0x1 1405#define QIB_7322_ErrMask_0_SDmaTailOutOfBoundErrMask_LSB 0x29 1406#define QIB_7322_ErrMask_0_SDmaTailOutOfBoundErrMask_MSB 0x29 1407#define QIB_7322_ErrMask_0_SDmaTailOutOfBoundErrMask_RMASK 0x1 1408#define QIB_7322_ErrMask_0_SDmaOutOfBoundErrMask_LSB 0x28 1409#define QIB_7322_ErrMask_0_SDmaOutOfBoundErrMask_MSB 0x28 1410#define QIB_7322_ErrMask_0_SDmaOutOfBoundErrMask_RMASK 0x1 1411#define QIB_7322_ErrMask_0_SDmaGenMismatchErrMask_LSB 0x27 1412#define QIB_7322_ErrMask_0_SDmaGenMismatchErrMask_MSB 0x27 1413#define QIB_7322_ErrMask_0_SDmaGenMismatchErrMask_RMASK 0x1 1414#define QIB_7322_ErrMask_0_SendBufMisuseErrMask_LSB 0x26 1415#define QIB_7322_ErrMask_0_SendBufMisuseErrMask_MSB 0x26 1416#define QIB_7322_ErrMask_0_SendBufMisuseErrMask_RMASK 0x1 1417#define QIB_7322_ErrMask_0_SendUnsupportedVLErrMask_LSB 0x25 1418#define QIB_7322_ErrMask_0_SendUnsupportedVLErrMask_MSB 0x25 1419#define QIB_7322_ErrMask_0_SendUnsupportedVLErrMask_RMASK 0x1 1420#define QIB_7322_ErrMask_0_SendUnexpectedPktNumErrMask_LSB 0x24 1421#define QIB_7322_ErrMask_0_SendUnexpectedPktNumErrMask_MSB 0x24 1422#define QIB_7322_ErrMask_0_SendUnexpectedPktNumErrMask_RMASK 0x1 1423#define QIB_7322_ErrMask_0_SendDroppedDataPktErrMask_LSB 0x22 1424#define QIB_7322_ErrMask_0_SendDroppedDataPktErrMask_MSB 0x22 1425#define QIB_7322_ErrMask_0_SendDroppedDataPktErrMask_RMASK 0x1 1426#define QIB_7322_ErrMask_0_SendDroppedSmpPktErrMask_LSB 0x21 1427#define QIB_7322_ErrMask_0_SendDroppedSmpPktErrMask_MSB 0x21 1428#define QIB_7322_ErrMask_0_SendDroppedSmpPktErrMask_RMASK 0x1 1429#define QIB_7322_ErrMask_0_SendPktLenErrMask_LSB 0x20 1430#define QIB_7322_ErrMask_0_SendPktLenErrMask_MSB 0x20 1431#define QIB_7322_ErrMask_0_SendPktLenErrMask_RMASK 0x1 1432#define QIB_7322_ErrMask_0_SendUnderRunErrMask_LSB 0x1F 1433#define QIB_7322_ErrMask_0_SendUnderRunErrMask_MSB 0x1F 1434#define QIB_7322_ErrMask_0_SendUnderRunErrMask_RMASK 0x1 1435#define QIB_7322_ErrMask_0_SendMaxPktLenErrMask_LSB 0x1E 1436#define QIB_7322_ErrMask_0_SendMaxPktLenErrMask_MSB 0x1E 1437#define QIB_7322_ErrMask_0_SendMaxPktLenErrMask_RMASK 0x1 1438#define QIB_7322_ErrMask_0_SendMinPktLenErrMask_LSB 0x1D 1439#define QIB_7322_ErrMask_0_SendMinPktLenErrMask_MSB 0x1D 1440#define QIB_7322_ErrMask_0_SendMinPktLenErrMask_RMASK 0x1 1441#define QIB_7322_ErrMask_0_RcvIBLostLinkErrMask_LSB 0x11 1442#define QIB_7322_ErrMask_0_RcvIBLostLinkErrMask_MSB 0x11 1443#define QIB_7322_ErrMask_0_RcvIBLostLinkErrMask_RMASK 0x1 1444#define QIB_7322_ErrMask_0_RcvHdrErrMask_LSB 0x10 1445#define QIB_7322_ErrMask_0_RcvHdrErrMask_MSB 0x10 1446#define QIB_7322_ErrMask_0_RcvHdrErrMask_RMASK 0x1 1447#define QIB_7322_ErrMask_0_RcvHdrLenErrMask_LSB 0xF 1448#define QIB_7322_ErrMask_0_RcvHdrLenErrMask_MSB 0xF 1449#define QIB_7322_ErrMask_0_RcvHdrLenErrMask_RMASK 0x1 1450#define QIB_7322_ErrMask_0_RcvBadTidErrMask_LSB 0xE 1451#define QIB_7322_ErrMask_0_RcvBadTidErrMask_MSB 0xE 1452#define QIB_7322_ErrMask_0_RcvBadTidErrMask_RMASK 0x1 1453#define QIB_7322_ErrMask_0_RcvBadVersionErrMask_LSB 0xB 1454#define QIB_7322_ErrMask_0_RcvBadVersionErrMask_MSB 0xB 1455#define QIB_7322_ErrMask_0_RcvBadVersionErrMask_RMASK 0x1 1456#define QIB_7322_ErrMask_0_RcvIBFlowErrMask_LSB 0xA 1457#define QIB_7322_ErrMask_0_RcvIBFlowErrMask_MSB 0xA 1458#define QIB_7322_ErrMask_0_RcvIBFlowErrMask_RMASK 0x1 1459#define QIB_7322_ErrMask_0_RcvEBPErrMask_LSB 0x9 1460#define QIB_7322_ErrMask_0_RcvEBPErrMask_MSB 0x9 1461#define QIB_7322_ErrMask_0_RcvEBPErrMask_RMASK 0x1 1462#define QIB_7322_ErrMask_0_RcvUnsupportedVLErrMask_LSB 0x8 1463#define QIB_7322_ErrMask_0_RcvUnsupportedVLErrMask_MSB 0x8 1464#define QIB_7322_ErrMask_0_RcvUnsupportedVLErrMask_RMASK 0x1 1465#define QIB_7322_ErrMask_0_RcvUnexpectedCharErrMask_LSB 0x7 1466#define QIB_7322_ErrMask_0_RcvUnexpectedCharErrMask_MSB 0x7 1467#define QIB_7322_ErrMask_0_RcvUnexpectedCharErrMask_RMASK 0x1 1468#define QIB_7322_ErrMask_0_RcvShortPktLenErrMask_LSB 0x6 1469#define QIB_7322_ErrMask_0_RcvShortPktLenErrMask_MSB 0x6 1470#define QIB_7322_ErrMask_0_RcvShortPktLenErrMask_RMASK 0x1 1471#define QIB_7322_ErrMask_0_RcvLongPktLenErrMask_LSB 0x5 1472#define QIB_7322_ErrMask_0_RcvLongPktLenErrMask_MSB 0x5 1473#define QIB_7322_ErrMask_0_RcvLongPktLenErrMask_RMASK 0x1 1474#define QIB_7322_ErrMask_0_RcvMaxPktLenErrMask_LSB 0x4 1475#define QIB_7322_ErrMask_0_RcvMaxPktLenErrMask_MSB 0x4 1476#define QIB_7322_ErrMask_0_RcvMaxPktLenErrMask_RMASK 0x1 1477#define QIB_7322_ErrMask_0_RcvMinPktLenErrMask_LSB 0x3 1478#define QIB_7322_ErrMask_0_RcvMinPktLenErrMask_MSB 0x3 1479#define QIB_7322_ErrMask_0_RcvMinPktLenErrMask_RMASK 0x1 1480#define QIB_7322_ErrMask_0_RcvICRCErrMask_LSB 0x2 1481#define QIB_7322_ErrMask_0_RcvICRCErrMask_MSB 0x2 1482#define QIB_7322_ErrMask_0_RcvICRCErrMask_RMASK 0x1 1483#define QIB_7322_ErrMask_0_RcvVCRCErrMask_LSB 0x1 1484#define QIB_7322_ErrMask_0_RcvVCRCErrMask_MSB 0x1 1485#define QIB_7322_ErrMask_0_RcvVCRCErrMask_RMASK 0x1 1486#define QIB_7322_ErrMask_0_RcvFormatErrMask_LSB 0x0 1487#define QIB_7322_ErrMask_0_RcvFormatErrMask_MSB 0x0 1488#define QIB_7322_ErrMask_0_RcvFormatErrMask_RMASK 0x1 1489 1490#define QIB_7322_ErrStatus_0_OFFS 0x1088 1491#define QIB_7322_ErrStatus_0_DEF 0x0000000000000000 1492#define QIB_7322_ErrStatus_0_IBStatusChanged_LSB 0x3A 1493#define QIB_7322_ErrStatus_0_IBStatusChanged_MSB 0x3A 1494#define QIB_7322_ErrStatus_0_IBStatusChanged_RMASK 0x1 1495#define QIB_7322_ErrStatus_0_SHeadersErr_LSB 0x39 1496#define QIB_7322_ErrStatus_0_SHeadersErr_MSB 0x39 1497#define QIB_7322_ErrStatus_0_SHeadersErr_RMASK 0x1 1498#define QIB_7322_ErrStatus_0_VL15BufMisuseErr_LSB 0x36 1499#define QIB_7322_ErrStatus_0_VL15BufMisuseErr_MSB 0x36 1500#define QIB_7322_ErrStatus_0_VL15BufMisuseErr_RMASK 0x1 1501#define QIB_7322_ErrStatus_0_SDmaHaltErr_LSB 0x31 1502#define QIB_7322_ErrStatus_0_SDmaHaltErr_MSB 0x31 1503#define QIB_7322_ErrStatus_0_SDmaHaltErr_RMASK 0x1 1504#define QIB_7322_ErrStatus_0_SDmaDescAddrMisalignErr_LSB 0x30 1505#define QIB_7322_ErrStatus_0_SDmaDescAddrMisalignErr_MSB 0x30 1506#define QIB_7322_ErrStatus_0_SDmaDescAddrMisalignErr_RMASK 0x1 1507#define QIB_7322_ErrStatus_0_SDmaUnexpDataErr_LSB 0x2F 1508#define QIB_7322_ErrStatus_0_SDmaUnexpDataErr_MSB 0x2F 1509#define QIB_7322_ErrStatus_0_SDmaUnexpDataErr_RMASK 0x1 1510#define QIB_7322_ErrStatus_0_SDmaMissingDwErr_LSB 0x2E 1511#define QIB_7322_ErrStatus_0_SDmaMissingDwErr_MSB 0x2E 1512#define QIB_7322_ErrStatus_0_SDmaMissingDwErr_RMASK 0x1 1513#define QIB_7322_ErrStatus_0_SDmaDwEnErr_LSB 0x2D 1514#define QIB_7322_ErrStatus_0_SDmaDwEnErr_MSB 0x2D 1515#define QIB_7322_ErrStatus_0_SDmaDwEnErr_RMASK 0x1 1516#define QIB_7322_ErrStatus_0_SDmaRpyTagErr_LSB 0x2C 1517#define QIB_7322_ErrStatus_0_SDmaRpyTagErr_MSB 0x2C 1518#define QIB_7322_ErrStatus_0_SDmaRpyTagErr_RMASK 0x1 1519#define QIB_7322_ErrStatus_0_SDma1stDescErr_LSB 0x2B 1520#define QIB_7322_ErrStatus_0_SDma1stDescErr_MSB 0x2B 1521#define QIB_7322_ErrStatus_0_SDma1stDescErr_RMASK 0x1 1522#define QIB_7322_ErrStatus_0_SDmaBaseErr_LSB 0x2A 1523#define QIB_7322_ErrStatus_0_SDmaBaseErr_MSB 0x2A 1524#define QIB_7322_ErrStatus_0_SDmaBaseErr_RMASK 0x1 1525#define QIB_7322_ErrStatus_0_SDmaTailOutOfBoundErr_LSB 0x29 1526#define QIB_7322_ErrStatus_0_SDmaTailOutOfBoundErr_MSB 0x29 1527#define QIB_7322_ErrStatus_0_SDmaTailOutOfBoundErr_RMASK 0x1 1528#define QIB_7322_ErrStatus_0_SDmaOutOfBoundErr_LSB 0x28 1529#define QIB_7322_ErrStatus_0_SDmaOutOfBoundErr_MSB 0x28 1530#define QIB_7322_ErrStatus_0_SDmaOutOfBoundErr_RMASK 0x1 1531#define QIB_7322_ErrStatus_0_SDmaGenMismatchErr_LSB 0x27 1532#define QIB_7322_ErrStatus_0_SDmaGenMismatchErr_MSB 0x27 1533#define QIB_7322_ErrStatus_0_SDmaGenMismatchErr_RMASK 0x1 1534#define QIB_7322_ErrStatus_0_SendBufMisuseErr_LSB 0x26 1535#define QIB_7322_ErrStatus_0_SendBufMisuseErr_MSB 0x26 1536#define QIB_7322_ErrStatus_0_SendBufMisuseErr_RMASK 0x1 1537#define QIB_7322_ErrStatus_0_SendUnsupportedVLErr_LSB 0x25 1538#define QIB_7322_ErrStatus_0_SendUnsupportedVLErr_MSB 0x25 1539#define QIB_7322_ErrStatus_0_SendUnsupportedVLErr_RMASK 0x1 1540#define QIB_7322_ErrStatus_0_SendUnexpectedPktNumErr_LSB 0x24 1541#define QIB_7322_ErrStatus_0_SendUnexpectedPktNumErr_MSB 0x24 1542#define QIB_7322_ErrStatus_0_SendUnexpectedPktNumErr_RMASK 0x1 1543#define QIB_7322_ErrStatus_0_SendDroppedDataPktErr_LSB 0x22 1544#define QIB_7322_ErrStatus_0_SendDroppedDataPktErr_MSB 0x22 1545#define QIB_7322_ErrStatus_0_SendDroppedDataPktErr_RMASK 0x1 1546#define QIB_7322_ErrStatus_0_SendDroppedSmpPktErr_LSB 0x21 1547#define QIB_7322_ErrStatus_0_SendDroppedSmpPktErr_MSB 0x21 1548#define QIB_7322_ErrStatus_0_SendDroppedSmpPktErr_RMASK 0x1 1549#define QIB_7322_ErrStatus_0_SendPktLenErr_LSB 0x20 1550#define QIB_7322_ErrStatus_0_SendPktLenErr_MSB 0x20 1551#define QIB_7322_ErrStatus_0_SendPktLenErr_RMASK 0x1 1552#define QIB_7322_ErrStatus_0_SendUnderRunErr_LSB 0x1F 1553#define QIB_7322_ErrStatus_0_SendUnderRunErr_MSB 0x1F 1554#define QIB_7322_ErrStatus_0_SendUnderRunErr_RMASK 0x1 1555#define QIB_7322_ErrStatus_0_SendMaxPktLenErr_LSB 0x1E 1556#define QIB_7322_ErrStatus_0_SendMaxPktLenErr_MSB 0x1E 1557#define QIB_7322_ErrStatus_0_SendMaxPktLenErr_RMASK 0x1 1558#define QIB_7322_ErrStatus_0_SendMinPktLenErr_LSB 0x1D 1559#define QIB_7322_ErrStatus_0_SendMinPktLenErr_MSB 0x1D 1560#define QIB_7322_ErrStatus_0_SendMinPktLenErr_RMASK 0x1 1561#define QIB_7322_ErrStatus_0_RcvIBLostLinkErr_LSB 0x11 1562#define QIB_7322_ErrStatus_0_RcvIBLostLinkErr_MSB 0x11 1563#define QIB_7322_ErrStatus_0_RcvIBLostLinkErr_RMASK 0x1 1564#define QIB_7322_ErrStatus_0_RcvHdrErr_LSB 0x10 1565#define QIB_7322_ErrStatus_0_RcvHdrErr_MSB 0x10 1566#define QIB_7322_ErrStatus_0_RcvHdrErr_RMASK 0x1 1567#define QIB_7322_ErrStatus_0_RcvHdrLenErr_LSB 0xF 1568#define QIB_7322_ErrStatus_0_RcvHdrLenErr_MSB 0xF 1569#define QIB_7322_ErrStatus_0_RcvHdrLenErr_RMASK 0x1 1570#define QIB_7322_ErrStatus_0_RcvBadTidErr_LSB 0xE 1571#define QIB_7322_ErrStatus_0_RcvBadTidErr_MSB 0xE 1572#define QIB_7322_ErrStatus_0_RcvBadTidErr_RMASK 0x1 1573#define QIB_7322_ErrStatus_0_RcvBadVersionErr_LSB 0xB 1574#define QIB_7322_ErrStatus_0_RcvBadVersionErr_MSB 0xB 1575#define QIB_7322_ErrStatus_0_RcvBadVersionErr_RMASK 0x1 1576#define QIB_7322_ErrStatus_0_RcvIBFlowErr_LSB 0xA 1577#define QIB_7322_ErrStatus_0_RcvIBFlowErr_MSB 0xA 1578#define QIB_7322_ErrStatus_0_RcvIBFlowErr_RMASK 0x1 1579#define QIB_7322_ErrStatus_0_RcvEBPErr_LSB 0x9 1580#define QIB_7322_ErrStatus_0_RcvEBPErr_MSB 0x9 1581#define QIB_7322_ErrStatus_0_RcvEBPErr_RMASK 0x1 1582#define QIB_7322_ErrStatus_0_RcvUnsupportedVLErr_LSB 0x8 1583#define QIB_7322_ErrStatus_0_RcvUnsupportedVLErr_MSB 0x8 1584#define QIB_7322_ErrStatus_0_RcvUnsupportedVLErr_RMASK 0x1 1585#define QIB_7322_ErrStatus_0_RcvUnexpectedCharErr_LSB 0x7 1586#define QIB_7322_ErrStatus_0_RcvUnexpectedCharErr_MSB 0x7 1587#define QIB_7322_ErrStatus_0_RcvUnexpectedCharErr_RMASK 0x1 1588#define QIB_7322_ErrStatus_0_RcvShortPktLenErr_LSB 0x6 1589#define QIB_7322_ErrStatus_0_RcvShortPktLenErr_MSB 0x6 1590#define QIB_7322_ErrStatus_0_RcvShortPktLenErr_RMASK 0x1 1591#define QIB_7322_ErrStatus_0_RcvLongPktLenErr_LSB 0x5 1592#define QIB_7322_ErrStatus_0_RcvLongPktLenErr_MSB 0x5 1593#define QIB_7322_ErrStatus_0_RcvLongPktLenErr_RMASK 0x1 1594#define QIB_7322_ErrStatus_0_RcvMaxPktLenErr_LSB 0x4 1595#define QIB_7322_ErrStatus_0_RcvMaxPktLenErr_MSB 0x4 1596#define QIB_7322_ErrStatus_0_RcvMaxPktLenErr_RMASK 0x1 1597#define QIB_7322_ErrStatus_0_RcvMinPktLenErr_LSB 0x3 1598#define QIB_7322_ErrStatus_0_RcvMinPktLenErr_MSB 0x3 1599#define QIB_7322_ErrStatus_0_RcvMinPktLenErr_RMASK 0x1 1600#define QIB_7322_ErrStatus_0_RcvICRCErr_LSB 0x2 1601#define QIB_7322_ErrStatus_0_RcvICRCErr_MSB 0x2 1602#define QIB_7322_ErrStatus_0_RcvICRCErr_RMASK 0x1 1603#define QIB_7322_ErrStatus_0_RcvVCRCErr_LSB 0x1 1604#define QIB_7322_ErrStatus_0_RcvVCRCErr_MSB 0x1 1605#define QIB_7322_ErrStatus_0_RcvVCRCErr_RMASK 0x1 1606#define QIB_7322_ErrStatus_0_RcvFormatErr_LSB 0x0 1607#define QIB_7322_ErrStatus_0_RcvFormatErr_MSB 0x0 1608#define QIB_7322_ErrStatus_0_RcvFormatErr_RMASK 0x1 1609 1610#define QIB_7322_ErrClear_0_OFFS 0x1090 1611#define QIB_7322_ErrClear_0_DEF 0x0000000000000000 1612#define QIB_7322_ErrClear_0_IBStatusChangedClear_LSB 0x3A 1613#define QIB_7322_ErrClear_0_IBStatusChangedClear_MSB 0x3A 1614#define QIB_7322_ErrClear_0_IBStatusChangedClear_RMASK 0x1 1615#define QIB_7322_ErrClear_0_SHeadersErrClear_LSB 0x39 1616#define QIB_7322_ErrClear_0_SHeadersErrClear_MSB 0x39 1617#define QIB_7322_ErrClear_0_SHeadersErrClear_RMASK 0x1 1618#define QIB_7322_ErrClear_0_VL15BufMisuseErrClear_LSB 0x36 1619#define QIB_7322_ErrClear_0_VL15BufMisuseErrClear_MSB 0x36 1620#define QIB_7322_ErrClear_0_VL15BufMisuseErrClear_RMASK 0x1 1621#define QIB_7322_ErrClear_0_SDmaHaltErrClear_LSB 0x31 1622#define QIB_7322_ErrClear_0_SDmaHaltErrClear_MSB 0x31 1623#define QIB_7322_ErrClear_0_SDmaHaltErrClear_RMASK 0x1 1624#define QIB_7322_ErrClear_0_SDmaDescAddrMisalignErrClear_LSB 0x30 1625#define QIB_7322_ErrClear_0_SDmaDescAddrMisalignErrClear_MSB 0x30 1626#define QIB_7322_ErrClear_0_SDmaDescAddrMisalignErrClear_RMASK 0x1 1627#define QIB_7322_ErrClear_0_SDmaUnexpDataErrClear_LSB 0x2F 1628#define QIB_7322_ErrClear_0_SDmaUnexpDataErrClear_MSB 0x2F 1629#define QIB_7322_ErrClear_0_SDmaUnexpDataErrClear_RMASK 0x1 1630#define QIB_7322_ErrClear_0_SDmaMissingDwErrClear_LSB 0x2E 1631#define QIB_7322_ErrClear_0_SDmaMissingDwErrClear_MSB 0x2E 1632#define QIB_7322_ErrClear_0_SDmaMissingDwErrClear_RMASK 0x1 1633#define QIB_7322_ErrClear_0_SDmaDwEnErrClear_LSB 0x2D 1634#define QIB_7322_ErrClear_0_SDmaDwEnErrClear_MSB 0x2D 1635#define QIB_7322_ErrClear_0_SDmaDwEnErrClear_RMASK 0x1 1636#define QIB_7322_ErrClear_0_SDmaRpyTagErrClear_LSB 0x2C 1637#define QIB_7322_ErrClear_0_SDmaRpyTagErrClear_MSB 0x2C 1638#define QIB_7322_ErrClear_0_SDmaRpyTagErrClear_RMASK 0x1 1639#define QIB_7322_ErrClear_0_SDma1stDescErrClear_LSB 0x2B 1640#define QIB_7322_ErrClear_0_SDma1stDescErrClear_MSB 0x2B 1641#define QIB_7322_ErrClear_0_SDma1stDescErrClear_RMASK 0x1 1642#define QIB_7322_ErrClear_0_SDmaBaseErrClear_LSB 0x2A 1643#define QIB_7322_ErrClear_0_SDmaBaseErrClear_MSB 0x2A 1644#define QIB_7322_ErrClear_0_SDmaBaseErrClear_RMASK 0x1 1645#define QIB_7322_ErrClear_0_SDmaTailOutOfBoundErrClear_LSB 0x29 1646#define QIB_7322_ErrClear_0_SDmaTailOutOfBoundErrClear_MSB 0x29 1647#define QIB_7322_ErrClear_0_SDmaTailOutOfBoundErrClear_RMASK 0x1 1648#define QIB_7322_ErrClear_0_SDmaOutOfBoundErrClear_LSB 0x28 1649#define QIB_7322_ErrClear_0_SDmaOutOfBoundErrClear_MSB 0x28 1650#define QIB_7322_ErrClear_0_SDmaOutOfBoundErrClear_RMASK 0x1 1651#define QIB_7322_ErrClear_0_SDmaGenMismatchErrClear_LSB 0x27 1652#define QIB_7322_ErrClear_0_SDmaGenMismatchErrClear_MSB 0x27 1653#define QIB_7322_ErrClear_0_SDmaGenMismatchErrClear_RMASK 0x1 1654#define QIB_7322_ErrClear_0_SendBufMisuseErrClear_LSB 0x26 1655#define QIB_7322_ErrClear_0_SendBufMisuseErrClear_MSB 0x26 1656#define QIB_7322_ErrClear_0_SendBufMisuseErrClear_RMASK 0x1 1657#define QIB_7322_ErrClear_0_SendUnsupportedVLErrClear_LSB 0x25 1658#define QIB_7322_ErrClear_0_SendUnsupportedVLErrClear_MSB 0x25 1659#define QIB_7322_ErrClear_0_SendUnsupportedVLErrClear_RMASK 0x1 1660#define QIB_7322_ErrClear_0_SendUnexpectedPktNumErrClear_LSB 0x24 1661#define QIB_7322_ErrClear_0_SendUnexpectedPktNumErrClear_MSB 0x24 1662#define QIB_7322_ErrClear_0_SendUnexpectedPktNumErrClear_RMASK 0x1 1663#define QIB_7322_ErrClear_0_SendDroppedDataPktErrClear_LSB 0x22 1664#define QIB_7322_ErrClear_0_SendDroppedDataPktErrClear_MSB 0x22 1665#define QIB_7322_ErrClear_0_SendDroppedDataPktErrClear_RMASK 0x1 1666#define QIB_7322_ErrClear_0_SendDroppedSmpPktErrClear_LSB 0x21 1667#define QIB_7322_ErrClear_0_SendDroppedSmpPktErrClear_MSB 0x21 1668#define QIB_7322_ErrClear_0_SendDroppedSmpPktErrClear_RMASK 0x1 1669#define QIB_7322_ErrClear_0_SendPktLenErrClear_LSB 0x20 1670#define QIB_7322_ErrClear_0_SendPktLenErrClear_MSB 0x20 1671#define QIB_7322_ErrClear_0_SendPktLenErrClear_RMASK 0x1 1672#define QIB_7322_ErrClear_0_SendUnderRunErrClear_LSB 0x1F 1673#define QIB_7322_ErrClear_0_SendUnderRunErrClear_MSB 0x1F 1674#define QIB_7322_ErrClear_0_SendUnderRunErrClear_RMASK 0x1 1675#define QIB_7322_ErrClear_0_SendMaxPktLenErrClear_LSB 0x1E 1676#define QIB_7322_ErrClear_0_SendMaxPktLenErrClear_MSB 0x1E 1677#define QIB_7322_ErrClear_0_SendMaxPktLenErrClear_RMASK 0x1 1678#define QIB_7322_ErrClear_0_SendMinPktLenErrClear_LSB 0x1D 1679#define QIB_7322_ErrClear_0_SendMinPktLenErrClear_MSB 0x1D 1680#define QIB_7322_ErrClear_0_SendMinPktLenErrClear_RMASK 0x1 1681#define QIB_7322_ErrClear_0_RcvIBLostLinkErrClear_LSB 0x11 1682#define QIB_7322_ErrClear_0_RcvIBLostLinkErrClear_MSB 0x11 1683#define QIB_7322_ErrClear_0_RcvIBLostLinkErrClear_RMASK 0x1 1684#define QIB_7322_ErrClear_0_RcvHdrErrClear_LSB 0x10 1685#define QIB_7322_ErrClear_0_RcvHdrErrClear_MSB 0x10 1686#define QIB_7322_ErrClear_0_RcvHdrErrClear_RMASK 0x1 1687#define QIB_7322_ErrClear_0_RcvHdrLenErrClear_LSB 0xF 1688#define QIB_7322_ErrClear_0_RcvHdrLenErrClear_MSB 0xF 1689#define QIB_7322_ErrClear_0_RcvHdrLenErrClear_RMASK 0x1 1690#define QIB_7322_ErrClear_0_RcvBadTidErrClear_LSB 0xE 1691#define QIB_7322_ErrClear_0_RcvBadTidErrClear_MSB 0xE 1692#define QIB_7322_ErrClear_0_RcvBadTidErrClear_RMASK 0x1 1693#define QIB_7322_ErrClear_0_RcvBadVersionErrClear_LSB 0xB 1694#define QIB_7322_ErrClear_0_RcvBadVersionErrClear_MSB 0xB 1695#define QIB_7322_ErrClear_0_RcvBadVersionErrClear_RMASK 0x1 1696#define QIB_7322_ErrClear_0_RcvIBFlowErrClear_LSB 0xA 1697#define QIB_7322_ErrClear_0_RcvIBFlowErrClear_MSB 0xA 1698#define QIB_7322_ErrClear_0_RcvIBFlowErrClear_RMASK 0x1 1699#define QIB_7322_ErrClear_0_RcvEBPErrClear_LSB 0x9 1700#define QIB_7322_ErrClear_0_RcvEBPErrClear_MSB 0x9 1701#define QIB_7322_ErrClear_0_RcvEBPErrClear_RMASK 0x1 1702#define QIB_7322_ErrClear_0_RcvUnsupportedVLErrClear_LSB 0x8 1703#define QIB_7322_ErrClear_0_RcvUnsupportedVLErrClear_MSB 0x8 1704#define QIB_7322_ErrClear_0_RcvUnsupportedVLErrClear_RMASK 0x1 1705#define QIB_7322_ErrClear_0_RcvUnexpectedCharErrClear_LSB 0x7 1706#define QIB_7322_ErrClear_0_RcvUnexpectedCharErrClear_MSB 0x7 1707#define QIB_7322_ErrClear_0_RcvUnexpectedCharErrClear_RMASK 0x1 1708#define QIB_7322_ErrClear_0_RcvShortPktLenErrClear_LSB 0x6 1709#define QIB_7322_ErrClear_0_RcvShortPktLenErrClear_MSB 0x6 1710#define QIB_7322_ErrClear_0_RcvShortPktLenErrClear_RMASK 0x1 1711#define QIB_7322_ErrClear_0_RcvLongPktLenErrClear_LSB 0x5 1712#define QIB_7322_ErrClear_0_RcvLongPktLenErrClear_MSB 0x5 1713#define QIB_7322_ErrClear_0_RcvLongPktLenErrClear_RMASK 0x1 1714#define QIB_7322_ErrClear_0_RcvMaxPktLenErrClear_LSB 0x4 1715#define QIB_7322_ErrClear_0_RcvMaxPktLenErrClear_MSB 0x4 1716#define QIB_7322_ErrClear_0_RcvMaxPktLenErrClear_RMASK 0x1 1717#define QIB_7322_ErrClear_0_RcvMinPktLenErrClear_LSB 0x3 1718#define QIB_7322_ErrClear_0_RcvMinPktLenErrClear_MSB 0x3 1719#define QIB_7322_ErrClear_0_RcvMinPktLenErrClear_RMASK 0x1 1720#define QIB_7322_ErrClear_0_RcvICRCErrClear_LSB 0x2 1721#define QIB_7322_ErrClear_0_RcvICRCErrClear_MSB 0x2 1722#define QIB_7322_ErrClear_0_RcvICRCErrClear_RMASK 0x1 1723#define QIB_7322_ErrClear_0_RcvVCRCErrClear_LSB 0x1 1724#define QIB_7322_ErrClear_0_RcvVCRCErrClear_MSB 0x1 1725#define QIB_7322_ErrClear_0_RcvVCRCErrClear_RMASK 0x1 1726#define QIB_7322_ErrClear_0_RcvFormatErrClear_LSB 0x0 1727#define QIB_7322_ErrClear_0_RcvFormatErrClear_MSB 0x0 1728#define QIB_7322_ErrClear_0_RcvFormatErrClear_RMASK 0x1 1729 1730#define QIB_7322_TXEStatus_0_OFFS 0x10B8 1731#define QIB_7322_TXEStatus_0_DEF 0x0000000XC00080FF 1732#define QIB_7322_TXEStatus_0_TXE_IBC_Idle_LSB 0x1F 1733#define QIB_7322_TXEStatus_0_TXE_IBC_Idle_MSB 0x1F 1734#define QIB_7322_TXEStatus_0_TXE_IBC_Idle_RMASK 0x1 1735#define QIB_7322_TXEStatus_0_RmFifoEmpty_LSB 0x1E 1736#define QIB_7322_TXEStatus_0_RmFifoEmpty_MSB 0x1E 1737#define QIB_7322_TXEStatus_0_RmFifoEmpty_RMASK 0x1 1738#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL15_LSB 0xF 1739#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL15_MSB 0xF 1740#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL15_RMASK 0x1 1741#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL7_LSB 0x7 1742#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL7_MSB 0x7 1743#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL7_RMASK 0x1 1744#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL6_LSB 0x6 1745#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL6_MSB 0x6 1746#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL6_RMASK 0x1 1747#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL5_LSB 0x5 1748#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL5_MSB 0x5 1749#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL5_RMASK 0x1 1750#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL4_LSB 0x4 1751#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL4_MSB 0x4 1752#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL4_RMASK 0x1 1753#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL3_LSB 0x3 1754#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL3_MSB 0x3 1755#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL3_RMASK 0x1 1756#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL2_LSB 0x2 1757#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL2_MSB 0x2 1758#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL2_RMASK 0x1 1759#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL1_LSB 0x1 1760#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL1_MSB 0x1 1761#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL1_RMASK 0x1 1762#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL0_LSB 0x0 1763#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL0_MSB 0x0 1764#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL0_RMASK 0x1 1765 1766#define QIB_7322_RcvCtrl_0_OFFS 0x1100 1767#define QIB_7322_RcvCtrl_0_DEF 0x0000000000000000 1768#define QIB_7322_RcvCtrl_0_RcvResetCredit_LSB 0x2A 1769#define QIB_7322_RcvCtrl_0_RcvResetCredit_MSB 0x2A 1770#define QIB_7322_RcvCtrl_0_RcvResetCredit_RMASK 0x1 1771#define QIB_7322_RcvCtrl_0_RcvPartitionKeyDisable_LSB 0x29 1772#define QIB_7322_RcvCtrl_0_RcvPartitionKeyDisable_MSB 0x29 1773#define QIB_7322_RcvCtrl_0_RcvPartitionKeyDisable_RMASK 0x1 1774#define QIB_7322_RcvCtrl_0_RcvQPMapEnable_LSB 0x28 1775#define QIB_7322_RcvCtrl_0_RcvQPMapEnable_MSB 0x28 1776#define QIB_7322_RcvCtrl_0_RcvQPMapEnable_RMASK 0x1 1777#define QIB_7322_RcvCtrl_0_RcvIBPortEnable_LSB 0x27 1778#define QIB_7322_RcvCtrl_0_RcvIBPortEnable_MSB 0x27 1779#define QIB_7322_RcvCtrl_0_RcvIBPortEnable_RMASK 0x1 1780#define QIB_7322_RcvCtrl_0_ContextEnableUser_LSB 0x2 1781#define QIB_7322_RcvCtrl_0_ContextEnableUser_MSB 0x11 1782#define QIB_7322_RcvCtrl_0_ContextEnableUser_RMASK 0xFFFF 1783#define QIB_7322_RcvCtrl_0_ContextEnableKernel_LSB 0x0 1784#define QIB_7322_RcvCtrl_0_ContextEnableKernel_MSB 0x0 1785#define QIB_7322_RcvCtrl_0_ContextEnableKernel_RMASK 0x1 1786 1787#define QIB_7322_RcvBTHQP_0_OFFS 0x1108 1788#define QIB_7322_RcvBTHQP_0_DEF 0x0000000000000000 1789#define QIB_7322_RcvBTHQP_0_RcvBTHQP_LSB 0x0 1790#define QIB_7322_RcvBTHQP_0_RcvBTHQP_MSB 0x17 1791#define QIB_7322_RcvBTHQP_0_RcvBTHQP_RMASK 0xFFFFFF 1792 1793#define QIB_7322_RcvQPMapTableA_0_OFFS 0x1110 1794#define QIB_7322_RcvQPMapTableA_0_DEF 0x0000000000000000 1795#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext5_LSB 0x19 1796#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext5_MSB 0x1D 1797#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext5_RMASK 0x1F 1798#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext4_LSB 0x14 1799#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext4_MSB 0x18 1800#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext4_RMASK 0x1F 1801#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext3_LSB 0xF 1802#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext3_MSB 0x13 1803#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext3_RMASK 0x1F 1804#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext2_LSB 0xA 1805#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext2_MSB 0xE 1806#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext2_RMASK 0x1F 1807#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext1_LSB 0x5 1808#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext1_MSB 0x9 1809#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext1_RMASK 0x1F 1810#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext0_LSB 0x0 1811#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext0_MSB 0x4 1812#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext0_RMASK 0x1F 1813 1814#define QIB_7322_RcvQPMapTableB_0_OFFS 0x1118 1815#define QIB_7322_RcvQPMapTableB_0_DEF 0x0000000000000000 1816#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext11_LSB 0x19 1817#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext11_MSB 0x1D 1818#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext11_RMASK 0x1F 1819#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext10_LSB 0x14 1820#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext10_MSB 0x18 1821#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext10_RMASK 0x1F 1822#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext9_LSB 0xF 1823#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext9_MSB 0x13 1824#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext9_RMASK 0x1F 1825#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext8_LSB 0xA 1826#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext8_MSB 0xE 1827#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext8_RMASK 0x1F 1828#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext7_LSB 0x5 1829#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext7_MSB 0x9 1830#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext7_RMASK 0x1F 1831#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext6_LSB 0x0 1832#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext6_MSB 0x4 1833#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext6_RMASK 0x1F 1834 1835#define QIB_7322_RcvQPMapTableC_0_OFFS 0x1120 1836#define QIB_7322_RcvQPMapTableC_0_DEF 0x0000000000000000 1837#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext17_LSB 0x19 1838#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext17_MSB 0x1D 1839#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext17_RMASK 0x1F 1840#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext16_LSB 0x14 1841#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext16_MSB 0x18 1842#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext16_RMASK 0x1F 1843#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext15_LSB 0xF 1844#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext15_MSB 0x13 1845#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext15_RMASK 0x1F 1846#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext14_LSB 0xA 1847#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext14_MSB 0xE 1848#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext14_RMASK 0x1F 1849#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext13_LSB 0x5 1850#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext13_MSB 0x9 1851#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext13_RMASK 0x1F 1852#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext12_LSB 0x0 1853#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext12_MSB 0x4 1854#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext12_RMASK 0x1F 1855 1856#define QIB_7322_RcvQPMapTableD_0_OFFS 0x1128 1857#define QIB_7322_RcvQPMapTableD_0_DEF 0x0000000000000000 1858#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext23_LSB 0x19 1859#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext23_MSB 0x1D 1860#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext23_RMASK 0x1F 1861#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext22_LSB 0x14 1862#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext22_MSB 0x18 1863#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext22_RMASK 0x1F 1864#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext21_LSB 0xF 1865#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext21_MSB 0x13 1866#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext21_RMASK 0x1F 1867#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext20_LSB 0xA 1868#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext20_MSB 0xE 1869#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext20_RMASK 0x1F 1870#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext19_LSB 0x5 1871#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext19_MSB 0x9 1872#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext19_RMASK 0x1F 1873#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext18_LSB 0x0 1874#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext18_MSB 0x4 1875#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext18_RMASK 0x1F 1876 1877#define QIB_7322_RcvQPMapTableE_0_OFFS 0x1130 1878#define QIB_7322_RcvQPMapTableE_0_DEF 0x0000000000000000 1879#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext29_LSB 0x19 1880#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext29_MSB 0x1D 1881#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext29_RMASK 0x1F 1882#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext28_LSB 0x14 1883#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext28_MSB 0x18 1884#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext28_RMASK 0x1F 1885#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext27_LSB 0xF 1886#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext27_MSB 0x13 1887#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext27_RMASK 0x1F 1888#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext26_LSB 0xA 1889#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext26_MSB 0xE 1890#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext26_RMASK 0x1F 1891#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext25_LSB 0x5 1892#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext25_MSB 0x9 1893#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext25_RMASK 0x1F 1894#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext24_LSB 0x0 1895#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext24_MSB 0x4 1896#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext24_RMASK 0x1F 1897 1898#define QIB_7322_RcvQPMapTableF_0_OFFS 0x1138 1899#define QIB_7322_RcvQPMapTableF_0_DEF 0x0000000000000000 1900#define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext31_LSB 0x5 1901#define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext31_MSB 0x9 1902#define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext31_RMASK 0x1F 1903#define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext30_LSB 0x0 1904#define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext30_MSB 0x4 1905#define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext30_RMASK 0x1F 1906 1907#define QIB_7322_PSStat_0_OFFS 0x1140 1908#define QIB_7322_PSStat_0_DEF 0x0000000000000000 1909 1910#define QIB_7322_PSStart_0_OFFS 0x1148 1911#define QIB_7322_PSStart_0_DEF 0x0000000000000000 1912 1913#define QIB_7322_PSInterval_0_OFFS 0x1150 1914#define QIB_7322_PSInterval_0_DEF 0x0000000000000000 1915 1916#define QIB_7322_RcvStatus_0_OFFS 0x1160 1917#define QIB_7322_RcvStatus_0_DEF 0x0000000000000000 1918#define QIB_7322_RcvStatus_0_DmaeqBlockingContext_LSB 0x1 1919#define QIB_7322_RcvStatus_0_DmaeqBlockingContext_MSB 0x5 1920#define QIB_7322_RcvStatus_0_DmaeqBlockingContext_RMASK 0x1F 1921#define QIB_7322_RcvStatus_0_RxPktInProgress_LSB 0x0 1922#define QIB_7322_RcvStatus_0_RxPktInProgress_MSB 0x0 1923#define QIB_7322_RcvStatus_0_RxPktInProgress_RMASK 0x1 1924 1925#define QIB_7322_RcvPartitionKey_0_OFFS 0x1168 1926#define QIB_7322_RcvPartitionKey_0_DEF 0x0000000000000000 1927 1928#define QIB_7322_RcvQPMulticastContext_0_OFFS 0x1170 1929#define QIB_7322_RcvQPMulticastContext_0_DEF 0x0000000000000000 1930#define QIB_7322_RcvQPMulticastContext_0_RcvQpMcContext_LSB 0x0 1931#define QIB_7322_RcvQPMulticastContext_0_RcvQpMcContext_MSB 0x4 1932#define QIB_7322_RcvQPMulticastContext_0_RcvQpMcContext_RMASK 0x1F 1933 1934#define QIB_7322_RcvPktLEDCnt_0_OFFS 0x1178 1935#define QIB_7322_RcvPktLEDCnt_0_DEF 0x0000000000000000 1936#define QIB_7322_RcvPktLEDCnt_0_ONperiod_LSB 0x20 1937#define QIB_7322_RcvPktLEDCnt_0_ONperiod_MSB 0x3F 1938#define QIB_7322_RcvPktLEDCnt_0_ONperiod_RMASK 0xFFFFFFFF 1939#define QIB_7322_RcvPktLEDCnt_0_OFFperiod_LSB 0x0 1940#define QIB_7322_RcvPktLEDCnt_0_OFFperiod_MSB 0x1F 1941#define QIB_7322_RcvPktLEDCnt_0_OFFperiod_RMASK 0xFFFFFFFF 1942 1943#define QIB_7322_SendDmaIdleCnt_0_OFFS 0x1180 1944#define QIB_7322_SendDmaIdleCnt_0_DEF 0x0000000000000000 1945#define QIB_7322_SendDmaIdleCnt_0_SendDmaIdleCnt_LSB 0x0 1946#define QIB_7322_SendDmaIdleCnt_0_SendDmaIdleCnt_MSB 0xF 1947#define QIB_7322_SendDmaIdleCnt_0_SendDmaIdleCnt_RMASK 0xFFFF 1948 1949#define QIB_7322_SendDmaReloadCnt_0_OFFS 0x1188 1950#define QIB_7322_SendDmaReloadCnt_0_DEF 0x0000000000000000 1951#define QIB_7322_SendDmaReloadCnt_0_SendDmaReloadCnt_LSB 0x0 1952#define QIB_7322_SendDmaReloadCnt_0_SendDmaReloadCnt_MSB 0xF 1953#define QIB_7322_SendDmaReloadCnt_0_SendDmaReloadCnt_RMASK 0xFFFF 1954 1955#define QIB_7322_SendDmaDescCnt_0_OFFS 0x1190 1956#define QIB_7322_SendDmaDescCnt_0_DEF 0x0000000000000000 1957#define QIB_7322_SendDmaDescCnt_0_SendDmaDescCnt_LSB 0x0 1958#define QIB_7322_SendDmaDescCnt_0_SendDmaDescCnt_MSB 0xF 1959#define QIB_7322_SendDmaDescCnt_0_SendDmaDescCnt_RMASK 0xFFFF 1960 1961#define QIB_7322_SendCtrl_0_OFFS 0x11C0 1962#define QIB_7322_SendCtrl_0_DEF 0x0000000000000000 1963#define QIB_7322_SendCtrl_0_IBVLArbiterEn_LSB 0xF 1964#define QIB_7322_SendCtrl_0_IBVLArbiterEn_MSB 0xF 1965#define QIB_7322_SendCtrl_0_IBVLArbiterEn_RMASK 0x1 1966#define QIB_7322_SendCtrl_0_TxeDrainRmFifo_LSB 0xE 1967#define QIB_7322_SendCtrl_0_TxeDrainRmFifo_MSB 0xE 1968#define QIB_7322_SendCtrl_0_TxeDrainRmFifo_RMASK 0x1 1969#define QIB_7322_SendCtrl_0_TxeDrainLaFifo_LSB 0xD 1970#define QIB_7322_SendCtrl_0_TxeDrainLaFifo_MSB 0xD 1971#define QIB_7322_SendCtrl_0_TxeDrainLaFifo_RMASK 0x1 1972#define QIB_7322_SendCtrl_0_SDmaHalt_LSB 0xC 1973#define QIB_7322_SendCtrl_0_SDmaHalt_MSB 0xC 1974#define QIB_7322_SendCtrl_0_SDmaHalt_RMASK 0x1 1975#define QIB_7322_SendCtrl_0_SDmaEnable_LSB 0xB 1976#define QIB_7322_SendCtrl_0_SDmaEnable_MSB 0xB 1977#define QIB_7322_SendCtrl_0_SDmaEnable_RMASK 0x1 1978#define QIB_7322_SendCtrl_0_SDmaSingleDescriptor_LSB 0xA 1979#define QIB_7322_SendCtrl_0_SDmaSingleDescriptor_MSB 0xA 1980#define QIB_7322_SendCtrl_0_SDmaSingleDescriptor_RMASK 0x1 1981#define QIB_7322_SendCtrl_0_SDmaIntEnable_LSB 0x9 1982#define QIB_7322_SendCtrl_0_SDmaIntEnable_MSB 0x9 1983#define QIB_7322_SendCtrl_0_SDmaIntEnable_RMASK 0x1 1984#define QIB_7322_SendCtrl_0_SDmaCleanup_LSB 0x8 1985#define QIB_7322_SendCtrl_0_SDmaCleanup_MSB 0x8 1986#define QIB_7322_SendCtrl_0_SDmaCleanup_RMASK 0x1 1987#define QIB_7322_SendCtrl_0_ForceCreditUpToDate_LSB 0x7 1988#define QIB_7322_SendCtrl_0_ForceCreditUpToDate_MSB 0x7 1989#define QIB_7322_SendCtrl_0_ForceCreditUpToDate_RMASK 0x1 1990#define QIB_7322_SendCtrl_0_SendEnable_LSB 0x3 1991#define QIB_7322_SendCtrl_0_SendEnable_MSB 0x3 1992#define QIB_7322_SendCtrl_0_SendEnable_RMASK 0x1 1993#define QIB_7322_SendCtrl_0_TxeBypassIbc_LSB 0x1 1994#define QIB_7322_SendCtrl_0_TxeBypassIbc_MSB 0x1 1995#define QIB_7322_SendCtrl_0_TxeBypassIbc_RMASK 0x1 1996#define QIB_7322_SendCtrl_0_TxeAbortIbc_LSB 0x0 1997#define QIB_7322_SendCtrl_0_TxeAbortIbc_MSB 0x0 1998#define QIB_7322_SendCtrl_0_TxeAbortIbc_RMASK 0x1 1999 2000#define QIB_7322_SendDmaBase_0_OFFS 0x11F8 2001#define QIB_7322_SendDmaBase_0_DEF 0x0000000000000000 2002#define QIB_7322_SendDmaBase_0_SendDmaBase_LSB 0x0 2003#define QIB_7322_SendDmaBase_0_SendDmaBase_MSB 0x2F 2004#define QIB_7322_SendDmaBase_0_SendDmaBase_RMASK 0xFFFFFFFFFFFF 2005 2006#define QIB_7322_SendDmaLenGen_0_OFFS 0x1200 2007#define QIB_7322_SendDmaLenGen_0_DEF 0x0000000000000000 2008#define QIB_7322_SendDmaLenGen_0_Generation_LSB 0x10 2009#define QIB_7322_SendDmaLenGen_0_Generation_MSB 0x12 2010#define QIB_7322_SendDmaLenGen_0_Generation_RMASK 0x7 2011#define QIB_7322_SendDmaLenGen_0_Length_LSB 0x0 2012#define QIB_7322_SendDmaLenGen_0_Length_MSB 0xF 2013#define QIB_7322_SendDmaLenGen_0_Length_RMASK 0xFFFF 2014 2015#define QIB_7322_SendDmaTail_0_OFFS 0x1208 2016#define QIB_7322_SendDmaTail_0_DEF 0x0000000000000000 2017#define QIB_7322_SendDmaTail_0_SendDmaTail_LSB 0x0 2018#define QIB_7322_SendDmaTail_0_SendDmaTail_MSB 0xF 2019#define QIB_7322_SendDmaTail_0_SendDmaTail_RMASK 0xFFFF 2020 2021#define QIB_7322_SendDmaHead_0_OFFS 0x1210 2022#define QIB_7322_SendDmaHead_0_DEF 0x0000000000000000 2023#define QIB_7322_SendDmaHead_0_InternalSendDmaHead_LSB 0x20 2024#define QIB_7322_SendDmaHead_0_InternalSendDmaHead_MSB 0x2F 2025#define QIB_7322_SendDmaHead_0_InternalSendDmaHead_RMASK 0xFFFF 2026#define QIB_7322_SendDmaHead_0_SendDmaHead_LSB 0x0 2027#define QIB_7322_SendDmaHead_0_SendDmaHead_MSB 0xF 2028#define QIB_7322_SendDmaHead_0_SendDmaHead_RMASK 0xFFFF 2029 2030#define QIB_7322_SendDmaHeadAddr_0_OFFS 0x1218 2031#define QIB_7322_SendDmaHeadAddr_0_DEF 0x0000000000000000 2032#define QIB_7322_SendDmaHeadAddr_0_SendDmaHeadAddr_LSB 0x0 2033#define QIB_7322_SendDmaHeadAddr_0_SendDmaHeadAddr_MSB 0x2F 2034#define QIB_7322_SendDmaHeadAddr_0_SendDmaHeadAddr_RMASK 0xFFFFFFFFFFFF 2035 2036#define QIB_7322_SendDmaBufMask0_0_OFFS 0x1220 2037#define QIB_7322_SendDmaBufMask0_0_DEF 0x0000000000000000 2038#define QIB_7322_SendDmaBufMask0_0_BufMask_63_0_LSB 0x0 2039#define QIB_7322_SendDmaBufMask0_0_BufMask_63_0_MSB 0x3F 2040#define QIB_7322_SendDmaBufMask0_0_BufMask_63_0_RMASK 0x0 2041 2042#define QIB_7322_SendDmaStatus_0_OFFS 0x1238 2043#define QIB_7322_SendDmaStatus_0_DEF 0x0000000042000000 2044#define QIB_7322_SendDmaStatus_0_ScoreBoardDrainInProg_LSB 0x3F 2045#define QIB_7322_SendDmaStatus_0_ScoreBoardDrainInProg_MSB 0x3F 2046#define QIB_7322_SendDmaStatus_0_ScoreBoardDrainInProg_RMASK 0x1 2047#define QIB_7322_SendDmaStatus_0_HaltInProg_LSB 0x3E 2048#define QIB_7322_SendDmaStatus_0_HaltInProg_MSB 0x3E 2049#define QIB_7322_SendDmaStatus_0_HaltInProg_RMASK 0x1 2050#define QIB_7322_SendDmaStatus_0_InternalSDmaHalt_LSB 0x3D 2051#define QIB_7322_SendDmaStatus_0_InternalSDmaHalt_MSB 0x3D 2052#define QIB_7322_SendDmaStatus_0_InternalSDmaHalt_RMASK 0x1 2053#define QIB_7322_SendDmaStatus_0_ScbDescIndex_13_0_LSB 0x2F 2054#define QIB_7322_SendDmaStatus_0_ScbDescIndex_13_0_MSB 0x3C 2055#define QIB_7322_SendDmaStatus_0_ScbDescIndex_13_0_RMASK 0x3FFF 2056#define QIB_7322_SendDmaStatus_0_RpyLowAddr_6_0_LSB 0x28 2057#define QIB_7322_SendDmaStatus_0_RpyLowAddr_6_0_MSB 0x2E 2058#define QIB_7322_SendDmaStatus_0_RpyLowAddr_6_0_RMASK 0x7F 2059#define QIB_7322_SendDmaStatus_0_RpyTag_7_0_LSB 0x20 2060#define QIB_7322_SendDmaStatus_0_RpyTag_7_0_MSB 0x27 2061#define QIB_7322_SendDmaStatus_0_RpyTag_7_0_RMASK 0xFF 2062#define QIB_7322_SendDmaStatus_0_ScbFull_LSB 0x1F 2063#define QIB_7322_SendDmaStatus_0_ScbFull_MSB 0x1F 2064#define QIB_7322_SendDmaStatus_0_ScbFull_RMASK 0x1 2065#define QIB_7322_SendDmaStatus_0_ScbEmpty_LSB 0x1E 2066#define QIB_7322_SendDmaStatus_0_ScbEmpty_MSB 0x1E 2067#define QIB_7322_SendDmaStatus_0_ScbEmpty_RMASK 0x1 2068#define QIB_7322_SendDmaStatus_0_ScbEntryValid_LSB 0x1D 2069#define QIB_7322_SendDmaStatus_0_ScbEntryValid_MSB 0x1D 2070#define QIB_7322_SendDmaStatus_0_ScbEntryValid_RMASK 0x1 2071#define QIB_7322_SendDmaStatus_0_ScbFetchDescFlag_LSB 0x1C 2072#define QIB_7322_SendDmaStatus_0_ScbFetchDescFlag_MSB 0x1C 2073#define QIB_7322_SendDmaStatus_0_ScbFetchDescFlag_RMASK 0x1 2074#define QIB_7322_SendDmaStatus_0_SplFifoReadyToGo_LSB 0x1B 2075#define QIB_7322_SendDmaStatus_0_SplFifoReadyToGo_MSB 0x1B 2076#define QIB_7322_SendDmaStatus_0_SplFifoReadyToGo_RMASK 0x1 2077#define QIB_7322_SendDmaStatus_0_SplFifoDisarmed_LSB 0x1A 2078#define QIB_7322_SendDmaStatus_0_SplFifoDisarmed_MSB 0x1A 2079#define QIB_7322_SendDmaStatus_0_SplFifoDisarmed_RMASK 0x1 2080#define QIB_7322_SendDmaStatus_0_SplFifoEmpty_LSB 0x19 2081#define QIB_7322_SendDmaStatus_0_SplFifoEmpty_MSB 0x19 2082#define QIB_7322_SendDmaStatus_0_SplFifoEmpty_RMASK 0x1 2083#define QIB_7322_SendDmaStatus_0_SplFifoFull_LSB 0x18 2084#define QIB_7322_SendDmaStatus_0_SplFifoFull_MSB 0x18 2085#define QIB_7322_SendDmaStatus_0_SplFifoFull_RMASK 0x1 2086#define QIB_7322_SendDmaStatus_0_SplFifoBufNum_LSB 0x10 2087#define QIB_7322_SendDmaStatus_0_SplFifoBufNum_MSB 0x17 2088#define QIB_7322_SendDmaStatus_0_SplFifoBufNum_RMASK 0xFF 2089#define QIB_7322_SendDmaStatus_0_SplFifoDescIndex_LSB 0x0 2090#define QIB_7322_SendDmaStatus_0_SplFifoDescIndex_MSB 0xF 2091#define QIB_7322_SendDmaStatus_0_SplFifoDescIndex_RMASK 0xFFFF 2092 2093#define QIB_7322_SendDmaPriorityThld_0_OFFS 0x1258 2094#define QIB_7322_SendDmaPriorityThld_0_DEF 0x0000000000000000 2095#define QIB_7322_SendDmaPriorityThld_0_PriorityThreshold_LSB 0x0 2096#define QIB_7322_SendDmaPriorityThld_0_PriorityThreshold_MSB 0x3 2097#define QIB_7322_SendDmaPriorityThld_0_PriorityThreshold_RMASK 0xF 2098 2099#define QIB_7322_SendHdrErrSymptom_0_OFFS 0x1260 2100#define QIB_7322_SendHdrErrSymptom_0_DEF 0x0000000000000000 2101#define QIB_7322_SendHdrErrSymptom_0_NonKeyPacket_LSB 0x6 2102#define QIB_7322_SendHdrErrSymptom_0_NonKeyPacket_MSB 0x6 2103#define QIB_7322_SendHdrErrSymptom_0_NonKeyPacket_RMASK 0x1 2104#define QIB_7322_SendHdrErrSymptom_0_GRHFail_LSB 0x5 2105#define QIB_7322_SendHdrErrSymptom_0_GRHFail_MSB 0x5 2106#define QIB_7322_SendHdrErrSymptom_0_GRHFail_RMASK 0x1 2107#define QIB_7322_SendHdrErrSymptom_0_PkeyFail_LSB 0x4 2108#define QIB_7322_SendHdrErrSymptom_0_PkeyFail_MSB 0x4 2109#define QIB_7322_SendHdrErrSymptom_0_PkeyFail_RMASK 0x1 2110#define QIB_7322_SendHdrErrSymptom_0_QPFail_LSB 0x3 2111#define QIB_7322_SendHdrErrSymptom_0_QPFail_MSB 0x3 2112#define QIB_7322_SendHdrErrSymptom_0_QPFail_RMASK 0x1 2113#define QIB_7322_SendHdrErrSymptom_0_SLIDFail_LSB 0x2 2114#define QIB_7322_SendHdrErrSymptom_0_SLIDFail_MSB 0x2 2115#define QIB_7322_SendHdrErrSymptom_0_SLIDFail_RMASK 0x1 2116#define QIB_7322_SendHdrErrSymptom_0_RawIPV6_LSB 0x1 2117#define QIB_7322_SendHdrErrSymptom_0_RawIPV6_MSB 0x1 2118#define QIB_7322_SendHdrErrSymptom_0_RawIPV6_RMASK 0x1 2119#define QIB_7322_SendHdrErrSymptom_0_PacketTooSmall_LSB 0x0 2120#define QIB_7322_SendHdrErrSymptom_0_PacketTooSmall_MSB 0x0 2121#define QIB_7322_SendHdrErrSymptom_0_PacketTooSmall_RMASK 0x1 2122 2123#define QIB_7322_RxCreditVL0_0_OFFS 0x1280 2124#define QIB_7322_RxCreditVL0_0_DEF 0x0000000000000000 2125#define QIB_7322_RxCreditVL0_0_RxBufrConsumedVL_LSB 0x10 2126#define QIB_7322_RxCreditVL0_0_RxBufrConsumedVL_MSB 0x1B 2127#define QIB_7322_RxCreditVL0_0_RxBufrConsumedVL_RMASK 0xFFF 2128#define QIB_7322_RxCreditVL0_0_RxMaxCreditVL_LSB 0x0 2129#define QIB_7322_RxCreditVL0_0_RxMaxCreditVL_MSB 0xB 2130#define QIB_7322_RxCreditVL0_0_RxMaxCreditVL_RMASK 0xFFF 2131 2132#define QIB_7322_SendDmaBufUsed0_0_OFFS 0x1480 2133#define QIB_7322_SendDmaBufUsed0_0_DEF 0x0000000000000000 2134#define QIB_7322_SendDmaBufUsed0_0_BufUsed_63_0_LSB 0x0 2135#define QIB_7322_SendDmaBufUsed0_0_BufUsed_63_0_MSB 0x3F 2136#define QIB_7322_SendDmaBufUsed0_0_BufUsed_63_0_RMASK 0x0 2137 2138#define QIB_7322_SendCheckControl_0_OFFS 0x14A8 2139#define QIB_7322_SendCheckControl_0_DEF 0x0000000000000000 2140#define QIB_7322_SendCheckControl_0_PKey_En_LSB 0x4 2141#define QIB_7322_SendCheckControl_0_PKey_En_MSB 0x4 2142#define QIB_7322_SendCheckControl_0_PKey_En_RMASK 0x1 2143#define QIB_7322_SendCheckControl_0_BTHQP_En_LSB 0x3 2144#define QIB_7322_SendCheckControl_0_BTHQP_En_MSB 0x3 2145#define QIB_7322_SendCheckControl_0_BTHQP_En_RMASK 0x1 2146#define QIB_7322_SendCheckControl_0_SLID_En_LSB 0x2 2147#define QIB_7322_SendCheckControl_0_SLID_En_MSB 0x2 2148#define QIB_7322_SendCheckControl_0_SLID_En_RMASK 0x1 2149#define QIB_7322_SendCheckControl_0_RawIPV6_En_LSB 0x1 2150#define QIB_7322_SendCheckControl_0_RawIPV6_En_MSB 0x1 2151#define QIB_7322_SendCheckControl_0_RawIPV6_En_RMASK 0x1 2152#define QIB_7322_SendCheckControl_0_PacketTooSmall_En_LSB 0x0 2153#define QIB_7322_SendCheckControl_0_PacketTooSmall_En_MSB 0x0 2154#define QIB_7322_SendCheckControl_0_PacketTooSmall_En_RMASK 0x1 2155 2156#define QIB_7322_SendIBSLIDMask_0_OFFS 0x14B0 2157#define QIB_7322_SendIBSLIDMask_0_DEF 0x0000000000000000 2158#define QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_LSB 0x0 2159#define QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_MSB 0xF 2160#define QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK 0xFFFF 2161 2162#define QIB_7322_SendIBSLIDAssign_0_OFFS 0x14B8 2163#define QIB_7322_SendIBSLIDAssign_0_DEF 0x0000000000000000 2164#define QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_LSB 0x0 2165#define QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_MSB 0xF 2166#define QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK 0xFFFF 2167 2168#define QIB_7322_IBCStatusA_0_OFFS 0x1540 2169#define QIB_7322_IBCStatusA_0_DEF 0x0000000000000X02 2170#define QIB_7322_IBCStatusA_0_TxCreditOk_VL7_LSB 0x27 2171#define QIB_7322_IBCStatusA_0_TxCreditOk_VL7_MSB 0x27 2172#define QIB_7322_IBCStatusA_0_TxCreditOk_VL7_RMASK 0x1 2173#define QIB_7322_IBCStatusA_0_TxCreditOk_VL6_LSB 0x26 2174#define QIB_7322_IBCStatusA_0_TxCreditOk_VL6_MSB 0x26 2175#define QIB_7322_IBCStatusA_0_TxCreditOk_VL6_RMASK 0x1 2176#define QIB_7322_IBCStatusA_0_TxCreditOk_VL5_LSB 0x25 2177#define QIB_7322_IBCStatusA_0_TxCreditOk_VL5_MSB 0x25 2178#define QIB_7322_IBCStatusA_0_TxCreditOk_VL5_RMASK 0x1 2179#define QIB_7322_IBCStatusA_0_TxCreditOk_VL4_LSB 0x24 2180#define QIB_7322_IBCStatusA_0_TxCreditOk_VL4_MSB 0x24 2181#define QIB_7322_IBCStatusA_0_TxCreditOk_VL4_RMASK 0x1 2182#define QIB_7322_IBCStatusA_0_TxCreditOk_VL3_LSB 0x23 2183#define QIB_7322_IBCStatusA_0_TxCreditOk_VL3_MSB 0x23 2184#define QIB_7322_IBCStatusA_0_TxCreditOk_VL3_RMASK 0x1 2185#define QIB_7322_IBCStatusA_0_TxCreditOk_VL2_LSB 0x22 2186#define QIB_7322_IBCStatusA_0_TxCreditOk_VL2_MSB 0x22 2187#define QIB_7322_IBCStatusA_0_TxCreditOk_VL2_RMASK 0x1 2188#define QIB_7322_IBCStatusA_0_TxCreditOk_VL1_LSB 0x21 2189#define QIB_7322_IBCStatusA_0_TxCreditOk_VL1_MSB 0x21 2190#define QIB_7322_IBCStatusA_0_TxCreditOk_VL1_RMASK 0x1 2191#define QIB_7322_IBCStatusA_0_TxCreditOk_VL0_LSB 0x20 2192#define QIB_7322_IBCStatusA_0_TxCreditOk_VL0_MSB 0x20 2193#define QIB_7322_IBCStatusA_0_TxCreditOk_VL0_RMASK 0x1 2194#define QIB_7322_IBCStatusA_0_TxReady_LSB 0x1E 2195#define QIB_7322_IBCStatusA_0_TxReady_MSB 0x1E 2196#define QIB_7322_IBCStatusA_0_TxReady_RMASK 0x1 2197#define QIB_7322_IBCStatusA_0_LinkSpeedQDR_LSB 0x1D 2198#define QIB_7322_IBCStatusA_0_LinkSpeedQDR_MSB 0x1D 2199#define QIB_7322_IBCStatusA_0_LinkSpeedQDR_RMASK 0x1 2200#define QIB_7322_IBCStatusA_0_ScrambleCapRemote_LSB 0xF 2201#define QIB_7322_IBCStatusA_0_ScrambleCapRemote_MSB 0xF 2202#define QIB_7322_IBCStatusA_0_ScrambleCapRemote_RMASK 0x1 2203#define QIB_7322_IBCStatusA_0_ScrambleEn_LSB 0xE 2204#define QIB_7322_IBCStatusA_0_ScrambleEn_MSB 0xE 2205#define QIB_7322_IBCStatusA_0_ScrambleEn_RMASK 0x1 2206#define QIB_7322_IBCStatusA_0_IBTxLaneReversed_LSB 0xD 2207#define QIB_7322_IBCStatusA_0_IBTxLaneReversed_MSB 0xD 2208#define QIB_7322_IBCStatusA_0_IBTxLaneReversed_RMASK 0x1 2209#define QIB_7322_IBCStatusA_0_IBRxLaneReversed_LSB 0xC 2210#define QIB_7322_IBCStatusA_0_IBRxLaneReversed_MSB 0xC 2211#define QIB_7322_IBCStatusA_0_IBRxLaneReversed_RMASK 0x1 2212#define QIB_7322_IBCStatusA_0_DDS_RXEQ_FAIL_LSB 0xA 2213#define QIB_7322_IBCStatusA_0_DDS_RXEQ_FAIL_MSB 0xA 2214#define QIB_7322_IBCStatusA_0_DDS_RXEQ_FAIL_RMASK 0x1 2215#define QIB_7322_IBCStatusA_0_LinkWidthActive_LSB 0x9 2216#define QIB_7322_IBCStatusA_0_LinkWidthActive_MSB 0x9 2217#define QIB_7322_IBCStatusA_0_LinkWidthActive_RMASK 0x1 2218#define QIB_7322_IBCStatusA_0_LinkSpeedActive_LSB 0x8 2219#define QIB_7322_IBCStatusA_0_LinkSpeedActive_MSB 0x8 2220#define QIB_7322_IBCStatusA_0_LinkSpeedActive_RMASK 0x1 2221#define QIB_7322_IBCStatusA_0_LinkState_LSB 0x5 2222#define QIB_7322_IBCStatusA_0_LinkState_MSB 0x7 2223#define QIB_7322_IBCStatusA_0_LinkState_RMASK 0x7 2224#define QIB_7322_IBCStatusA_0_LinkTrainingState_LSB 0x0 2225#define QIB_7322_IBCStatusA_0_LinkTrainingState_MSB 0x4 2226#define QIB_7322_IBCStatusA_0_LinkTrainingState_RMASK 0x1F 2227 2228#define QIB_7322_IBCStatusB_0_OFFS 0x1548 2229#define QIB_7322_IBCStatusB_0_DEF 0x00000000XXXXXXXX 2230#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_debug_LSB 0x27 2231#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_debug_MSB 0x27 2232#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_debug_RMASK 0x1 2233#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_reached_threshold_LSB 0x26 2234#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_reached_threshold_MSB 0x26 2235#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_reached_threshold_RMASK 0x1 2236#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_started_LSB 0x25 2237#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_started_MSB 0x25 2238#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_started_RMASK 0x1 2239#define QIB_7322_IBCStatusB_0_heartbeat_timed_out_LSB 0x24 2240#define QIB_7322_IBCStatusB_0_heartbeat_timed_out_MSB 0x24 2241#define QIB_7322_IBCStatusB_0_heartbeat_timed_out_RMASK 0x1 2242#define QIB_7322_IBCStatusB_0_heartbeat_crosstalk_LSB 0x20 2243#define QIB_7322_IBCStatusB_0_heartbeat_crosstalk_MSB 0x23 2244#define QIB_7322_IBCStatusB_0_heartbeat_crosstalk_RMASK 0xF 2245#define QIB_7322_IBCStatusB_0_RxEqLocalDevice_LSB 0x1E 2246#define QIB_7322_IBCStatusB_0_RxEqLocalDevice_MSB 0x1F 2247#define QIB_7322_IBCStatusB_0_RxEqLocalDevice_RMASK 0x3 2248#define QIB_7322_IBCStatusB_0_ReqDDSLocalFromRmt_LSB 0x1A 2249#define QIB_7322_IBCStatusB_0_ReqDDSLocalFromRmt_MSB 0x1D 2250#define QIB_7322_IBCStatusB_0_ReqDDSLocalFromRmt_RMASK 0xF 2251#define QIB_7322_IBCStatusB_0_LinkRoundTripLatency_LSB 0x0 2252#define QIB_7322_IBCStatusB_0_LinkRoundTripLatency_MSB 0x19 2253#define QIB_7322_IBCStatusB_0_LinkRoundTripLatency_RMASK 0x3FFFFFF 2254 2255#define QIB_7322_IBCCtrlA_0_OFFS 0x1560 2256#define QIB_7322_IBCCtrlA_0_DEF 0x0000000000000000 2257#define QIB_7322_IBCCtrlA_0_Loopback_LSB 0x3F 2258#define QIB_7322_IBCCtrlA_0_Loopback_MSB 0x3F 2259#define QIB_7322_IBCCtrlA_0_Loopback_RMASK 0x1 2260#define QIB_7322_IBCCtrlA_0_LinkDownDefaultState_LSB 0x3E 2261#define QIB_7322_IBCCtrlA_0_LinkDownDefaultState_MSB 0x3E 2262#define QIB_7322_IBCCtrlA_0_LinkDownDefaultState_RMASK 0x1 2263#define QIB_7322_IBCCtrlA_0_IBLinkEn_LSB 0x3D 2264#define QIB_7322_IBCCtrlA_0_IBLinkEn_MSB 0x3D 2265#define QIB_7322_IBCCtrlA_0_IBLinkEn_RMASK 0x1 2266#define QIB_7322_IBCCtrlA_0_IBStatIntReductionEn_LSB 0x3C 2267#define QIB_7322_IBCCtrlA_0_IBStatIntReductionEn_MSB 0x3C 2268#define QIB_7322_IBCCtrlA_0_IBStatIntReductionEn_RMASK 0x1 2269#define QIB_7322_IBCCtrlA_0_NumVLane_LSB 0x30 2270#define QIB_7322_IBCCtrlA_0_NumVLane_MSB 0x32 2271#define QIB_7322_IBCCtrlA_0_NumVLane_RMASK 0x7 2272#define QIB_7322_IBCCtrlA_0_OverrunThreshold_LSB 0x24 2273#define QIB_7322_IBCCtrlA_0_OverrunThreshold_MSB 0x27 2274#define QIB_7322_IBCCtrlA_0_OverrunThreshold_RMASK 0xF 2275#define QIB_7322_IBCCtrlA_0_PhyerrThreshold_LSB 0x20 2276#define QIB_7322_IBCCtrlA_0_PhyerrThreshold_MSB 0x23 2277#define QIB_7322_IBCCtrlA_0_PhyerrThreshold_RMASK 0xF 2278#define QIB_7322_IBCCtrlA_0_MaxPktLen_LSB 0x15 2279#define QIB_7322_IBCCtrlA_0_MaxPktLen_MSB 0x1F 2280#define QIB_7322_IBCCtrlA_0_MaxPktLen_RMASK 0x7FF 2281#define QIB_7322_IBCCtrlA_0_LinkCmd_LSB 0x13 2282#define QIB_7322_IBCCtrlA_0_LinkCmd_MSB 0x14 2283#define QIB_7322_IBCCtrlA_0_LinkCmd_RMASK 0x3 2284#define QIB_7322_IBCCtrlA_0_LinkInitCmd_LSB 0x10 2285#define QIB_7322_IBCCtrlA_0_LinkInitCmd_MSB 0x12 2286#define QIB_7322_IBCCtrlA_0_LinkInitCmd_RMASK 0x7 2287#define QIB_7322_IBCCtrlA_0_FlowCtrlWaterMark_LSB 0x8 2288#define QIB_7322_IBCCtrlA_0_FlowCtrlWaterMark_MSB 0xF 2289#define QIB_7322_IBCCtrlA_0_FlowCtrlWaterMark_RMASK 0xFF 2290#define QIB_7322_IBCCtrlA_0_FlowCtrlPeriod_LSB 0x0 2291#define QIB_7322_IBCCtrlA_0_FlowCtrlPeriod_MSB 0x7 2292#define QIB_7322_IBCCtrlA_0_FlowCtrlPeriod_RMASK 0xFF 2293 2294#define QIB_7322_IBCCtrlB_0_OFFS 0x1568 2295#define QIB_7322_IBCCtrlB_0_DEF 0x00000000000305FF 2296#define QIB_7322_IBCCtrlB_0_IB_DLID_MASK_LSB 0x30 2297#define QIB_7322_IBCCtrlB_0_IB_DLID_MASK_MSB 0x3F 2298#define QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK 0xFFFF 2299#define QIB_7322_IBCCtrlB_0_IB_DLID_LSB 0x20 2300#define QIB_7322_IBCCtrlB_0_IB_DLID_MSB 0x2F 2301#define QIB_7322_IBCCtrlB_0_IB_DLID_RMASK 0xFFFF 2302#define QIB_7322_IBCCtrlB_0_IB_ENABLE_FILT_DPKT_LSB 0x1B 2303#define QIB_7322_IBCCtrlB_0_IB_ENABLE_FILT_DPKT_MSB 0x1B 2304#define QIB_7322_IBCCtrlB_0_IB_ENABLE_FILT_DPKT_RMASK 0x1 2305#define QIB_7322_IBCCtrlB_0_HRTBT_REQ_LSB 0x1A 2306#define QIB_7322_IBCCtrlB_0_HRTBT_REQ_MSB 0x1A 2307#define QIB_7322_IBCCtrlB_0_HRTBT_REQ_RMASK 0x1 2308#define QIB_7322_IBCCtrlB_0_HRTBT_PORT_LSB 0x12 2309#define QIB_7322_IBCCtrlB_0_HRTBT_PORT_MSB 0x19 2310#define QIB_7322_IBCCtrlB_0_HRTBT_PORT_RMASK 0xFF 2311#define QIB_7322_IBCCtrlB_0_HRTBT_AUTO_LSB 0x11 2312#define QIB_7322_IBCCtrlB_0_HRTBT_AUTO_MSB 0x11 2313#define QIB_7322_IBCCtrlB_0_HRTBT_AUTO_RMASK 0x1 2314#define QIB_7322_IBCCtrlB_0_HRTBT_ENB_LSB 0x10 2315#define QIB_7322_IBCCtrlB_0_HRTBT_ENB_MSB 0x10 2316#define QIB_7322_IBCCtrlB_0_HRTBT_ENB_RMASK 0x1 2317#define QIB_7322_IBCCtrlB_0_SD_DDS_LSB 0xC 2318#define QIB_7322_IBCCtrlB_0_SD_DDS_MSB 0xF 2319#define QIB_7322_IBCCtrlB_0_SD_DDS_RMASK 0xF 2320#define QIB_7322_IBCCtrlB_0_SD_DDSV_LSB 0xB 2321#define QIB_7322_IBCCtrlB_0_SD_DDSV_MSB 0xB 2322#define QIB_7322_IBCCtrlB_0_SD_DDSV_RMASK 0x1 2323#define QIB_7322_IBCCtrlB_0_SD_ADD_ENB_LSB 0xA 2324#define QIB_7322_IBCCtrlB_0_SD_ADD_ENB_MSB 0xA 2325#define QIB_7322_IBCCtrlB_0_SD_ADD_ENB_RMASK 0x1 2326#define QIB_7322_IBCCtrlB_0_SD_RX_EQUAL_ENABLE_LSB 0x9 2327#define QIB_7322_IBCCtrlB_0_SD_RX_EQUAL_ENABLE_MSB 0x9 2328#define QIB_7322_IBCCtrlB_0_SD_RX_EQUAL_ENABLE_RMASK 0x1 2329#define QIB_7322_IBCCtrlB_0_IB_LANE_REV_SUPPORTED_LSB 0x8 2330#define QIB_7322_IBCCtrlB_0_IB_LANE_REV_SUPPORTED_MSB 0x8 2331#define QIB_7322_IBCCtrlB_0_IB_LANE_REV_SUPPORTED_RMASK 0x1 2332#define QIB_7322_IBCCtrlB_0_IB_POLARITY_REV_SUPP_LSB 0x7 2333#define QIB_7322_IBCCtrlB_0_IB_POLARITY_REV_SUPP_MSB 0x7 2334#define QIB_7322_IBCCtrlB_0_IB_POLARITY_REV_SUPP_RMASK 0x1 2335#define QIB_7322_IBCCtrlB_0_IB_NUM_CHANNELS_LSB 0x5 2336#define QIB_7322_IBCCtrlB_0_IB_NUM_CHANNELS_MSB 0x6 2337#define QIB_7322_IBCCtrlB_0_IB_NUM_CHANNELS_RMASK 0x3 2338#define QIB_7322_IBCCtrlB_0_SD_SPEED_QDR_LSB 0x4 2339#define QIB_7322_IBCCtrlB_0_SD_SPEED_QDR_MSB 0x4 2340#define QIB_7322_IBCCtrlB_0_SD_SPEED_QDR_RMASK 0x1 2341#define QIB_7322_IBCCtrlB_0_SD_SPEED_DDR_LSB 0x3 2342#define QIB_7322_IBCCtrlB_0_SD_SPEED_DDR_MSB 0x3 2343#define QIB_7322_IBCCtrlB_0_SD_SPEED_DDR_RMASK 0x1 2344#define QIB_7322_IBCCtrlB_0_SD_SPEED_SDR_LSB 0x2 2345#define QIB_7322_IBCCtrlB_0_SD_SPEED_SDR_MSB 0x2 2346#define QIB_7322_IBCCtrlB_0_SD_SPEED_SDR_RMASK 0x1 2347#define QIB_7322_IBCCtrlB_0_SD_SPEED_LSB 0x1 2348#define QIB_7322_IBCCtrlB_0_SD_SPEED_MSB 0x1 2349#define QIB_7322_IBCCtrlB_0_SD_SPEED_RMASK 0x1 2350#define QIB_7322_IBCCtrlB_0_IB_ENHANCED_MODE_LSB 0x0 2351#define QIB_7322_IBCCtrlB_0_IB_ENHANCED_MODE_MSB 0x0 2352#define QIB_7322_IBCCtrlB_0_IB_ENHANCED_MODE_RMASK 0x1 2353 2354#define QIB_7322_IBCCtrlC_0_OFFS 0x1570 2355#define QIB_7322_IBCCtrlC_0_DEF 0x0000000000000301 2356#define QIB_7322_IBCCtrlC_0_IB_BACK_PORCH_LSB 0x5 2357#define QIB_7322_IBCCtrlC_0_IB_BACK_PORCH_MSB 0x9 2358#define QIB_7322_IBCCtrlC_0_IB_BACK_PORCH_RMASK 0x1F 2359#define QIB_7322_IBCCtrlC_0_IB_FRONT_PORCH_LSB 0x0 2360#define QIB_7322_IBCCtrlC_0_IB_FRONT_PORCH_MSB 0x4 2361#define QIB_7322_IBCCtrlC_0_IB_FRONT_PORCH_RMASK 0x1F 2362 2363#define QIB_7322_HRTBT_GUID_0_OFFS 0x1588 2364#define QIB_7322_HRTBT_GUID_0_DEF 0x0000000000000000 2365 2366#define QIB_7322_IB_SDTEST_IF_TX_0_OFFS 0x1590 2367#define QIB_7322_IB_SDTEST_IF_TX_0_DEF 0x0000000000000000 2368#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_RX_CFG_LSB 0x30 2369#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_RX_CFG_MSB 0x3F 2370#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_RX_CFG_RMASK 0xFFFF 2371#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_TX_CFG_LSB 0x20 2372#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_TX_CFG_MSB 0x2F 2373#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_TX_CFG_RMASK 0xFFFF 2374#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_SPEED_LSB 0xD 2375#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_SPEED_MSB 0xF 2376#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_SPEED_RMASK 0x7 2377#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_OPCODE_LSB 0xB 2378#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_OPCODE_MSB 0xC 2379#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_OPCODE_RMASK 0x3 2380#define QIB_7322_IB_SDTEST_IF_TX_0_CREDIT_CHANGE_LSB 0x4 2381#define QIB_7322_IB_SDTEST_IF_TX_0_CREDIT_CHANGE_MSB 0x4 2382#define QIB_7322_IB_SDTEST_IF_TX_0_CREDIT_CHANGE_RMASK 0x1 2383#define QIB_7322_IB_SDTEST_IF_TX_0_VL_CAP_LSB 0x2 2384#define QIB_7322_IB_SDTEST_IF_TX_0_VL_CAP_MSB 0x3 2385#define QIB_7322_IB_SDTEST_IF_TX_0_VL_CAP_RMASK 0x3 2386#define QIB_7322_IB_SDTEST_IF_TX_0_TS_3_TX_VALID_LSB 0x1 2387#define QIB_7322_IB_SDTEST_IF_TX_0_TS_3_TX_VALID_MSB 0x1 2388#define QIB_7322_IB_SDTEST_IF_TX_0_TS_3_TX_VALID_RMASK 0x1 2389#define QIB_7322_IB_SDTEST_IF_TX_0_TS_T_TX_VALID_LSB 0x0 2390#define QIB_7322_IB_SDTEST_IF_TX_0_TS_T_TX_VALID_MSB 0x0 2391#define QIB_7322_IB_SDTEST_IF_TX_0_TS_T_TX_VALID_RMASK 0x1 2392 2393#define QIB_7322_IB_SDTEST_IF_RX_0_OFFS 0x1598 2394#define QIB_7322_IB_SDTEST_IF_RX_0_DEF 0x0000000000000000 2395#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_RX_CFG_LSB 0x30 2396#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_RX_CFG_MSB 0x3F 2397#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_RX_CFG_RMASK 0xFFFF 2398#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_TX_CFG_LSB 0x20 2399#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_TX_CFG_MSB 0x2F 2400#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_TX_CFG_RMASK 0xFFFF 2401#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_B_LSB 0x18 2402#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_B_MSB 0x1F 2403#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_B_RMASK 0xFF 2404#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_A_LSB 0x10 2405#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_A_MSB 0x17 2406#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_A_RMASK 0xFF 2407#define QIB_7322_IB_SDTEST_IF_RX_0_TS_3_RX_VALID_LSB 0x1 2408#define QIB_7322_IB_SDTEST_IF_RX_0_TS_3_RX_VALID_MSB 0x1 2409#define QIB_7322_IB_SDTEST_IF_RX_0_TS_3_RX_VALID_RMASK 0x1 2410#define QIB_7322_IB_SDTEST_IF_RX_0_TS_T_RX_VALID_LSB 0x0 2411#define QIB_7322_IB_SDTEST_IF_RX_0_TS_T_RX_VALID_MSB 0x0 2412#define QIB_7322_IB_SDTEST_IF_RX_0_TS_T_RX_VALID_RMASK 0x1 2413 2414#define QIB_7322_IBNCModeCtrl_0_OFFS 0x15B8 2415#define QIB_7322_IBNCModeCtrl_0_DEF 0x0000000000000000 2416#define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteForce_LSB 0x22 2417#define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteForce_MSB 0x22 2418#define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteForce_RMASK 0x1 2419#define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteMask_LSB 0x21 2420#define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteMask_MSB 0x21 2421#define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteMask_RMASK 0x1 2422#define QIB_7322_IBNCModeCtrl_0_ScrambleCapLocal_LSB 0x20 2423#define QIB_7322_IBNCModeCtrl_0_ScrambleCapLocal_MSB 0x20 2424#define QIB_7322_IBNCModeCtrl_0_ScrambleCapLocal_RMASK 0x1 2425#define QIB_7322_IBNCModeCtrl_0_TSMCode_TS2_LSB 0x11 2426#define QIB_7322_IBNCModeCtrl_0_TSMCode_TS2_MSB 0x19 2427#define QIB_7322_IBNCModeCtrl_0_TSMCode_TS2_RMASK 0x1FF 2428#define QIB_7322_IBNCModeCtrl_0_TSMCode_TS1_LSB 0x8 2429#define QIB_7322_IBNCModeCtrl_0_TSMCode_TS1_MSB 0x10 2430#define QIB_7322_IBNCModeCtrl_0_TSMCode_TS1_RMASK 0x1FF 2431#define QIB_7322_IBNCModeCtrl_0_TSMEnable_ignore_TSM_on_rx_LSB 0x2 2432#define QIB_7322_IBNCModeCtrl_0_TSMEnable_ignore_TSM_on_rx_MSB 0x2 2433#define QIB_7322_IBNCModeCtrl_0_TSMEnable_ignore_TSM_on_rx_RMASK 0x1 2434#define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS2_LSB 0x1 2435#define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS2_MSB 0x1 2436#define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS2_RMASK 0x1 2437#define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS1_LSB 0x0 2438#define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS1_MSB 0x0 2439#define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS1_RMASK 0x1 2440 2441#define QIB_7322_IBSerdesStatus_0_OFFS 0x15D0 2442#define QIB_7322_IBSerdesStatus_0_DEF 0x0000000000000000 2443 2444#define QIB_7322_IBPCSConfig_0_OFFS 0x15D8 2445#define QIB_7322_IBPCSConfig_0_DEF 0x0000000000000007 2446#define QIB_7322_IBPCSConfig_0_link_sync_mask_LSB 0x9 2447#define QIB_7322_IBPCSConfig_0_link_sync_mask_MSB 0x12 2448#define QIB_7322_IBPCSConfig_0_link_sync_mask_RMASK 0x3FF 2449#define QIB_7322_IBPCSConfig_0_xcv_rreset_LSB 0x2 2450#define QIB_7322_IBPCSConfig_0_xcv_rreset_MSB 0x2 2451#define QIB_7322_IBPCSConfig_0_xcv_rreset_RMASK 0x1 2452#define QIB_7322_IBPCSConfig_0_xcv_treset_LSB 0x1 2453#define QIB_7322_IBPCSConfig_0_xcv_treset_MSB 0x1 2454#define QIB_7322_IBPCSConfig_0_xcv_treset_RMASK 0x1 2455#define QIB_7322_IBPCSConfig_0_tx_rx_reset_LSB 0x0 2456#define QIB_7322_IBPCSConfig_0_tx_rx_reset_MSB 0x0 2457#define QIB_7322_IBPCSConfig_0_tx_rx_reset_RMASK 0x1 2458 2459#define QIB_7322_IBSerdesCtrl_0_OFFS 0x15E0 2460#define QIB_7322_IBSerdesCtrl_0_DEF 0x0000000000FFA00F 2461#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_QDR_LSB 0x1A 2462#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_QDR_MSB 0x1A 2463#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_QDR_RMASK 0x1 2464#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_DDR_LSB 0x19 2465#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_DDR_MSB 0x19 2466#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_DDR_RMASK 0x1 2467#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_SDR_LSB 0x18 2468#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_SDR_MSB 0x18 2469#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_SDR_RMASK 0x1 2470#define QIB_7322_IBSerdesCtrl_0_CHANNEL_RESET_N_LSB 0x14 2471#define QIB_7322_IBSerdesCtrl_0_CHANNEL_RESET_N_MSB 0x17 2472#define QIB_7322_IBSerdesCtrl_0_CHANNEL_RESET_N_RMASK 0xF 2473#define QIB_7322_IBSerdesCtrl_0_CGMODE_LSB 0x10 2474#define QIB_7322_IBSerdesCtrl_0_CGMODE_MSB 0x13 2475#define QIB_7322_IBSerdesCtrl_0_CGMODE_RMASK 0xF 2476#define QIB_7322_IBSerdesCtrl_0_IB_LAT_MODE_LSB 0xF 2477#define QIB_7322_IBSerdesCtrl_0_IB_LAT_MODE_MSB 0xF 2478#define QIB_7322_IBSerdesCtrl_0_IB_LAT_MODE_RMASK 0x1 2479#define QIB_7322_IBSerdesCtrl_0_RXLOSEN_LSB 0xD 2480#define QIB_7322_IBSerdesCtrl_0_RXLOSEN_MSB 0xD 2481#define QIB_7322_IBSerdesCtrl_0_RXLOSEN_RMASK 0x1 2482#define QIB_7322_IBSerdesCtrl_0_LPEN_LSB 0xC 2483#define QIB_7322_IBSerdesCtrl_0_LPEN_MSB 0xC 2484#define QIB_7322_IBSerdesCtrl_0_LPEN_RMASK 0x1 2485#define QIB_7322_IBSerdesCtrl_0_PLLPD_LSB 0xB 2486#define QIB_7322_IBSerdesCtrl_0_PLLPD_MSB 0xB 2487#define QIB_7322_IBSerdesCtrl_0_PLLPD_RMASK 0x1 2488#define QIB_7322_IBSerdesCtrl_0_TXPD_LSB 0xA 2489#define QIB_7322_IBSerdesCtrl_0_TXPD_MSB 0xA 2490#define QIB_7322_IBSerdesCtrl_0_TXPD_RMASK 0x1 2491#define QIB_7322_IBSerdesCtrl_0_RXPD_LSB 0x9 2492#define QIB_7322_IBSerdesCtrl_0_RXPD_MSB 0x9 2493#define QIB_7322_IBSerdesCtrl_0_RXPD_RMASK 0x1 2494#define QIB_7322_IBSerdesCtrl_0_TXIDLE_LSB 0x8 2495#define QIB_7322_IBSerdesCtrl_0_TXIDLE_MSB 0x8 2496#define QIB_7322_IBSerdesCtrl_0_TXIDLE_RMASK 0x1 2497#define QIB_7322_IBSerdesCtrl_0_CMODE_LSB 0x0 2498#define QIB_7322_IBSerdesCtrl_0_CMODE_MSB 0x6 2499#define QIB_7322_IBSerdesCtrl_0_CMODE_RMASK 0x7F 2500 2501#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_OFFS 0x1600 2502#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_DEF 0x0000000000000000 2503#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_tx_override_deemphasis_select_LSB 0x1F 2504#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_tx_override_deemphasis_select_MSB 0x1F 2505#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_tx_override_deemphasis_select_RMASK 0x1 2506#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_reset_tx_deemphasis_override_LSB 0x1E 2507#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_reset_tx_deemphasis_override_MSB 0x1E 2508#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_reset_tx_deemphasis_override_RMASK 0x1 2509#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txampcntl_d2a_LSB 0xE 2510#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txampcntl_d2a_MSB 0x11 2511#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txampcntl_d2a_RMASK 0xF 2512#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txc0_ena_LSB 0x9 2513#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txc0_ena_MSB 0xD 2514#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txc0_ena_RMASK 0x1F 2515#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcp1_ena_LSB 0x5 2516#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcp1_ena_MSB 0x8 2517#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcp1_ena_RMASK 0xF 2518#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_xtra_emph0_LSB 0x3 2519#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_xtra_emph0_MSB 0x4 2520#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_xtra_emph0_RMASK 0x3 2521#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_ena_LSB 0x0 2522#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_ena_MSB 0x2 2523#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_ena_RMASK 0x7 2524 2525#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_OFFS 0x1640 2526#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_DEF 0x0000000000000000 2527#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch3_LSB 0x27 2528#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch3_MSB 0x27 2529#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch3_RMASK 0x1 2530#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch2_LSB 0x26 2531#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch2_MSB 0x26 2532#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch2_RMASK 0x1 2533#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch1_LSB 0x25 2534#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch1_MSB 0x25 2535#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch1_RMASK 0x1 2536#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch0_LSB 0x24 2537#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch0_MSB 0x24 2538#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch0_RMASK 0x1 2539#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch3_LSB 0x23 2540#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch3_MSB 0x23 2541#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch3_RMASK 0x1 2542#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch2_LSB 0x22 2543#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch2_MSB 0x22 2544#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch2_RMASK 0x1 2545#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch1_LSB 0x21 2546#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch1_MSB 0x21 2547#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch1_RMASK 0x1 2548#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch0_LSB 0x20 2549#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch0_MSB 0x20 2550#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch0_RMASK 0x1 2551#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch3_LSB 0x18 2552#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch3_MSB 0x1F 2553#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch3_RMASK 0xFF 2554#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch2_LSB 0x10 2555#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch2_MSB 0x17 2556#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch2_RMASK 0xFF 2557#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch1_LSB 0x8 2558#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch1_MSB 0xF 2559#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch1_RMASK 0xFF 2560#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch0_LSB 0x0 2561#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch0_MSB 0x7 2562#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch0_RMASK 0xFF 2563 2564#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_OFFS 0x1648 2565#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_DEF 0x0000000000000000 2566#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch3_LSB 0x27 2567#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch3_MSB 0x27 2568#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch3_RMASK 0x1 2569#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch2_LSB 0x26 2570#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch2_MSB 0x26 2571#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch2_RMASK 0x1 2572#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch1_LSB 0x25 2573#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch1_MSB 0x25 2574#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch1_RMASK 0x1 2575#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch0_LSB 0x24 2576#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch0_MSB 0x24 2577#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch0_RMASK 0x1 2578#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch3_LSB 0x23 2579#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch3_MSB 0x23 2580#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch3_RMASK 0x1 2581#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch2_LSB 0x22 2582#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch2_MSB 0x22 2583#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch2_RMASK 0x1 2584#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch1_LSB 0x21 2585#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch1_MSB 0x21 2586#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch1_RMASK 0x1 2587#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch0_LSB 0x20 2588#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch0_MSB 0x20 2589#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch0_RMASK 0x1 2590#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch3_LSB 0x18 2591#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch3_MSB 0x1F 2592#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch3_RMASK 0xFF 2593#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch2_LSB 0x10 2594#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch2_MSB 0x17 2595#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch2_RMASK 0xFF 2596#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch1_LSB 0x8 2597#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch1_MSB 0xF 2598#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch1_RMASK 0xFF 2599#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch0_LSB 0x0 2600#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch0_MSB 0x7 2601#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch0_RMASK 0xFF 2602 2603#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_OFFS 0x1650 2604#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_DEF 0x0000000000000000 2605#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch3_LSB 0x27 2606#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch3_MSB 0x27 2607#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch3_RMASK 0x1 2608#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch2_LSB 0x26 2609#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch2_MSB 0x26 2610#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch2_RMASK 0x1 2611#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch1_LSB 0x25 2612#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch1_MSB 0x25 2613#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch1_RMASK 0x1 2614#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch0_LSB 0x24 2615#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch0_MSB 0x24 2616#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch0_RMASK 0x1 2617#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch3_LSB 0x23 2618#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch3_MSB 0x23 2619#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch3_RMASK 0x1 2620#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch2_LSB 0x22 2621#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch2_MSB 0x22 2622#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch2_RMASK 0x1 2623#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch1_LSB 0x21 2624#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch1_MSB 0x21 2625#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch1_RMASK 0x1 2626#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch0_LSB 0x20 2627#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch0_MSB 0x20 2628#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch0_RMASK 0x1 2629#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch3_LSB 0x18 2630#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch3_MSB 0x1F 2631#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch3_RMASK 0xFF 2632#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch2_LSB 0x10 2633#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch2_MSB 0x17 2634#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch2_RMASK 0xFF 2635#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch1_LSB 0x8 2636#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch1_MSB 0xF 2637#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch1_RMASK 0xFF 2638#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch0_LSB 0x0 2639#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch0_MSB 0x7 2640#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch0_RMASK 0xFF 2641 2642#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_OFFS 0x1658 2643#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_DEF 0x0000000000000000 2644#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch3_LSB 0x27 2645#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch3_MSB 0x27 2646#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch3_RMASK 0x1 2647#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch2_LSB 0x26 2648#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch2_MSB 0x26 2649#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch2_RMASK 0x1 2650#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch1_LSB 0x25 2651#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch1_MSB 0x25 2652#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch1_RMASK 0x1 2653#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch0_LSB 0x24 2654#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch0_MSB 0x24 2655#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch0_RMASK 0x1 2656#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch3_LSB 0x23 2657#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch3_MSB 0x23 2658#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch3_RMASK 0x1 2659#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch2_LSB 0x22 2660#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch2_MSB 0x22 2661#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch2_RMASK 0x1 2662#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch1_LSB 0x21 2663#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch1_MSB 0x21 2664#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch1_RMASK 0x1 2665#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch0_LSB 0x20 2666#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch0_MSB 0x20 2667#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch0_RMASK 0x1 2668#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch3_LSB 0x18 2669#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch3_MSB 0x1F 2670#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch3_RMASK 0xFF 2671#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch2_LSB 0x10 2672#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch2_MSB 0x17 2673#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch2_RMASK 0xFF 2674#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch1_LSB 0x8 2675#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch1_MSB 0xF 2676#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch1_RMASK 0xFF 2677#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch0_LSB 0x0 2678#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch0_MSB 0x7 2679#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch0_RMASK 0xFF 2680 2681#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_OFFS 0x1660 2682#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_DEF 0x0000000000000000 2683#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch3_LSB 0x27 2684#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch3_MSB 0x27 2685#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch3_RMASK 0x1 2686#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch2_LSB 0x26 2687#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch2_MSB 0x26 2688#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch2_RMASK 0x1 2689#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch1_LSB 0x25 2690#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch1_MSB 0x25 2691#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch1_RMASK 0x1 2692#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch0_LSB 0x24 2693#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch0_MSB 0x24 2694#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch0_RMASK 0x1 2695#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch3_LSB 0x23 2696#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch3_MSB 0x23 2697#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch3_RMASK 0x1 2698#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch2_LSB 0x22 2699#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch2_MSB 0x22 2700#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch2_RMASK 0x1 2701#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch1_LSB 0x21 2702#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch1_MSB 0x21 2703#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch1_RMASK 0x1 2704#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch0_LSB 0x20 2705#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch0_MSB 0x20 2706#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch0_RMASK 0x1 2707#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch3_LSB 0x18 2708#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch3_MSB 0x1F 2709#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch3_RMASK 0xFF 2710#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch2_LSB 0x10 2711#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch2_MSB 0x17 2712#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch2_RMASK 0xFF 2713#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch1_LSB 0x8 2714#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch1_MSB 0xF 2715#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch1_RMASK 0xFF 2716#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch0_LSB 0x0 2717#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch0_MSB 0x7 2718#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch0_RMASK 0xFF 2719 2720#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_OFFS 0x1668 2721#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_DEF 0x0000000000000000 2722#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch3_LSB 0x27 2723#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch3_MSB 0x27 2724#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch3_RMASK 0x1 2725#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch2_LSB 0x26 2726#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch2_MSB 0x26 2727#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch2_RMASK 0x1 2728#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch1_LSB 0x25 2729#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch1_MSB 0x25 2730#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch1_RMASK 0x1 2731#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch0_LSB 0x24 2732#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch0_MSB 0x24 2733#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch0_RMASK 0x1 2734#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch3_LSB 0x23 2735#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch3_MSB 0x23 2736#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch3_RMASK 0x1 2737#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch2_LSB 0x22 2738#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch2_MSB 0x22 2739#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch2_RMASK 0x1 2740#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch1_LSB 0x21 2741#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch1_MSB 0x21 2742#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch1_RMASK 0x1 2743#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch0_LSB 0x20 2744#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch0_MSB 0x20 2745#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch0_RMASK 0x1 2746#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch3_LSB 0x18 2747#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch3_MSB 0x1F 2748#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch3_RMASK 0xFF 2749#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch2_LSB 0x10 2750#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch2_MSB 0x17 2751#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch2_RMASK 0xFF 2752#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch1_LSB 0x8 2753#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch1_MSB 0xF 2754#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch1_RMASK 0xFF 2755#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch0_LSB 0x0 2756#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch0_MSB 0x7 2757#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch0_RMASK 0xFF 2758 2759#define QIB_7322_ADAPT_DISABLE_TIMER_THRESHOLD_0_OFFS 0x1670 2760#define QIB_7322_ADAPT_DISABLE_TIMER_THRESHOLD_0_DEF 0x0000000000000000 2761 2762#define QIB_7322_HighPriorityLimit_0_OFFS 0x1BC0 2763#define QIB_7322_HighPriorityLimit_0_DEF 0x0000000000000000 2764#define QIB_7322_HighPriorityLimit_0_Limit_LSB 0x0 2765#define QIB_7322_HighPriorityLimit_0_Limit_MSB 0x7 2766#define QIB_7322_HighPriorityLimit_0_Limit_RMASK 0xFF 2767 2768#define QIB_7322_LowPriority0_0_OFFS 0x1C00 2769#define QIB_7322_LowPriority0_0_DEF 0x0000000000000000 2770#define QIB_7322_LowPriority0_0_VirtualLane_LSB 0x10 2771#define QIB_7322_LowPriority0_0_VirtualLane_MSB 0x12 2772#define QIB_7322_LowPriority0_0_VirtualLane_RMASK 0x7 2773#define QIB_7322_LowPriority0_0_Weight_LSB 0x0 2774#define QIB_7322_LowPriority0_0_Weight_MSB 0x7 2775#define QIB_7322_LowPriority0_0_Weight_RMASK 0xFF 2776 2777#define QIB_7322_HighPriority0_0_OFFS 0x1E00 2778#define QIB_7322_HighPriority0_0_DEF 0x0000000000000000 2779#define QIB_7322_HighPriority0_0_VirtualLane_LSB 0x10 2780#define QIB_7322_HighPriority0_0_VirtualLane_MSB 0x12 2781#define QIB_7322_HighPriority0_0_VirtualLane_RMASK 0x7 2782#define QIB_7322_HighPriority0_0_Weight_LSB 0x0 2783#define QIB_7322_HighPriority0_0_Weight_MSB 0x7 2784#define QIB_7322_HighPriority0_0_Weight_RMASK 0xFF 2785 2786#define QIB_7322_CntrRegBase_1_OFFS 0x2028 2787#define QIB_7322_CntrRegBase_1_DEF 0x0000000000013000 2788 2789#define QIB_7322_RcvQPMulticastContext_1_OFFS 0x2170 2790 2791#define QIB_7322_SendCtrl_1_OFFS 0x21C0 2792 2793#define QIB_7322_SendBufAvail0_OFFS 0x3000 2794#define QIB_7322_SendBufAvail0_DEF 0x0000000000000000 2795#define QIB_7322_SendBufAvail0_SendBuf_31_0_LSB 0x0 2796#define QIB_7322_SendBufAvail0_SendBuf_31_0_MSB 0x3F 2797#define QIB_7322_SendBufAvail0_SendBuf_31_0_RMASK 0x0 2798 2799#define QIB_7322_MsixTable_OFFS 0x8000 2800#define QIB_7322_MsixTable_DEF 0x0000000000000000 2801 2802#define QIB_7322_MsixPba_OFFS 0x9000 2803#define QIB_7322_MsixPba_DEF 0x0000000000000000 2804 2805#define QIB_7322_LAMemory_OFFS 0xA000 2806#define QIB_7322_LAMemory_DEF 0x0000000000000000 2807 2808#define QIB_7322_LBIntCnt_OFFS 0x11000 2809#define QIB_7322_LBIntCnt_DEF 0x0000000000000000 2810 2811#define QIB_7322_LBFlowStallCnt_OFFS 0x11008 2812#define QIB_7322_LBFlowStallCnt_DEF 0x0000000000000000 2813 2814#define QIB_7322_RxTIDFullErrCnt_OFFS 0x110D0 2815#define QIB_7322_RxTIDFullErrCnt_DEF 0x0000000000000000 2816 2817#define QIB_7322_RxTIDValidErrCnt_OFFS 0x110D8 2818#define QIB_7322_RxTIDValidErrCnt_DEF 0x0000000000000000 2819 2820#define QIB_7322_RxP0HdrEgrOvflCnt_OFFS 0x110E8 2821#define QIB_7322_RxP0HdrEgrOvflCnt_DEF 0x0000000000000000 2822 2823#define QIB_7322_PcieRetryBufDiagQwordCnt_OFFS 0x111A0 2824#define QIB_7322_PcieRetryBufDiagQwordCnt_DEF 0x0000000000000000 2825 2826#define QIB_7322_RxTidFlowDropCnt_OFFS 0x111E0 2827#define QIB_7322_RxTidFlowDropCnt_DEF 0x0000000000000000 2828 2829#define QIB_7322_LBIntCnt_0_OFFS 0x12000 2830#define QIB_7322_LBIntCnt_0_DEF 0x0000000000000000 2831 2832#define QIB_7322_TxCreditUpToDateTimeOut_0_OFFS 0x12008 2833#define QIB_7322_TxCreditUpToDateTimeOut_0_DEF 0x0000000000000000 2834 2835#define QIB_7322_TxSDmaDescCnt_0_OFFS 0x12010 2836#define QIB_7322_TxSDmaDescCnt_0_DEF 0x0000000000000000 2837 2838#define QIB_7322_TxUnsupVLErrCnt_0_OFFS 0x12018 2839#define QIB_7322_TxUnsupVLErrCnt_0_DEF 0x0000000000000000 2840 2841#define QIB_7322_TxDataPktCnt_0_OFFS 0x12020 2842#define QIB_7322_TxDataPktCnt_0_DEF 0x0000000000000000 2843 2844#define QIB_7322_TxFlowPktCnt_0_OFFS 0x12028 2845#define QIB_7322_TxFlowPktCnt_0_DEF 0x0000000000000000 2846 2847#define QIB_7322_TxDwordCnt_0_OFFS 0x12030 2848#define QIB_7322_TxDwordCnt_0_DEF 0x0000000000000000 2849 2850#define QIB_7322_TxLenErrCnt_0_OFFS 0x12038 2851#define QIB_7322_TxLenErrCnt_0_DEF 0x0000000000000000 2852 2853#define QIB_7322_TxMaxMinLenErrCnt_0_OFFS 0x12040 2854#define QIB_7322_TxMaxMinLenErrCnt_0_DEF 0x0000000000000000 2855 2856#define QIB_7322_TxUnderrunCnt_0_OFFS 0x12048 2857#define QIB_7322_TxUnderrunCnt_0_DEF 0x0000000000000000 2858 2859#define QIB_7322_TxFlowStallCnt_0_OFFS 0x12050 2860#define QIB_7322_TxFlowStallCnt_0_DEF 0x0000000000000000 2861 2862#define QIB_7322_TxDroppedPktCnt_0_OFFS 0x12058 2863#define QIB_7322_TxDroppedPktCnt_0_DEF 0x0000000000000000 2864 2865#define QIB_7322_RxDroppedPktCnt_0_OFFS 0x12060 2866#define QIB_7322_RxDroppedPktCnt_0_DEF 0x0000000000000000 2867 2868#define QIB_7322_RxDataPktCnt_0_OFFS 0x12068 2869#define QIB_7322_RxDataPktCnt_0_DEF 0x0000000000000000 2870 2871#define QIB_7322_RxFlowPktCnt_0_OFFS 0x12070 2872#define QIB_7322_RxFlowPktCnt_0_DEF 0x0000000000000000 2873 2874#define QIB_7322_RxDwordCnt_0_OFFS 0x12078 2875#define QIB_7322_RxDwordCnt_0_DEF 0x0000000000000000 2876 2877#define QIB_7322_RxLenErrCnt_0_OFFS 0x12080 2878#define QIB_7322_RxLenErrCnt_0_DEF 0x0000000000000000 2879 2880#define QIB_7322_RxMaxMinLenErrCnt_0_OFFS 0x12088 2881#define QIB_7322_RxMaxMinLenErrCnt_0_DEF 0x0000000000000000 2882 2883#define QIB_7322_RxICRCErrCnt_0_OFFS 0x12090 2884#define QIB_7322_RxICRCErrCnt_0_DEF 0x0000000000000000 2885 2886#define QIB_7322_RxVCRCErrCnt_0_OFFS 0x12098 2887#define QIB_7322_RxVCRCErrCnt_0_DEF 0x0000000000000000 2888 2889#define QIB_7322_RxFlowCtrlViolCnt_0_OFFS 0x120A0 2890#define QIB_7322_RxFlowCtrlViolCnt_0_DEF 0x0000000000000000 2891 2892#define QIB_7322_RxVersionErrCnt_0_OFFS 0x120A8 2893#define QIB_7322_RxVersionErrCnt_0_DEF 0x0000000000000000 2894 2895#define QIB_7322_RxLinkMalformCnt_0_OFFS 0x120B0 2896#define QIB_7322_RxLinkMalformCnt_0_DEF 0x0000000000000000 2897 2898#define QIB_7322_RxEBPCnt_0_OFFS 0x120B8 2899#define QIB_7322_RxEBPCnt_0_DEF 0x0000000000000000 2900 2901#define QIB_7322_RxLPCRCErrCnt_0_OFFS 0x120C0 2902#define QIB_7322_RxLPCRCErrCnt_0_DEF 0x0000000000000000 2903 2904#define QIB_7322_RxBufOvflCnt_0_OFFS 0x120C8 2905#define QIB_7322_RxBufOvflCnt_0_DEF 0x0000000000000000 2906 2907#define QIB_7322_RxLenTruncateCnt_0_OFFS 0x120D0 2908#define QIB_7322_RxLenTruncateCnt_0_DEF 0x0000000000000000 2909 2910#define QIB_7322_RxPKeyMismatchCnt_0_OFFS 0x120E0 2911#define QIB_7322_RxPKeyMismatchCnt_0_DEF 0x0000000000000000 2912 2913#define QIB_7322_IBLinkDownedCnt_0_OFFS 0x12180 2914#define QIB_7322_IBLinkDownedCnt_0_DEF 0x0000000000000000 2915 2916#define QIB_7322_IBSymbolErrCnt_0_OFFS 0x12188 2917#define QIB_7322_IBSymbolErrCnt_0_DEF 0x0000000000000000 2918 2919#define QIB_7322_IBStatusChangeCnt_0_OFFS 0x12190 2920#define QIB_7322_IBStatusChangeCnt_0_DEF 0x0000000000000000 2921 2922#define QIB_7322_IBLinkErrRecoveryCnt_0_OFFS 0x12198 2923#define QIB_7322_IBLinkErrRecoveryCnt_0_DEF 0x0000000000000000 2924 2925#define QIB_7322_ExcessBufferOvflCnt_0_OFFS 0x121A8 2926#define QIB_7322_ExcessBufferOvflCnt_0_DEF 0x0000000000000000 2927 2928#define QIB_7322_LocalLinkIntegrityErrCnt_0_OFFS 0x121B0 2929#define QIB_7322_LocalLinkIntegrityErrCnt_0_DEF 0x0000000000000000 2930 2931#define QIB_7322_RxVlErrCnt_0_OFFS 0x121B8 2932#define QIB_7322_RxVlErrCnt_0_DEF 0x0000000000000000 2933 2934#define QIB_7322_RxDlidFltrCnt_0_OFFS 0x121C0 2935#define QIB_7322_RxDlidFltrCnt_0_DEF 0x0000000000000000 2936 2937#define QIB_7322_RxVL15DroppedPktCnt_0_OFFS 0x121C8 2938#define QIB_7322_RxVL15DroppedPktCnt_0_DEF 0x0000000000000000 2939 2940#define QIB_7322_RxOtherLocalPhyErrCnt_0_OFFS 0x121D0 2941#define QIB_7322_RxOtherLocalPhyErrCnt_0_DEF 0x0000000000000000 2942 2943#define QIB_7322_RxQPInvalidContextCnt_0_OFFS 0x121D8 2944#define QIB_7322_RxQPInvalidContextCnt_0_DEF 0x0000000000000000 2945 2946#define QIB_7322_TxHeadersErrCnt_0_OFFS 0x121F8 2947#define QIB_7322_TxHeadersErrCnt_0_DEF 0x0000000000000000 2948 2949#define QIB_7322_PSRcvDataCount_0_OFFS 0x12218 2950#define QIB_7322_PSRcvDataCount_0_DEF 0x0000000000000000 2951 2952#define QIB_7322_PSRcvPktsCount_0_OFFS 0x12220 2953#define QIB_7322_PSRcvPktsCount_0_DEF 0x0000000000000000 2954 2955#define QIB_7322_PSXmitDataCount_0_OFFS 0x12228 2956#define QIB_7322_PSXmitDataCount_0_DEF 0x0000000000000000 2957 2958#define QIB_7322_PSXmitPktsCount_0_OFFS 0x12230 2959#define QIB_7322_PSXmitPktsCount_0_DEF 0x0000000000000000 2960 2961#define QIB_7322_PSXmitWaitCount_0_OFFS 0x12238 2962#define QIB_7322_PSXmitWaitCount_0_DEF 0x0000000000000000 2963 2964#define QIB_7322_LBIntCnt_1_OFFS 0x13000 2965#define QIB_7322_LBIntCnt_1_DEF 0x0000000000000000 2966 2967#define QIB_7322_TxCreditUpToDateTimeOut_1_OFFS 0x13008 2968#define QIB_7322_TxCreditUpToDateTimeOut_1_DEF 0x0000000000000000 2969 2970#define QIB_7322_TxSDmaDescCnt_1_OFFS 0x13010 2971#define QIB_7322_TxSDmaDescCnt_1_DEF 0x0000000000000000 2972 2973#define QIB_7322_TxUnsupVLErrCnt_1_OFFS 0x13018 2974#define QIB_7322_TxUnsupVLErrCnt_1_DEF 0x0000000000000000 2975 2976#define QIB_7322_TxDataPktCnt_1_OFFS 0x13020 2977#define QIB_7322_TxDataPktCnt_1_DEF 0x0000000000000000 2978 2979#define QIB_7322_TxFlowPktCnt_1_OFFS 0x13028 2980#define QIB_7322_TxFlowPktCnt_1_DEF 0x0000000000000000 2981 2982#define QIB_7322_TxDwordCnt_1_OFFS 0x13030 2983#define QIB_7322_TxDwordCnt_1_DEF 0x0000000000000000 2984 2985#define QIB_7322_TxLenErrCnt_1_OFFS 0x13038 2986#define QIB_7322_TxLenErrCnt_1_DEF 0x0000000000000000 2987 2988#define QIB_7322_TxMaxMinLenErrCnt_1_OFFS 0x13040 2989#define QIB_7322_TxMaxMinLenErrCnt_1_DEF 0x0000000000000000 2990 2991#define QIB_7322_TxUnderrunCnt_1_OFFS 0x13048 2992#define QIB_7322_TxUnderrunCnt_1_DEF 0x0000000000000000 2993 2994#define QIB_7322_TxFlowStallCnt_1_OFFS 0x13050 2995#define QIB_7322_TxFlowStallCnt_1_DEF 0x0000000000000000 2996 2997#define QIB_7322_TxDroppedPktCnt_1_OFFS 0x13058 2998#define QIB_7322_TxDroppedPktCnt_1_DEF 0x0000000000000000 2999 3000#define QIB_7322_RxDroppedPktCnt_1_OFFS 0x13060 3001#define QIB_7322_RxDroppedPktCnt_1_DEF 0x0000000000000000 3002 3003#define QIB_7322_RxDataPktCnt_1_OFFS 0x13068 3004#define QIB_7322_RxDataPktCnt_1_DEF 0x0000000000000000 3005 3006#define QIB_7322_RxFlowPktCnt_1_OFFS 0x13070 3007#define QIB_7322_RxFlowPktCnt_1_DEF 0x0000000000000000 3008 3009#define QIB_7322_RxDwordCnt_1_OFFS 0x13078 3010#define QIB_7322_RxDwordCnt_1_DEF 0x0000000000000000 3011 3012#define QIB_7322_RxLenErrCnt_1_OFFS 0x13080 3013#define QIB_7322_RxLenErrCnt_1_DEF 0x0000000000000000 3014 3015#define QIB_7322_RxMaxMinLenErrCnt_1_OFFS 0x13088 3016#define QIB_7322_RxMaxMinLenErrCnt_1_DEF 0x0000000000000000 3017 3018#define QIB_7322_RxICRCErrCnt_1_OFFS 0x13090 3019#define QIB_7322_RxICRCErrCnt_1_DEF 0x0000000000000000 3020 3021#define QIB_7322_RxVCRCErrCnt_1_OFFS 0x13098 3022#define QIB_7322_RxVCRCErrCnt_1_DEF 0x0000000000000000 3023 3024#define QIB_7322_RxFlowCtrlViolCnt_1_OFFS 0x130A0 3025#define QIB_7322_RxFlowCtrlViolCnt_1_DEF 0x0000000000000000 3026 3027#define QIB_7322_RxVersionErrCnt_1_OFFS 0x130A8 3028#define QIB_7322_RxVersionErrCnt_1_DEF 0x0000000000000000 3029 3030#define QIB_7322_RxLinkMalformCnt_1_OFFS 0x130B0 3031#define QIB_7322_RxLinkMalformCnt_1_DEF 0x0000000000000000 3032 3033#define QIB_7322_RxEBPCnt_1_OFFS 0x130B8 3034#define QIB_7322_RxEBPCnt_1_DEF 0x0000000000000000 3035 3036#define QIB_7322_RxLPCRCErrCnt_1_OFFS 0x130C0 3037#define QIB_7322_RxLPCRCErrCnt_1_DEF 0x0000000000000000 3038 3039#define QIB_7322_RxBufOvflCnt_1_OFFS 0x130C8 3040#define QIB_7322_RxBufOvflCnt_1_DEF 0x0000000000000000 3041 3042#define QIB_7322_RxLenTruncateCnt_1_OFFS 0x130D0 3043#define QIB_7322_RxLenTruncateCnt_1_DEF 0x0000000000000000 3044 3045#define QIB_7322_RxPKeyMismatchCnt_1_OFFS 0x130E0 3046#define QIB_7322_RxPKeyMismatchCnt_1_DEF 0x0000000000000000 3047 3048#define QIB_7322_IBLinkDownedCnt_1_OFFS 0x13180 3049#define QIB_7322_IBLinkDownedCnt_1_DEF 0x0000000000000000 3050 3051#define QIB_7322_IBSymbolErrCnt_1_OFFS 0x13188 3052#define QIB_7322_IBSymbolErrCnt_1_DEF 0x0000000000000000 3053 3054#define QIB_7322_IBStatusChangeCnt_1_OFFS 0x13190 3055#define QIB_7322_IBStatusChangeCnt_1_DEF 0x0000000000000000 3056 3057#define QIB_7322_IBLinkErrRecoveryCnt_1_OFFS 0x13198 3058#define QIB_7322_IBLinkErrRecoveryCnt_1_DEF 0x0000000000000000 3059 3060#define QIB_7322_ExcessBufferOvflCnt_1_OFFS 0x131A8 3061#define QIB_7322_ExcessBufferOvflCnt_1_DEF 0x0000000000000000 3062 3063#define QIB_7322_LocalLinkIntegrityErrCnt_1_OFFS 0x131B0 3064#define QIB_7322_LocalLinkIntegrityErrCnt_1_DEF 0x0000000000000000 3065 3066#define QIB_7322_RxVlErrCnt_1_OFFS 0x131B8 3067#define QIB_7322_RxVlErrCnt_1_DEF 0x0000000000000000 3068 3069#define QIB_7322_RxDlidFltrCnt_1_OFFS 0x131C0 3070#define QIB_7322_RxDlidFltrCnt_1_DEF 0x0000000000000000 3071 3072#define QIB_7322_RxVL15DroppedPktCnt_1_OFFS 0x131C8 3073#define QIB_7322_RxVL15DroppedPktCnt_1_DEF 0x0000000000000000 3074 3075#define QIB_7322_RxOtherLocalPhyErrCnt_1_OFFS 0x131D0 3076#define QIB_7322_RxOtherLocalPhyErrCnt_1_DEF 0x0000000000000000 3077 3078#define QIB_7322_RxQPInvalidContextCnt_1_OFFS 0x131D8 3079#define QIB_7322_RxQPInvalidContextCnt_1_DEF 0x0000000000000000 3080 3081#define QIB_7322_TxHeadersErrCnt_1_OFFS 0x131F8 3082#define QIB_7322_TxHeadersErrCnt_1_DEF 0x0000000000000000 3083 3084#define QIB_7322_PSRcvDataCount_1_OFFS 0x13218 3085#define QIB_7322_PSRcvDataCount_1_DEF 0x0000000000000000 3086 3087#define QIB_7322_PSRcvPktsCount_1_OFFS 0x13220 3088#define QIB_7322_PSRcvPktsCount_1_DEF 0x0000000000000000 3089 3090#define QIB_7322_PSXmitDataCount_1_OFFS 0x13228 3091#define QIB_7322_PSXmitDataCount_1_DEF 0x0000000000000000 3092 3093#define QIB_7322_PSXmitPktsCount_1_OFFS 0x13230 3094#define QIB_7322_PSXmitPktsCount_1_DEF 0x0000000000000000 3095 3096#define QIB_7322_PSXmitWaitCount_1_OFFS 0x13238 3097#define QIB_7322_PSXmitWaitCount_1_DEF 0x0000000000000000 3098 3099#define QIB_7322_RcvEgrArray_OFFS 0x14000 3100#define QIB_7322_RcvEgrArray_DEF 0x0000000000000000 3101#define QIB_7322_RcvEgrArray_RT_BufSize_LSB 0x25 3102#define QIB_7322_RcvEgrArray_RT_BufSize_MSB 0x27 3103#define QIB_7322_RcvEgrArray_RT_BufSize_RMASK 0x7 3104#define QIB_7322_RcvEgrArray_RT_Addr_LSB 0x0 3105#define QIB_7322_RcvEgrArray_RT_Addr_MSB 0x24 3106#define QIB_7322_RcvEgrArray_RT_Addr_RMASK 0x1FFFFFFFFF 3107 3108#define QIB_7322_RcvTIDArray0_OFFS 0x50000 3109#define QIB_7322_RcvTIDArray0_DEF 0x0000000000000000 3110#define QIB_7322_RcvTIDArray0_RT_BufSize_LSB 0x25 3111#define QIB_7322_RcvTIDArray0_RT_BufSize_MSB 0x27 3112#define QIB_7322_RcvTIDArray0_RT_BufSize_RMASK 0x7 3113#define QIB_7322_RcvTIDArray0_RT_Addr_LSB 0x0 3114#define QIB_7322_RcvTIDArray0_RT_Addr_MSB 0x24 3115#define QIB_7322_RcvTIDArray0_RT_Addr_RMASK 0x1FFFFFFFFF 3116 3117#define QIB_7322_IBSD_DDS_MAP_TABLE_0_OFFS 0xD0000 3118#define QIB_7322_IBSD_DDS_MAP_TABLE_0_DEF 0x0000000000000000 3119 3120#define QIB_7322_RcvHdrTail0_OFFS 0x200000 3121#define QIB_7322_RcvHdrTail0_DEF 0x0000000000000000 3122 3123#define QIB_7322_RcvHdrHead0_OFFS 0x200008 3124#define QIB_7322_RcvHdrHead0_DEF 0x0000000000000000 3125#define QIB_7322_RcvHdrHead0_counter_LSB 0x20 3126#define QIB_7322_RcvHdrHead0_counter_MSB 0x2F 3127#define QIB_7322_RcvHdrHead0_counter_RMASK 0xFFFF 3128#define QIB_7322_RcvHdrHead0_RcvHeadPointer_LSB 0x0 3129#define QIB_7322_RcvHdrHead0_RcvHeadPointer_MSB 0x1F 3130#define QIB_7322_RcvHdrHead0_RcvHeadPointer_RMASK 0xFFFFFFFF 3131 3132#define QIB_7322_RcvEgrIndexTail0_OFFS 0x200010 3133#define QIB_7322_RcvEgrIndexTail0_DEF 0x0000000000000000 3134 3135#define QIB_7322_RcvEgrIndexHead0_OFFS 0x200018 3136#define QIB_7322_RcvEgrIndexHead0_DEF 0x0000000000000000 3137 3138#define QIB_7322_RcvTIDFlowTable0_OFFS 0x201000 3139#define QIB_7322_RcvTIDFlowTable0_DEF 0x0000000000000000 3140#define QIB_7322_RcvTIDFlowTable0_GenMismatch_LSB 0x1C 3141#define QIB_7322_RcvTIDFlowTable0_GenMismatch_MSB 0x1C 3142#define QIB_7322_RcvTIDFlowTable0_GenMismatch_RMASK 0x1 3143#define QIB_7322_RcvTIDFlowTable0_SeqMismatch_LSB 0x1B 3144#define QIB_7322_RcvTIDFlowTable0_SeqMismatch_MSB 0x1B 3145#define QIB_7322_RcvTIDFlowTable0_SeqMismatch_RMASK 0x1 3146#define QIB_7322_RcvTIDFlowTable0_KeepOnGenErr_LSB 0x16 3147#define QIB_7322_RcvTIDFlowTable0_KeepOnGenErr_MSB 0x16 3148#define QIB_7322_RcvTIDFlowTable0_KeepOnGenErr_RMASK 0x1 3149#define QIB_7322_RcvTIDFlowTable0_KeepAfterSeqErr_LSB 0x15 3150#define QIB_7322_RcvTIDFlowTable0_KeepAfterSeqErr_MSB 0x15 3151#define QIB_7322_RcvTIDFlowTable0_KeepAfterSeqErr_RMASK 0x1 3152#define QIB_7322_RcvTIDFlowTable0_HdrSuppEnabled_LSB 0x14 3153#define QIB_7322_RcvTIDFlowTable0_HdrSuppEnabled_MSB 0x14 3154#define QIB_7322_RcvTIDFlowTable0_HdrSuppEnabled_RMASK 0x1 3155#define QIB_7322_RcvTIDFlowTable0_FlowValid_LSB 0x13 3156#define QIB_7322_RcvTIDFlowTable0_FlowValid_MSB 0x13 3157#define QIB_7322_RcvTIDFlowTable0_FlowValid_RMASK 0x1 3158#define QIB_7322_RcvTIDFlowTable0_GenVal_LSB 0xB 3159#define QIB_7322_RcvTIDFlowTable0_GenVal_MSB 0x12 3160#define QIB_7322_RcvTIDFlowTable0_GenVal_RMASK 0xFF 3161#define QIB_7322_RcvTIDFlowTable0_SeqNum_LSB 0x0 3162#define QIB_7322_RcvTIDFlowTable0_SeqNum_MSB 0xA 3163#define QIB_7322_RcvTIDFlowTable0_SeqNum_RMASK 0x7FF