cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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icc-rpm.h (2752B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Copyright (C) 2020 Linaro Ltd
      4 */
      5
      6#ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H
      7#define __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H
      8
      9#define RPM_BUS_MASTER_REQ	0x73616d62
     10#define RPM_BUS_SLAVE_REQ	0x766c7362
     11
     12#define to_qcom_provider(_provider) \
     13	container_of(_provider, struct qcom_icc_provider, provider)
     14
     15enum qcom_icc_type {
     16	QCOM_ICC_NOC,
     17	QCOM_ICC_BIMC,
     18	QCOM_ICC_QNOC,
     19};
     20
     21/**
     22 * struct qcom_icc_provider - Qualcomm specific interconnect provider
     23 * @provider: generic interconnect provider
     24 * @bus_clks: the clk_bulk_data table of bus clocks
     25 * @num_clks: the total number of clk_bulk_data entries
     26 * @type: the ICC provider type
     27 * @qos_offset: offset to QoS registers
     28 * @regmap: regmap for QoS registers read/write access
     29 * @bus_clk_rate: bus clock rate in Hz
     30 */
     31struct qcom_icc_provider {
     32	struct icc_provider provider;
     33	int num_clks;
     34	enum qcom_icc_type type;
     35	struct regmap *regmap;
     36	unsigned int qos_offset;
     37	u64 *bus_clk_rate;
     38	struct clk_bulk_data bus_clks[];
     39};
     40
     41/**
     42 * struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters
     43 * @areq_prio: node requests priority
     44 * @prio_level: priority level for bus communication
     45 * @limit_commands: activate/deactivate limiter mode during runtime
     46 * @ap_owned: indicates if the node is owned by the AP or by the RPM
     47 * @qos_mode: default qos mode for this node
     48 * @qos_port: qos port number for finding qos registers of this node
     49 * @urg_fwd_en: enable urgent forwarding
     50 */
     51struct qcom_icc_qos {
     52	u32 areq_prio;
     53	u32 prio_level;
     54	bool limit_commands;
     55	bool ap_owned;
     56	int qos_mode;
     57	int qos_port;
     58	bool urg_fwd_en;
     59};
     60
     61/**
     62 * struct qcom_icc_node - Qualcomm specific interconnect nodes
     63 * @name: the node name used in debugfs
     64 * @id: a unique node identifier
     65 * @links: an array of nodes where we can go next while traversing
     66 * @num_links: the total number of @links
     67 * @buswidth: width of the interconnect between a node and the bus (bytes)
     68 * @mas_rpm_id:	RPM id for devices that are bus masters
     69 * @slv_rpm_id:	RPM id for devices that are bus slaves
     70 * @qos: NoC QoS setting parameters
     71 */
     72struct qcom_icc_node {
     73	unsigned char *name;
     74	u16 id;
     75	const u16 *links;
     76	u16 num_links;
     77	u16 buswidth;
     78	int mas_rpm_id;
     79	int slv_rpm_id;
     80	struct qcom_icc_qos qos;
     81};
     82
     83struct qcom_icc_desc {
     84	struct qcom_icc_node * const *nodes;
     85	size_t num_nodes;
     86	const char * const *clocks;
     87	size_t num_clocks;
     88	bool has_bus_pd;
     89	enum qcom_icc_type type;
     90	const struct regmap_config *regmap_cfg;
     91	unsigned int qos_offset;
     92};
     93
     94/* Valid for both NoC and BIMC */
     95#define NOC_QOS_MODE_INVALID		-1
     96#define NOC_QOS_MODE_FIXED		0x0
     97#define NOC_QOS_MODE_BYPASS		0x2
     98
     99int qnoc_probe(struct platform_device *pdev);
    100int qnoc_remove(struct platform_device *pdev);
    101
    102#endif