msm8939.c (32087B)
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020 Linaro Ltd 4 * Author: Jun Nie <jun.nie@linaro.org> 5 * With reference of msm8916 interconnect driver of Georgi Djakov. 6 */ 7 8#include <linux/clk.h> 9#include <linux/device.h> 10#include <linux/interconnect-provider.h> 11#include <linux/io.h> 12#include <linux/module.h> 13#include <linux/platform_device.h> 14#include <linux/regmap.h> 15#include <linux/of_device.h> 16 17#include <dt-bindings/interconnect/qcom,msm8939.h> 18 19#include "smd-rpm.h" 20#include "icc-rpm.h" 21 22enum { 23 MSM8939_BIMC_SNOC_MAS = 1, 24 MSM8939_BIMC_SNOC_SLV, 25 MSM8939_MASTER_AMPSS_M0, 26 MSM8939_MASTER_LPASS, 27 MSM8939_MASTER_BLSP_1, 28 MSM8939_MASTER_DEHR, 29 MSM8939_MASTER_GRAPHICS_3D, 30 MSM8939_MASTER_JPEG, 31 MSM8939_MASTER_MDP_PORT0, 32 MSM8939_MASTER_MDP_PORT1, 33 MSM8939_MASTER_CPP, 34 MSM8939_MASTER_CRYPTO_CORE0, 35 MSM8939_MASTER_SDCC_1, 36 MSM8939_MASTER_SDCC_2, 37 MSM8939_MASTER_QDSS_BAM, 38 MSM8939_MASTER_QDSS_ETR, 39 MSM8939_MASTER_SNOC_CFG, 40 MSM8939_MASTER_SPDM, 41 MSM8939_MASTER_TCU0, 42 MSM8939_MASTER_USB_HS1, 43 MSM8939_MASTER_USB_HS2, 44 MSM8939_MASTER_VFE, 45 MSM8939_MASTER_VIDEO_P0, 46 MSM8939_SNOC_MM_INT_0, 47 MSM8939_SNOC_MM_INT_1, 48 MSM8939_SNOC_MM_INT_2, 49 MSM8939_PNOC_INT_0, 50 MSM8939_PNOC_INT_1, 51 MSM8939_PNOC_MAS_0, 52 MSM8939_PNOC_MAS_1, 53 MSM8939_PNOC_SLV_0, 54 MSM8939_PNOC_SLV_1, 55 MSM8939_PNOC_SLV_2, 56 MSM8939_PNOC_SLV_3, 57 MSM8939_PNOC_SLV_4, 58 MSM8939_PNOC_SLV_8, 59 MSM8939_PNOC_SLV_9, 60 MSM8939_PNOC_SNOC_MAS, 61 MSM8939_PNOC_SNOC_SLV, 62 MSM8939_SNOC_QDSS_INT, 63 MSM8939_SLAVE_AMPSS_L2, 64 MSM8939_SLAVE_APSS, 65 MSM8939_SLAVE_LPASS, 66 MSM8939_SLAVE_BIMC_CFG, 67 MSM8939_SLAVE_BLSP_1, 68 MSM8939_SLAVE_BOOT_ROM, 69 MSM8939_SLAVE_CAMERA_CFG, 70 MSM8939_SLAVE_CATS_128, 71 MSM8939_SLAVE_OCMEM_64, 72 MSM8939_SLAVE_CLK_CTL, 73 MSM8939_SLAVE_CRYPTO_0_CFG, 74 MSM8939_SLAVE_DEHR_CFG, 75 MSM8939_SLAVE_DISPLAY_CFG, 76 MSM8939_SLAVE_EBI_CH0, 77 MSM8939_SLAVE_GRAPHICS_3D_CFG, 78 MSM8939_SLAVE_IMEM_CFG, 79 MSM8939_SLAVE_IMEM, 80 MSM8939_SLAVE_MPM, 81 MSM8939_SLAVE_MSG_RAM, 82 MSM8939_SLAVE_MSS, 83 MSM8939_SLAVE_PDM, 84 MSM8939_SLAVE_PMIC_ARB, 85 MSM8939_SLAVE_PNOC_CFG, 86 MSM8939_SLAVE_PRNG, 87 MSM8939_SLAVE_QDSS_CFG, 88 MSM8939_SLAVE_QDSS_STM, 89 MSM8939_SLAVE_RBCPR_CFG, 90 MSM8939_SLAVE_SDCC_1, 91 MSM8939_SLAVE_SDCC_2, 92 MSM8939_SLAVE_SECURITY, 93 MSM8939_SLAVE_SNOC_CFG, 94 MSM8939_SLAVE_SPDM, 95 MSM8939_SLAVE_SRVC_SNOC, 96 MSM8939_SLAVE_TCSR, 97 MSM8939_SLAVE_TLMM, 98 MSM8939_SLAVE_USB_HS1, 99 MSM8939_SLAVE_USB_HS2, 100 MSM8939_SLAVE_VENUS_CFG, 101 MSM8939_SNOC_BIMC_0_MAS, 102 MSM8939_SNOC_BIMC_0_SLV, 103 MSM8939_SNOC_BIMC_1_MAS, 104 MSM8939_SNOC_BIMC_1_SLV, 105 MSM8939_SNOC_BIMC_2_MAS, 106 MSM8939_SNOC_BIMC_2_SLV, 107 MSM8939_SNOC_INT_0, 108 MSM8939_SNOC_INT_1, 109 MSM8939_SNOC_INT_BIMC, 110 MSM8939_SNOC_PNOC_MAS, 111 MSM8939_SNOC_PNOC_SLV, 112}; 113 114static const u16 bimc_snoc_mas_links[] = { 115 MSM8939_BIMC_SNOC_SLV 116}; 117 118static struct qcom_icc_node bimc_snoc_mas = { 119 .name = "bimc_snoc_mas", 120 .id = MSM8939_BIMC_SNOC_MAS, 121 .buswidth = 8, 122 .mas_rpm_id = -1, 123 .slv_rpm_id = -1, 124 .qos.ap_owned = true, 125 .qos.qos_mode = NOC_QOS_MODE_INVALID, 126 .num_links = ARRAY_SIZE(bimc_snoc_mas_links), 127 .links = bimc_snoc_mas_links, 128}; 129 130static const u16 bimc_snoc_slv_links[] = { 131 MSM8939_SNOC_INT_0, 132 MSM8939_SNOC_INT_1 133}; 134 135static struct qcom_icc_node bimc_snoc_slv = { 136 .name = "bimc_snoc_slv", 137 .id = MSM8939_BIMC_SNOC_SLV, 138 .buswidth = 16, 139 .mas_rpm_id = -1, 140 .slv_rpm_id = 2, 141 .num_links = ARRAY_SIZE(bimc_snoc_slv_links), 142 .links = bimc_snoc_slv_links, 143}; 144 145static const u16 mas_apss_links[] = { 146 MSM8939_SLAVE_EBI_CH0, 147 MSM8939_BIMC_SNOC_MAS, 148 MSM8939_SLAVE_AMPSS_L2 149}; 150 151static struct qcom_icc_node mas_apss = { 152 .name = "mas_apss", 153 .id = MSM8939_MASTER_AMPSS_M0, 154 .buswidth = 16, 155 .mas_rpm_id = -1, 156 .slv_rpm_id = -1, 157 .qos.ap_owned = true, 158 .qos.qos_mode = NOC_QOS_MODE_FIXED, 159 .qos.areq_prio = 0, 160 .qos.prio_level = 0, 161 .qos.qos_port = 0, 162 .num_links = ARRAY_SIZE(mas_apss_links), 163 .links = mas_apss_links, 164}; 165 166static const u16 mas_audio_links[] = { 167 MSM8939_PNOC_MAS_0 168}; 169 170static struct qcom_icc_node mas_audio = { 171 .name = "mas_audio", 172 .id = MSM8939_MASTER_LPASS, 173 .buswidth = 4, 174 .mas_rpm_id = -1, 175 .slv_rpm_id = -1, 176 .num_links = ARRAY_SIZE(mas_audio_links), 177 .links = mas_audio_links, 178}; 179 180static const u16 mas_blsp_1_links[] = { 181 MSM8939_PNOC_MAS_1 182}; 183 184static struct qcom_icc_node mas_blsp_1 = { 185 .name = "mas_blsp_1", 186 .id = MSM8939_MASTER_BLSP_1, 187 .buswidth = 4, 188 .mas_rpm_id = -1, 189 .slv_rpm_id = -1, 190 .num_links = ARRAY_SIZE(mas_blsp_1_links), 191 .links = mas_blsp_1_links, 192}; 193 194static const u16 mas_dehr_links[] = { 195 MSM8939_PNOC_MAS_0 196}; 197 198static struct qcom_icc_node mas_dehr = { 199 .name = "mas_dehr", 200 .id = MSM8939_MASTER_DEHR, 201 .buswidth = 4, 202 .mas_rpm_id = -1, 203 .slv_rpm_id = -1, 204 .num_links = ARRAY_SIZE(mas_dehr_links), 205 .links = mas_dehr_links, 206}; 207 208static const u16 mas_gfx_links[] = { 209 MSM8939_SLAVE_EBI_CH0, 210 MSM8939_BIMC_SNOC_MAS, 211 MSM8939_SLAVE_AMPSS_L2 212}; 213 214static struct qcom_icc_node mas_gfx = { 215 .name = "mas_gfx", 216 .id = MSM8939_MASTER_GRAPHICS_3D, 217 .buswidth = 16, 218 .mas_rpm_id = -1, 219 .slv_rpm_id = -1, 220 .qos.ap_owned = true, 221 .qos.qos_mode = NOC_QOS_MODE_FIXED, 222 .qos.areq_prio = 0, 223 .qos.prio_level = 0, 224 .qos.qos_port = 2, 225 .num_links = ARRAY_SIZE(mas_gfx_links), 226 .links = mas_gfx_links, 227}; 228 229static const u16 mas_jpeg_links[] = { 230 MSM8939_SNOC_MM_INT_0, 231 MSM8939_SNOC_MM_INT_2 232}; 233 234static struct qcom_icc_node mas_jpeg = { 235 .name = "mas_jpeg", 236 .id = MSM8939_MASTER_JPEG, 237 .buswidth = 16, 238 .mas_rpm_id = -1, 239 .slv_rpm_id = -1, 240 .qos.ap_owned = true, 241 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 242 .qos.areq_prio = 0, 243 .qos.prio_level = 0, 244 .qos.qos_port = 6, 245 .num_links = ARRAY_SIZE(mas_jpeg_links), 246 .links = mas_jpeg_links, 247}; 248 249static const u16 mas_mdp0_links[] = { 250 MSM8939_SNOC_MM_INT_1, 251 MSM8939_SNOC_MM_INT_2 252}; 253 254static struct qcom_icc_node mas_mdp0 = { 255 .name = "mas_mdp0", 256 .id = MSM8939_MASTER_MDP_PORT0, 257 .buswidth = 16, 258 .mas_rpm_id = -1, 259 .slv_rpm_id = -1, 260 .qos.ap_owned = true, 261 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 262 .qos.areq_prio = 0, 263 .qos.prio_level = 0, 264 .qos.qos_port = 7, 265 .num_links = ARRAY_SIZE(mas_mdp0_links), 266 .links = mas_mdp0_links, 267}; 268 269static const u16 mas_mdp1_links[] = { 270 MSM8939_SNOC_MM_INT_0, 271 MSM8939_SNOC_MM_INT_2 272}; 273 274static struct qcom_icc_node mas_mdp1 = { 275 .name = "mas_mdp1", 276 .id = MSM8939_MASTER_MDP_PORT1, 277 .buswidth = 16, 278 .mas_rpm_id = -1, 279 .slv_rpm_id = -1, 280 .qos.ap_owned = true, 281 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 282 .qos.areq_prio = 0, 283 .qos.prio_level = 0, 284 .qos.qos_port = 13, 285 .num_links = ARRAY_SIZE(mas_mdp1_links), 286 .links = mas_mdp1_links, 287}; 288 289static const u16 mas_cpp_links[] = { 290 MSM8939_SNOC_MM_INT_0, 291 MSM8939_SNOC_MM_INT_2 292}; 293 294static struct qcom_icc_node mas_cpp = { 295 .name = "mas_cpp", 296 .id = MSM8939_MASTER_CPP, 297 .buswidth = 16, 298 .mas_rpm_id = -1, 299 .slv_rpm_id = -1, 300 .qos.ap_owned = true, 301 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 302 .qos.areq_prio = 0, 303 .qos.prio_level = 0, 304 .qos.qos_port = 12, 305 .num_links = ARRAY_SIZE(mas_cpp_links), 306 .links = mas_cpp_links, 307}; 308 309static const u16 mas_pcnoc_crypto_0_links[] = { 310 MSM8939_PNOC_INT_1 311}; 312 313static struct qcom_icc_node mas_pcnoc_crypto_0 = { 314 .name = "mas_pcnoc_crypto_0", 315 .id = MSM8939_MASTER_CRYPTO_CORE0, 316 .buswidth = 8, 317 .mas_rpm_id = -1, 318 .slv_rpm_id = -1, 319 .num_links = ARRAY_SIZE(mas_pcnoc_crypto_0_links), 320 .links = mas_pcnoc_crypto_0_links, 321}; 322 323static const u16 mas_pcnoc_sdcc_1_links[] = { 324 MSM8939_PNOC_INT_1 325}; 326 327static struct qcom_icc_node mas_pcnoc_sdcc_1 = { 328 .name = "mas_pcnoc_sdcc_1", 329 .id = MSM8939_MASTER_SDCC_1, 330 .buswidth = 8, 331 .mas_rpm_id = -1, 332 .slv_rpm_id = -1, 333 .num_links = ARRAY_SIZE(mas_pcnoc_sdcc_1_links), 334 .links = mas_pcnoc_sdcc_1_links, 335}; 336 337static const u16 mas_pcnoc_sdcc_2_links[] = { 338 MSM8939_PNOC_INT_1 339}; 340 341static struct qcom_icc_node mas_pcnoc_sdcc_2 = { 342 .name = "mas_pcnoc_sdcc_2", 343 .id = MSM8939_MASTER_SDCC_2, 344 .buswidth = 8, 345 .mas_rpm_id = -1, 346 .slv_rpm_id = -1, 347 .num_links = ARRAY_SIZE(mas_pcnoc_sdcc_2_links), 348 .links = mas_pcnoc_sdcc_2_links, 349}; 350 351static const u16 mas_qdss_bam_links[] = { 352 MSM8939_SNOC_QDSS_INT 353}; 354 355static struct qcom_icc_node mas_qdss_bam = { 356 .name = "mas_qdss_bam", 357 .id = MSM8939_MASTER_QDSS_BAM, 358 .buswidth = 8, 359 .mas_rpm_id = -1, 360 .slv_rpm_id = -1, 361 .qos.ap_owned = true, 362 .qos.qos_mode = NOC_QOS_MODE_FIXED, 363 .qos.areq_prio = 1, 364 .qos.prio_level = 1, 365 .qos.qos_port = 11, 366 .num_links = ARRAY_SIZE(mas_qdss_bam_links), 367 .links = mas_qdss_bam_links, 368}; 369 370static const u16 mas_qdss_etr_links[] = { 371 MSM8939_SNOC_QDSS_INT 372}; 373 374static struct qcom_icc_node mas_qdss_etr = { 375 .name = "mas_qdss_etr", 376 .id = MSM8939_MASTER_QDSS_ETR, 377 .buswidth = 8, 378 .mas_rpm_id = -1, 379 .slv_rpm_id = -1, 380 .qos.ap_owned = true, 381 .qos.qos_mode = NOC_QOS_MODE_FIXED, 382 .qos.areq_prio = 1, 383 .qos.prio_level = 1, 384 .qos.qos_port = 10, 385 .num_links = ARRAY_SIZE(mas_qdss_etr_links), 386 .links = mas_qdss_etr_links, 387}; 388 389static const u16 mas_snoc_cfg_links[] = { 390 MSM8939_SLAVE_SRVC_SNOC 391}; 392 393static struct qcom_icc_node mas_snoc_cfg = { 394 .name = "mas_snoc_cfg", 395 .id = MSM8939_MASTER_SNOC_CFG, 396 .buswidth = 4, 397 .mas_rpm_id = -1, 398 .slv_rpm_id = -1, 399 .num_links = ARRAY_SIZE(mas_snoc_cfg_links), 400 .links = mas_snoc_cfg_links, 401}; 402 403static const u16 mas_spdm_links[] = { 404 MSM8939_PNOC_MAS_0 405}; 406 407static struct qcom_icc_node mas_spdm = { 408 .name = "mas_spdm", 409 .id = MSM8939_MASTER_SPDM, 410 .buswidth = 4, 411 .mas_rpm_id = -1, 412 .slv_rpm_id = -1, 413 .num_links = ARRAY_SIZE(mas_spdm_links), 414 .links = mas_spdm_links, 415}; 416 417static const u16 mas_tcu0_links[] = { 418 MSM8939_SLAVE_EBI_CH0, 419 MSM8939_BIMC_SNOC_MAS, 420 MSM8939_SLAVE_AMPSS_L2 421}; 422 423static struct qcom_icc_node mas_tcu0 = { 424 .name = "mas_tcu0", 425 .id = MSM8939_MASTER_TCU0, 426 .buswidth = 16, 427 .mas_rpm_id = -1, 428 .slv_rpm_id = -1, 429 .qos.ap_owned = true, 430 .qos.qos_mode = NOC_QOS_MODE_FIXED, 431 .qos.areq_prio = 2, 432 .qos.prio_level = 2, 433 .qos.qos_port = 6, 434 .num_links = ARRAY_SIZE(mas_tcu0_links), 435 .links = mas_tcu0_links, 436}; 437 438static const u16 mas_usb_hs1_links[] = { 439 MSM8939_PNOC_MAS_1 440}; 441 442static struct qcom_icc_node mas_usb_hs1 = { 443 .name = "mas_usb_hs1", 444 .id = MSM8939_MASTER_USB_HS1, 445 .buswidth = 4, 446 .mas_rpm_id = -1, 447 .slv_rpm_id = -1, 448 .num_links = ARRAY_SIZE(mas_usb_hs1_links), 449 .links = mas_usb_hs1_links, 450}; 451 452static const u16 mas_usb_hs2_links[] = { 453 MSM8939_PNOC_MAS_1 454}; 455 456static struct qcom_icc_node mas_usb_hs2 = { 457 .name = "mas_usb_hs2", 458 .id = MSM8939_MASTER_USB_HS2, 459 .buswidth = 4, 460 .mas_rpm_id = -1, 461 .slv_rpm_id = -1, 462 .num_links = ARRAY_SIZE(mas_usb_hs2_links), 463 .links = mas_usb_hs2_links, 464}; 465 466static const u16 mas_vfe_links[] = { 467 MSM8939_SNOC_MM_INT_1, 468 MSM8939_SNOC_MM_INT_2 469}; 470 471static struct qcom_icc_node mas_vfe = { 472 .name = "mas_vfe", 473 .id = MSM8939_MASTER_VFE, 474 .buswidth = 16, 475 .mas_rpm_id = -1, 476 .slv_rpm_id = -1, 477 .qos.ap_owned = true, 478 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 479 .qos.areq_prio = 0, 480 .qos.prio_level = 0, 481 .qos.qos_port = 9, 482 .num_links = ARRAY_SIZE(mas_vfe_links), 483 .links = mas_vfe_links, 484}; 485 486static const u16 mas_video_links[] = { 487 MSM8939_SNOC_MM_INT_0, 488 MSM8939_SNOC_MM_INT_2 489}; 490 491static struct qcom_icc_node mas_video = { 492 .name = "mas_video", 493 .id = MSM8939_MASTER_VIDEO_P0, 494 .buswidth = 16, 495 .mas_rpm_id = -1, 496 .slv_rpm_id = -1, 497 .qos.ap_owned = true, 498 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 499 .qos.areq_prio = 0, 500 .qos.prio_level = 0, 501 .qos.qos_port = 8, 502 .num_links = ARRAY_SIZE(mas_video_links), 503 .links = mas_video_links, 504}; 505 506static const u16 mm_int_0_links[] = { 507 MSM8939_SNOC_BIMC_2_MAS 508}; 509 510static struct qcom_icc_node mm_int_0 = { 511 .name = "mm_int_0", 512 .id = MSM8939_SNOC_MM_INT_0, 513 .buswidth = 16, 514 .mas_rpm_id = -1, 515 .slv_rpm_id = -1, 516 .qos.ap_owned = true, 517 .qos.qos_mode = NOC_QOS_MODE_INVALID, 518 .num_links = ARRAY_SIZE(mm_int_0_links), 519 .links = mm_int_0_links, 520}; 521 522static const u16 mm_int_1_links[] = { 523 MSM8939_SNOC_BIMC_1_MAS 524}; 525 526static struct qcom_icc_node mm_int_1 = { 527 .name = "mm_int_1", 528 .id = MSM8939_SNOC_MM_INT_1, 529 .buswidth = 16, 530 .mas_rpm_id = -1, 531 .slv_rpm_id = -1, 532 .qos.ap_owned = true, 533 .qos.qos_mode = NOC_QOS_MODE_INVALID, 534 .num_links = ARRAY_SIZE(mm_int_1_links), 535 .links = mm_int_1_links, 536}; 537 538static const u16 mm_int_2_links[] = { 539 MSM8939_SNOC_INT_0 540}; 541 542static struct qcom_icc_node mm_int_2 = { 543 .name = "mm_int_2", 544 .id = MSM8939_SNOC_MM_INT_2, 545 .buswidth = 16, 546 .mas_rpm_id = -1, 547 .slv_rpm_id = -1, 548 .qos.ap_owned = true, 549 .qos.qos_mode = NOC_QOS_MODE_INVALID, 550 .num_links = ARRAY_SIZE(mm_int_2_links), 551 .links = mm_int_2_links, 552}; 553 554static const u16 pcnoc_int_0_links[] = { 555 MSM8939_PNOC_SNOC_MAS, 556 MSM8939_PNOC_SLV_0, 557 MSM8939_PNOC_SLV_1, 558 MSM8939_PNOC_SLV_2, 559 MSM8939_PNOC_SLV_3, 560 MSM8939_PNOC_SLV_4, 561 MSM8939_PNOC_SLV_8, 562 MSM8939_PNOC_SLV_9 563}; 564 565static struct qcom_icc_node pcnoc_int_0 = { 566 .name = "pcnoc_int_0", 567 .id = MSM8939_PNOC_INT_0, 568 .buswidth = 8, 569 .mas_rpm_id = -1, 570 .slv_rpm_id = -1, 571 .num_links = ARRAY_SIZE(pcnoc_int_0_links), 572 .links = pcnoc_int_0_links, 573}; 574 575static const u16 pcnoc_int_1_links[] = { 576 MSM8939_PNOC_SNOC_MAS 577}; 578 579static struct qcom_icc_node pcnoc_int_1 = { 580 .name = "pcnoc_int_1", 581 .id = MSM8939_PNOC_INT_1, 582 .buswidth = 8, 583 .mas_rpm_id = -1, 584 .slv_rpm_id = -1, 585 .num_links = ARRAY_SIZE(pcnoc_int_1_links), 586 .links = pcnoc_int_1_links, 587}; 588 589static const u16 pcnoc_m_0_links[] = { 590 MSM8939_PNOC_INT_0 591}; 592 593static struct qcom_icc_node pcnoc_m_0 = { 594 .name = "pcnoc_m_0", 595 .id = MSM8939_PNOC_MAS_0, 596 .buswidth = 8, 597 .mas_rpm_id = -1, 598 .slv_rpm_id = -1, 599 .num_links = ARRAY_SIZE(pcnoc_m_0_links), 600 .links = pcnoc_m_0_links, 601}; 602 603static const u16 pcnoc_m_1_links[] = { 604 MSM8939_PNOC_SNOC_MAS 605}; 606 607static struct qcom_icc_node pcnoc_m_1 = { 608 .name = "pcnoc_m_1", 609 .id = MSM8939_PNOC_MAS_1, 610 .buswidth = 8, 611 .mas_rpm_id = -1, 612 .slv_rpm_id = -1, 613 .num_links = ARRAY_SIZE(pcnoc_m_1_links), 614 .links = pcnoc_m_1_links, 615}; 616 617static const u16 pcnoc_s_0_links[] = { 618 MSM8939_SLAVE_CLK_CTL, 619 MSM8939_SLAVE_TLMM, 620 MSM8939_SLAVE_TCSR, 621 MSM8939_SLAVE_SECURITY, 622 MSM8939_SLAVE_MSS 623}; 624 625static struct qcom_icc_node pcnoc_s_0 = { 626 .name = "pcnoc_s_0", 627 .id = MSM8939_PNOC_SLV_0, 628 .buswidth = 4, 629 .mas_rpm_id = -1, 630 .slv_rpm_id = -1, 631 .num_links = ARRAY_SIZE(pcnoc_s_0_links), 632 .links = pcnoc_s_0_links, 633}; 634 635static const u16 pcnoc_s_1_links[] = { 636 MSM8939_SLAVE_IMEM_CFG, 637 MSM8939_SLAVE_CRYPTO_0_CFG, 638 MSM8939_SLAVE_MSG_RAM, 639 MSM8939_SLAVE_PDM, 640 MSM8939_SLAVE_PRNG 641}; 642 643static struct qcom_icc_node pcnoc_s_1 = { 644 .name = "pcnoc_s_1", 645 .id = MSM8939_PNOC_SLV_1, 646 .buswidth = 4, 647 .mas_rpm_id = -1, 648 .slv_rpm_id = -1, 649 .num_links = ARRAY_SIZE(pcnoc_s_1_links), 650 .links = pcnoc_s_1_links, 651}; 652 653static const u16 pcnoc_s_2_links[] = { 654 MSM8939_SLAVE_SPDM, 655 MSM8939_SLAVE_BOOT_ROM, 656 MSM8939_SLAVE_BIMC_CFG, 657 MSM8939_SLAVE_PNOC_CFG, 658 MSM8939_SLAVE_PMIC_ARB 659}; 660 661static struct qcom_icc_node pcnoc_s_2 = { 662 .name = "pcnoc_s_2", 663 .id = MSM8939_PNOC_SLV_2, 664 .buswidth = 4, 665 .mas_rpm_id = -1, 666 .slv_rpm_id = -1, 667 .num_links = ARRAY_SIZE(pcnoc_s_2_links), 668 .links = pcnoc_s_2_links, 669}; 670 671static const u16 pcnoc_s_3_links[] = { 672 MSM8939_SLAVE_MPM, 673 MSM8939_SLAVE_SNOC_CFG, 674 MSM8939_SLAVE_RBCPR_CFG, 675 MSM8939_SLAVE_QDSS_CFG, 676 MSM8939_SLAVE_DEHR_CFG 677}; 678 679static struct qcom_icc_node pcnoc_s_3 = { 680 .name = "pcnoc_s_3", 681 .id = MSM8939_PNOC_SLV_3, 682 .buswidth = 4, 683 .mas_rpm_id = -1, 684 .slv_rpm_id = -1, 685 .num_links = ARRAY_SIZE(pcnoc_s_3_links), 686 .links = pcnoc_s_3_links, 687}; 688 689static const u16 pcnoc_s_4_links[] = { 690 MSM8939_SLAVE_VENUS_CFG, 691 MSM8939_SLAVE_CAMERA_CFG, 692 MSM8939_SLAVE_DISPLAY_CFG 693}; 694 695static struct qcom_icc_node pcnoc_s_4 = { 696 .name = "pcnoc_s_4", 697 .id = MSM8939_PNOC_SLV_4, 698 .buswidth = 4, 699 .mas_rpm_id = -1, 700 .slv_rpm_id = -1, 701 .num_links = ARRAY_SIZE(pcnoc_s_4_links), 702 .links = pcnoc_s_4_links, 703}; 704 705static const u16 pcnoc_s_8_links[] = { 706 MSM8939_SLAVE_USB_HS1, 707 MSM8939_SLAVE_SDCC_1, 708 MSM8939_SLAVE_BLSP_1 709}; 710 711static struct qcom_icc_node pcnoc_s_8 = { 712 .name = "pcnoc_s_8", 713 .id = MSM8939_PNOC_SLV_8, 714 .buswidth = 4, 715 .mas_rpm_id = -1, 716 .slv_rpm_id = -1, 717 .num_links = ARRAY_SIZE(pcnoc_s_8_links), 718 .links = pcnoc_s_8_links, 719}; 720 721static const u16 pcnoc_s_9_links[] = { 722 MSM8939_SLAVE_SDCC_2, 723 MSM8939_SLAVE_LPASS, 724 MSM8939_SLAVE_USB_HS2 725}; 726 727static struct qcom_icc_node pcnoc_s_9 = { 728 .name = "pcnoc_s_9", 729 .id = MSM8939_PNOC_SLV_9, 730 .buswidth = 4, 731 .mas_rpm_id = -1, 732 .slv_rpm_id = -1, 733 .num_links = ARRAY_SIZE(pcnoc_s_9_links), 734 .links = pcnoc_s_9_links, 735}; 736 737static const u16 pcnoc_snoc_mas_links[] = { 738 MSM8939_PNOC_SNOC_SLV 739}; 740 741static struct qcom_icc_node pcnoc_snoc_mas = { 742 .name = "pcnoc_snoc_mas", 743 .id = MSM8939_PNOC_SNOC_MAS, 744 .buswidth = 8, 745 .mas_rpm_id = 29, 746 .slv_rpm_id = -1, 747 .num_links = ARRAY_SIZE(pcnoc_snoc_mas_links), 748 .links = pcnoc_snoc_mas_links, 749}; 750 751static const u16 pcnoc_snoc_slv_links[] = { 752 MSM8939_SNOC_INT_0, 753 MSM8939_SNOC_INT_BIMC, 754 MSM8939_SNOC_INT_1 755}; 756 757static struct qcom_icc_node pcnoc_snoc_slv = { 758 .name = "pcnoc_snoc_slv", 759 .id = MSM8939_PNOC_SNOC_SLV, 760 .buswidth = 8, 761 .mas_rpm_id = -1, 762 .slv_rpm_id = 45, 763 .num_links = ARRAY_SIZE(pcnoc_snoc_slv_links), 764 .links = pcnoc_snoc_slv_links, 765}; 766 767static const u16 qdss_int_links[] = { 768 MSM8939_SNOC_INT_0, 769 MSM8939_SNOC_INT_BIMC 770}; 771 772static struct qcom_icc_node qdss_int = { 773 .name = "qdss_int", 774 .id = MSM8939_SNOC_QDSS_INT, 775 .buswidth = 8, 776 .mas_rpm_id = -1, 777 .slv_rpm_id = -1, 778 .qos.ap_owned = true, 779 .qos.qos_mode = NOC_QOS_MODE_INVALID, 780 .num_links = ARRAY_SIZE(qdss_int_links), 781 .links = qdss_int_links, 782}; 783 784static struct qcom_icc_node slv_apps_l2 = { 785 .name = "slv_apps_l2", 786 .id = MSM8939_SLAVE_AMPSS_L2, 787 .buswidth = 16, 788 .mas_rpm_id = -1, 789 .slv_rpm_id = -1, 790}; 791 792static struct qcom_icc_node slv_apss = { 793 .name = "slv_apss", 794 .id = MSM8939_SLAVE_APSS, 795 .buswidth = 4, 796 .mas_rpm_id = -1, 797 .slv_rpm_id = -1, 798}; 799 800static struct qcom_icc_node slv_audio = { 801 .name = "slv_audio", 802 .id = MSM8939_SLAVE_LPASS, 803 .buswidth = 4, 804 .mas_rpm_id = -1, 805 .slv_rpm_id = -1, 806}; 807 808static struct qcom_icc_node slv_bimc_cfg = { 809 .name = "slv_bimc_cfg", 810 .id = MSM8939_SLAVE_BIMC_CFG, 811 .buswidth = 4, 812 .mas_rpm_id = -1, 813 .slv_rpm_id = -1, 814}; 815 816static struct qcom_icc_node slv_blsp_1 = { 817 .name = "slv_blsp_1", 818 .id = MSM8939_SLAVE_BLSP_1, 819 .buswidth = 4, 820 .mas_rpm_id = -1, 821 .slv_rpm_id = -1, 822}; 823 824static struct qcom_icc_node slv_boot_rom = { 825 .name = "slv_boot_rom", 826 .id = MSM8939_SLAVE_BOOT_ROM, 827 .buswidth = 4, 828 .mas_rpm_id = -1, 829 .slv_rpm_id = -1, 830}; 831 832static struct qcom_icc_node slv_camera_cfg = { 833 .name = "slv_camera_cfg", 834 .id = MSM8939_SLAVE_CAMERA_CFG, 835 .buswidth = 4, 836 .mas_rpm_id = -1, 837 .slv_rpm_id = -1, 838}; 839 840static struct qcom_icc_node slv_cats_0 = { 841 .name = "slv_cats_0", 842 .id = MSM8939_SLAVE_CATS_128, 843 .buswidth = 16, 844 .mas_rpm_id = -1, 845 .slv_rpm_id = -1, 846}; 847 848static struct qcom_icc_node slv_cats_1 = { 849 .name = "slv_cats_1", 850 .id = MSM8939_SLAVE_OCMEM_64, 851 .buswidth = 8, 852 .mas_rpm_id = -1, 853 .slv_rpm_id = -1, 854}; 855 856static struct qcom_icc_node slv_clk_ctl = { 857 .name = "slv_clk_ctl", 858 .id = MSM8939_SLAVE_CLK_CTL, 859 .buswidth = 4, 860 .mas_rpm_id = -1, 861 .slv_rpm_id = -1, 862}; 863 864static struct qcom_icc_node slv_crypto_0_cfg = { 865 .name = "slv_crypto_0_cfg", 866 .id = MSM8939_SLAVE_CRYPTO_0_CFG, 867 .buswidth = 4, 868 .mas_rpm_id = -1, 869 .slv_rpm_id = -1, 870}; 871 872static struct qcom_icc_node slv_dehr_cfg = { 873 .name = "slv_dehr_cfg", 874 .id = MSM8939_SLAVE_DEHR_CFG, 875 .buswidth = 4, 876 .mas_rpm_id = -1, 877 .slv_rpm_id = -1, 878}; 879 880static struct qcom_icc_node slv_display_cfg = { 881 .name = "slv_display_cfg", 882 .id = MSM8939_SLAVE_DISPLAY_CFG, 883 .buswidth = 4, 884 .mas_rpm_id = -1, 885 .slv_rpm_id = -1, 886}; 887 888static struct qcom_icc_node slv_ebi_ch0 = { 889 .name = "slv_ebi_ch0", 890 .id = MSM8939_SLAVE_EBI_CH0, 891 .buswidth = 16, 892 .mas_rpm_id = -1, 893 .slv_rpm_id = 0, 894}; 895 896static struct qcom_icc_node slv_gfx_cfg = { 897 .name = "slv_gfx_cfg", 898 .id = MSM8939_SLAVE_GRAPHICS_3D_CFG, 899 .buswidth = 4, 900 .mas_rpm_id = -1, 901 .slv_rpm_id = -1, 902}; 903 904static struct qcom_icc_node slv_imem_cfg = { 905 .name = "slv_imem_cfg", 906 .id = MSM8939_SLAVE_IMEM_CFG, 907 .buswidth = 4, 908 .mas_rpm_id = -1, 909 .slv_rpm_id = -1, 910}; 911 912static struct qcom_icc_node slv_imem = { 913 .name = "slv_imem", 914 .id = MSM8939_SLAVE_IMEM, 915 .buswidth = 8, 916 .mas_rpm_id = -1, 917 .slv_rpm_id = 26, 918}; 919 920static struct qcom_icc_node slv_mpm = { 921 .name = "slv_mpm", 922 .id = MSM8939_SLAVE_MPM, 923 .buswidth = 4, 924 .mas_rpm_id = -1, 925 .slv_rpm_id = -1, 926}; 927 928static struct qcom_icc_node slv_msg_ram = { 929 .name = "slv_msg_ram", 930 .id = MSM8939_SLAVE_MSG_RAM, 931 .buswidth = 4, 932 .mas_rpm_id = -1, 933 .slv_rpm_id = -1, 934}; 935 936static struct qcom_icc_node slv_mss = { 937 .name = "slv_mss", 938 .id = MSM8939_SLAVE_MSS, 939 .buswidth = 4, 940 .mas_rpm_id = -1, 941 .slv_rpm_id = -1, 942}; 943 944static struct qcom_icc_node slv_pdm = { 945 .name = "slv_pdm", 946 .id = MSM8939_SLAVE_PDM, 947 .buswidth = 4, 948 .mas_rpm_id = -1, 949 .slv_rpm_id = -1, 950}; 951 952static struct qcom_icc_node slv_pmic_arb = { 953 .name = "slv_pmic_arb", 954 .id = MSM8939_SLAVE_PMIC_ARB, 955 .buswidth = 4, 956 .mas_rpm_id = -1, 957 .slv_rpm_id = -1, 958}; 959 960static struct qcom_icc_node slv_pcnoc_cfg = { 961 .name = "slv_pcnoc_cfg", 962 .id = MSM8939_SLAVE_PNOC_CFG, 963 .buswidth = 4, 964 .mas_rpm_id = -1, 965 .slv_rpm_id = -1, 966}; 967 968static struct qcom_icc_node slv_prng = { 969 .name = "slv_prng", 970 .id = MSM8939_SLAVE_PRNG, 971 .buswidth = 4, 972 .mas_rpm_id = -1, 973 .slv_rpm_id = -1, 974}; 975 976static struct qcom_icc_node slv_qdss_cfg = { 977 .name = "slv_qdss_cfg", 978 .id = MSM8939_SLAVE_QDSS_CFG, 979 .buswidth = 4, 980 .mas_rpm_id = -1, 981 .slv_rpm_id = -1, 982}; 983 984static struct qcom_icc_node slv_qdss_stm = { 985 .name = "slv_qdss_stm", 986 .id = MSM8939_SLAVE_QDSS_STM, 987 .buswidth = 4, 988 .mas_rpm_id = -1, 989 .slv_rpm_id = 30, 990}; 991 992static struct qcom_icc_node slv_rbcpr_cfg = { 993 .name = "slv_rbcpr_cfg", 994 .id = MSM8939_SLAVE_RBCPR_CFG, 995 .buswidth = 4, 996 .mas_rpm_id = -1, 997 .slv_rpm_id = -1, 998}; 999 1000static struct qcom_icc_node slv_sdcc_1 = { 1001 .name = "slv_sdcc_1", 1002 .id = MSM8939_SLAVE_SDCC_1, 1003 .buswidth = 4, 1004 .mas_rpm_id = -1, 1005 .slv_rpm_id = -1, 1006}; 1007 1008static struct qcom_icc_node slv_sdcc_2 = { 1009 .name = "slv_sdcc_2", 1010 .id = MSM8939_SLAVE_SDCC_2, 1011 .buswidth = 4, 1012 .mas_rpm_id = -1, 1013 .slv_rpm_id = -1, 1014}; 1015 1016static struct qcom_icc_node slv_security = { 1017 .name = "slv_security", 1018 .id = MSM8939_SLAVE_SECURITY, 1019 .buswidth = 4, 1020 .mas_rpm_id = -1, 1021 .slv_rpm_id = -1, 1022}; 1023 1024static struct qcom_icc_node slv_snoc_cfg = { 1025 .name = "slv_snoc_cfg", 1026 .id = MSM8939_SLAVE_SNOC_CFG, 1027 .buswidth = 4, 1028 .mas_rpm_id = -1, 1029 .slv_rpm_id = -1, 1030}; 1031 1032static struct qcom_icc_node slv_spdm = { 1033 .name = "slv_spdm", 1034 .id = MSM8939_SLAVE_SPDM, 1035 .buswidth = 4, 1036 .mas_rpm_id = -1, 1037 .slv_rpm_id = -1, 1038}; 1039 1040static struct qcom_icc_node slv_srvc_snoc = { 1041 .name = "slv_srvc_snoc", 1042 .id = MSM8939_SLAVE_SRVC_SNOC, 1043 .buswidth = 8, 1044 .mas_rpm_id = -1, 1045 .slv_rpm_id = -1, 1046}; 1047 1048static struct qcom_icc_node slv_tcsr = { 1049 .name = "slv_tcsr", 1050 .id = MSM8939_SLAVE_TCSR, 1051 .buswidth = 4, 1052 .mas_rpm_id = -1, 1053 .slv_rpm_id = -1, 1054}; 1055 1056static struct qcom_icc_node slv_tlmm = { 1057 .name = "slv_tlmm", 1058 .id = MSM8939_SLAVE_TLMM, 1059 .buswidth = 4, 1060 .mas_rpm_id = -1, 1061 .slv_rpm_id = -1, 1062}; 1063 1064static struct qcom_icc_node slv_usb_hs1 = { 1065 .name = "slv_usb_hs1", 1066 .id = MSM8939_SLAVE_USB_HS1, 1067 .buswidth = 4, 1068 .mas_rpm_id = -1, 1069 .slv_rpm_id = -1, 1070}; 1071 1072static struct qcom_icc_node slv_usb_hs2 = { 1073 .name = "slv_usb_hs2", 1074 .id = MSM8939_SLAVE_USB_HS2, 1075 .buswidth = 4, 1076 .mas_rpm_id = -1, 1077 .slv_rpm_id = -1, 1078}; 1079 1080static struct qcom_icc_node slv_venus_cfg = { 1081 .name = "slv_venus_cfg", 1082 .id = MSM8939_SLAVE_VENUS_CFG, 1083 .buswidth = 4, 1084 .mas_rpm_id = -1, 1085 .slv_rpm_id = -1, 1086}; 1087 1088static const u16 snoc_bimc_0_mas_links[] = { 1089 MSM8939_SNOC_BIMC_0_SLV 1090}; 1091 1092static struct qcom_icc_node snoc_bimc_0_mas = { 1093 .name = "snoc_bimc_0_mas", 1094 .id = MSM8939_SNOC_BIMC_0_MAS, 1095 .buswidth = 16, 1096 .mas_rpm_id = -1, 1097 .slv_rpm_id = -1, 1098 .qos.ap_owned = true, 1099 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1100 .num_links = ARRAY_SIZE(snoc_bimc_0_mas_links), 1101 .links = snoc_bimc_0_mas_links, 1102}; 1103 1104static const u16 snoc_bimc_0_slv_links[] = { 1105 MSM8939_SLAVE_EBI_CH0 1106}; 1107 1108static struct qcom_icc_node snoc_bimc_0_slv = { 1109 .name = "snoc_bimc_0_slv", 1110 .id = MSM8939_SNOC_BIMC_0_SLV, 1111 .buswidth = 16, 1112 .mas_rpm_id = -1, 1113 .slv_rpm_id = -1, 1114 .qos.ap_owned = true, 1115 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1116 .num_links = ARRAY_SIZE(snoc_bimc_0_slv_links), 1117 .links = snoc_bimc_0_slv_links, 1118}; 1119 1120static const u16 snoc_bimc_1_mas_links[] = { 1121 MSM8939_SNOC_BIMC_1_SLV 1122}; 1123 1124static struct qcom_icc_node snoc_bimc_1_mas = { 1125 .name = "snoc_bimc_1_mas", 1126 .id = MSM8939_SNOC_BIMC_1_MAS, 1127 .buswidth = 16, 1128 .mas_rpm_id = 76, 1129 .slv_rpm_id = -1, 1130 .num_links = ARRAY_SIZE(snoc_bimc_1_mas_links), 1131 .links = snoc_bimc_1_mas_links, 1132}; 1133 1134static const u16 snoc_bimc_1_slv_links[] = { 1135 MSM8939_SLAVE_EBI_CH0 1136}; 1137 1138static struct qcom_icc_node snoc_bimc_1_slv = { 1139 .name = "snoc_bimc_1_slv", 1140 .id = MSM8939_SNOC_BIMC_1_SLV, 1141 .buswidth = 16, 1142 .mas_rpm_id = -1, 1143 .slv_rpm_id = 104, 1144 .num_links = ARRAY_SIZE(snoc_bimc_1_slv_links), 1145 .links = snoc_bimc_1_slv_links, 1146}; 1147 1148static const u16 snoc_bimc_2_mas_links[] = { 1149 MSM8939_SNOC_BIMC_2_SLV 1150}; 1151 1152static struct qcom_icc_node snoc_bimc_2_mas = { 1153 .name = "snoc_bimc_2_mas", 1154 .id = MSM8939_SNOC_BIMC_2_MAS, 1155 .buswidth = 16, 1156 .mas_rpm_id = -1, 1157 .slv_rpm_id = -1, 1158 .qos.ap_owned = true, 1159 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1160 .num_links = ARRAY_SIZE(snoc_bimc_2_mas_links), 1161 .links = snoc_bimc_2_mas_links, 1162}; 1163 1164static const u16 snoc_bimc_2_slv_links[] = { 1165 MSM8939_SLAVE_EBI_CH0 1166}; 1167 1168static struct qcom_icc_node snoc_bimc_2_slv = { 1169 .name = "snoc_bimc_2_slv", 1170 .id = MSM8939_SNOC_BIMC_2_SLV, 1171 .buswidth = 16, 1172 .mas_rpm_id = -1, 1173 .slv_rpm_id = -1, 1174 .qos.ap_owned = true, 1175 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1176 .num_links = ARRAY_SIZE(snoc_bimc_2_slv_links), 1177 .links = snoc_bimc_2_slv_links, 1178}; 1179 1180static const u16 snoc_int_0_links[] = { 1181 MSM8939_SLAVE_QDSS_STM, 1182 MSM8939_SLAVE_IMEM, 1183 MSM8939_SNOC_PNOC_MAS 1184}; 1185 1186static struct qcom_icc_node snoc_int_0 = { 1187 .name = "snoc_int_0", 1188 .id = MSM8939_SNOC_INT_0, 1189 .buswidth = 8, 1190 .mas_rpm_id = 99, 1191 .slv_rpm_id = 130, 1192 .num_links = ARRAY_SIZE(snoc_int_0_links), 1193 .links = snoc_int_0_links, 1194}; 1195 1196static const u16 snoc_int_1_links[] = { 1197 MSM8939_SLAVE_APSS, 1198 MSM8939_SLAVE_CATS_128, 1199 MSM8939_SLAVE_OCMEM_64 1200}; 1201 1202static struct qcom_icc_node snoc_int_1 = { 1203 .name = "snoc_int_1", 1204 .id = MSM8939_SNOC_INT_1, 1205 .buswidth = 8, 1206 .mas_rpm_id = -1, 1207 .slv_rpm_id = -1, 1208 .num_links = ARRAY_SIZE(snoc_int_1_links), 1209 .links = snoc_int_1_links, 1210}; 1211 1212static const u16 snoc_int_bimc_links[] = { 1213 MSM8939_SNOC_BIMC_1_MAS 1214}; 1215 1216static struct qcom_icc_node snoc_int_bimc = { 1217 .name = "snoc_int_bimc", 1218 .id = MSM8939_SNOC_INT_BIMC, 1219 .buswidth = 8, 1220 .mas_rpm_id = 101, 1221 .slv_rpm_id = 132, 1222 .num_links = ARRAY_SIZE(snoc_int_bimc_links), 1223 .links = snoc_int_bimc_links, 1224}; 1225 1226static const u16 snoc_pcnoc_mas_links[] = { 1227 MSM8939_SNOC_PNOC_SLV 1228}; 1229 1230static struct qcom_icc_node snoc_pcnoc_mas = { 1231 .name = "snoc_pcnoc_mas", 1232 .id = MSM8939_SNOC_PNOC_MAS, 1233 .buswidth = 8, 1234 .mas_rpm_id = -1, 1235 .slv_rpm_id = -1, 1236 .num_links = ARRAY_SIZE(snoc_pcnoc_mas_links), 1237 .links = snoc_pcnoc_mas_links, 1238}; 1239 1240static const u16 snoc_pcnoc_slv_links[] = { 1241 MSM8939_PNOC_INT_0 1242}; 1243 1244static struct qcom_icc_node snoc_pcnoc_slv = { 1245 .name = "snoc_pcnoc_slv", 1246 .id = MSM8939_SNOC_PNOC_SLV, 1247 .buswidth = 8, 1248 .mas_rpm_id = -1, 1249 .slv_rpm_id = -1, 1250 .num_links = ARRAY_SIZE(snoc_pcnoc_slv_links), 1251 .links = snoc_pcnoc_slv_links, 1252}; 1253 1254static struct qcom_icc_node * const msm8939_snoc_nodes[] = { 1255 [BIMC_SNOC_SLV] = &bimc_snoc_slv, 1256 [MASTER_QDSS_BAM] = &mas_qdss_bam, 1257 [MASTER_QDSS_ETR] = &mas_qdss_etr, 1258 [MASTER_SNOC_CFG] = &mas_snoc_cfg, 1259 [PCNOC_SNOC_SLV] = &pcnoc_snoc_slv, 1260 [SLAVE_APSS] = &slv_apss, 1261 [SLAVE_CATS_128] = &slv_cats_0, 1262 [SLAVE_OCMEM_64] = &slv_cats_1, 1263 [SLAVE_IMEM] = &slv_imem, 1264 [SLAVE_QDSS_STM] = &slv_qdss_stm, 1265 [SLAVE_SRVC_SNOC] = &slv_srvc_snoc, 1266 [SNOC_BIMC_0_MAS] = &snoc_bimc_0_mas, 1267 [SNOC_BIMC_1_MAS] = &snoc_bimc_1_mas, 1268 [SNOC_BIMC_2_MAS] = &snoc_bimc_2_mas, 1269 [SNOC_INT_0] = &snoc_int_0, 1270 [SNOC_INT_1] = &snoc_int_1, 1271 [SNOC_INT_BIMC] = &snoc_int_bimc, 1272 [SNOC_PCNOC_MAS] = &snoc_pcnoc_mas, 1273 [SNOC_QDSS_INT] = &qdss_int, 1274}; 1275 1276static const struct regmap_config msm8939_snoc_regmap_config = { 1277 .reg_bits = 32, 1278 .reg_stride = 4, 1279 .val_bits = 32, 1280 .max_register = 0x14080, 1281 .fast_io = true, 1282}; 1283 1284static const struct qcom_icc_desc msm8939_snoc = { 1285 .type = QCOM_ICC_NOC, 1286 .nodes = msm8939_snoc_nodes, 1287 .num_nodes = ARRAY_SIZE(msm8939_snoc_nodes), 1288 .regmap_cfg = &msm8939_snoc_regmap_config, 1289 .qos_offset = 0x7000, 1290}; 1291 1292static struct qcom_icc_node * const msm8939_snoc_mm_nodes[] = { 1293 [MASTER_VIDEO_P0] = &mas_video, 1294 [MASTER_JPEG] = &mas_jpeg, 1295 [MASTER_VFE] = &mas_vfe, 1296 [MASTER_MDP_PORT0] = &mas_mdp0, 1297 [MASTER_MDP_PORT1] = &mas_mdp1, 1298 [MASTER_CPP] = &mas_cpp, 1299 [SNOC_MM_INT_0] = &mm_int_0, 1300 [SNOC_MM_INT_1] = &mm_int_1, 1301 [SNOC_MM_INT_2] = &mm_int_2, 1302}; 1303 1304static const struct qcom_icc_desc msm8939_snoc_mm = { 1305 .type = QCOM_ICC_NOC, 1306 .nodes = msm8939_snoc_mm_nodes, 1307 .num_nodes = ARRAY_SIZE(msm8939_snoc_mm_nodes), 1308 .regmap_cfg = &msm8939_snoc_regmap_config, 1309 .qos_offset = 0x7000, 1310}; 1311 1312static struct qcom_icc_node * const msm8939_bimc_nodes[] = { 1313 [BIMC_SNOC_MAS] = &bimc_snoc_mas, 1314 [MASTER_AMPSS_M0] = &mas_apss, 1315 [MASTER_GRAPHICS_3D] = &mas_gfx, 1316 [MASTER_TCU0] = &mas_tcu0, 1317 [SLAVE_AMPSS_L2] = &slv_apps_l2, 1318 [SLAVE_EBI_CH0] = &slv_ebi_ch0, 1319 [SNOC_BIMC_0_SLV] = &snoc_bimc_0_slv, 1320 [SNOC_BIMC_1_SLV] = &snoc_bimc_1_slv, 1321 [SNOC_BIMC_2_SLV] = &snoc_bimc_2_slv, 1322}; 1323 1324static const struct regmap_config msm8939_bimc_regmap_config = { 1325 .reg_bits = 32, 1326 .reg_stride = 4, 1327 .val_bits = 32, 1328 .max_register = 0x62000, 1329 .fast_io = true, 1330}; 1331 1332static const struct qcom_icc_desc msm8939_bimc = { 1333 .type = QCOM_ICC_BIMC, 1334 .nodes = msm8939_bimc_nodes, 1335 .num_nodes = ARRAY_SIZE(msm8939_bimc_nodes), 1336 .regmap_cfg = &msm8939_bimc_regmap_config, 1337 .qos_offset = 0x8000, 1338}; 1339 1340static struct qcom_icc_node * const msm8939_pcnoc_nodes[] = { 1341 [MASTER_BLSP_1] = &mas_blsp_1, 1342 [MASTER_DEHR] = &mas_dehr, 1343 [MASTER_LPASS] = &mas_audio, 1344 [MASTER_CRYPTO_CORE0] = &mas_pcnoc_crypto_0, 1345 [MASTER_SDCC_1] = &mas_pcnoc_sdcc_1, 1346 [MASTER_SDCC_2] = &mas_pcnoc_sdcc_2, 1347 [MASTER_SPDM] = &mas_spdm, 1348 [MASTER_USB_HS1] = &mas_usb_hs1, 1349 [MASTER_USB_HS2] = &mas_usb_hs2, 1350 [PCNOC_INT_0] = &pcnoc_int_0, 1351 [PCNOC_INT_1] = &pcnoc_int_1, 1352 [PCNOC_MAS_0] = &pcnoc_m_0, 1353 [PCNOC_MAS_1] = &pcnoc_m_1, 1354 [PCNOC_SLV_0] = &pcnoc_s_0, 1355 [PCNOC_SLV_1] = &pcnoc_s_1, 1356 [PCNOC_SLV_2] = &pcnoc_s_2, 1357 [PCNOC_SLV_3] = &pcnoc_s_3, 1358 [PCNOC_SLV_4] = &pcnoc_s_4, 1359 [PCNOC_SLV_8] = &pcnoc_s_8, 1360 [PCNOC_SLV_9] = &pcnoc_s_9, 1361 [PCNOC_SNOC_MAS] = &pcnoc_snoc_mas, 1362 [SLAVE_BIMC_CFG] = &slv_bimc_cfg, 1363 [SLAVE_BLSP_1] = &slv_blsp_1, 1364 [SLAVE_BOOT_ROM] = &slv_boot_rom, 1365 [SLAVE_CAMERA_CFG] = &slv_camera_cfg, 1366 [SLAVE_CLK_CTL] = &slv_clk_ctl, 1367 [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg, 1368 [SLAVE_DEHR_CFG] = &slv_dehr_cfg, 1369 [SLAVE_DISPLAY_CFG] = &slv_display_cfg, 1370 [SLAVE_GRAPHICS_3D_CFG] = &slv_gfx_cfg, 1371 [SLAVE_IMEM_CFG] = &slv_imem_cfg, 1372 [SLAVE_LPASS] = &slv_audio, 1373 [SLAVE_MPM] = &slv_mpm, 1374 [SLAVE_MSG_RAM] = &slv_msg_ram, 1375 [SLAVE_MSS] = &slv_mss, 1376 [SLAVE_PDM] = &slv_pdm, 1377 [SLAVE_PMIC_ARB] = &slv_pmic_arb, 1378 [SLAVE_PCNOC_CFG] = &slv_pcnoc_cfg, 1379 [SLAVE_PRNG] = &slv_prng, 1380 [SLAVE_QDSS_CFG] = &slv_qdss_cfg, 1381 [SLAVE_RBCPR_CFG] = &slv_rbcpr_cfg, 1382 [SLAVE_SDCC_1] = &slv_sdcc_1, 1383 [SLAVE_SDCC_2] = &slv_sdcc_2, 1384 [SLAVE_SECURITY] = &slv_security, 1385 [SLAVE_SNOC_CFG] = &slv_snoc_cfg, 1386 [SLAVE_SPDM] = &slv_spdm, 1387 [SLAVE_TCSR] = &slv_tcsr, 1388 [SLAVE_TLMM] = &slv_tlmm, 1389 [SLAVE_USB_HS1] = &slv_usb_hs1, 1390 [SLAVE_USB_HS2] = &slv_usb_hs2, 1391 [SLAVE_VENUS_CFG] = &slv_venus_cfg, 1392 [SNOC_PCNOC_SLV] = &snoc_pcnoc_slv, 1393}; 1394 1395static const struct regmap_config msm8939_pcnoc_regmap_config = { 1396 .reg_bits = 32, 1397 .reg_stride = 4, 1398 .val_bits = 32, 1399 .max_register = 0x11000, 1400 .fast_io = true, 1401}; 1402 1403static const struct qcom_icc_desc msm8939_pcnoc = { 1404 .type = QCOM_ICC_NOC, 1405 .nodes = msm8939_pcnoc_nodes, 1406 .num_nodes = ARRAY_SIZE(msm8939_pcnoc_nodes), 1407 .regmap_cfg = &msm8939_pcnoc_regmap_config, 1408 .qos_offset = 0x7000, 1409}; 1410 1411static const struct of_device_id msm8939_noc_of_match[] = { 1412 { .compatible = "qcom,msm8939-bimc", .data = &msm8939_bimc }, 1413 { .compatible = "qcom,msm8939-pcnoc", .data = &msm8939_pcnoc }, 1414 { .compatible = "qcom,msm8939-snoc", .data = &msm8939_snoc }, 1415 { .compatible = "qcom,msm8939-snoc-mm", .data = &msm8939_snoc_mm }, 1416 { } 1417}; 1418MODULE_DEVICE_TABLE(of, msm8939_noc_of_match); 1419 1420static struct platform_driver msm8939_noc_driver = { 1421 .probe = qnoc_probe, 1422 .remove = qnoc_remove, 1423 .driver = { 1424 .name = "qnoc-msm8939", 1425 .of_match_table = msm8939_noc_of_match, 1426 }, 1427}; 1428module_platform_driver(msm8939_noc_driver); 1429MODULE_AUTHOR("Jun Nie <jun.nie@linaro.org>"); 1430MODULE_DESCRIPTION("Qualcomm MSM8939 NoC driver"); 1431MODULE_LICENSE("GPL v2");