sdx55.c (12361B)
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Qualcomm SDX55 interconnect driver 4 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 5 * 6 * Copyright (c) 2021, Linaro Ltd. 7 * 8 */ 9 10#include <linux/device.h> 11#include <linux/interconnect.h> 12#include <linux/interconnect-provider.h> 13#include <linux/module.h> 14#include <linux/of_platform.h> 15#include <dt-bindings/interconnect/qcom,sdx55.h> 16 17#include "bcm-voter.h" 18#include "icc-rpmh.h" 19#include "sdx55.h" 20 21DEFINE_QNODE(llcc_mc, SDX55_MASTER_LLCC, 4, 4, SDX55_SLAVE_EBI_CH0); 22DEFINE_QNODE(acm_tcu, SDX55_MASTER_TCU_0, 1, 8, SDX55_SLAVE_LLCC, SDX55_SLAVE_MEM_NOC_SNOC, SDX55_SLAVE_MEM_NOC_PCIE_SNOC); 23DEFINE_QNODE(qnm_snoc_gc, SDX55_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDX55_SLAVE_LLCC); 24DEFINE_QNODE(xm_apps_rdwr, SDX55_MASTER_AMPSS_M0, 1, 16, SDX55_SLAVE_LLCC, SDX55_SLAVE_MEM_NOC_SNOC, SDX55_SLAVE_MEM_NOC_PCIE_SNOC); 25DEFINE_QNODE(qhm_audio, SDX55_MASTER_AUDIO, 1, 4, SDX55_SLAVE_ANOC_SNOC); 26DEFINE_QNODE(qhm_blsp1, SDX55_MASTER_BLSP_1, 1, 4, SDX55_SLAVE_ANOC_SNOC); 27DEFINE_QNODE(qhm_qdss_bam, SDX55_MASTER_QDSS_BAM, 1, 4, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_TLMM, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); 28DEFINE_QNODE(qhm_qpic, SDX55_MASTER_QPIC, 1, 4, SDX55_SLAVE_AOSS, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP, SDX55_SLAVE_AUDIO); 29DEFINE_QNODE(qhm_snoc_cfg, SDX55_MASTER_SNOC_CFG, 1, 4, SDX55_SLAVE_SERVICE_SNOC); 30DEFINE_QNODE(qhm_spmi_fetcher1, SDX55_MASTER_SPMI_FETCHER, 1, 4, SDX55_SLAVE_AOSS, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP); 31DEFINE_QNODE(qnm_aggre_noc, SDX55_MASTER_ANOC_SNOC, 1, 8, SDX55_SLAVE_PCIE_0, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_TLMM, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_USB3, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_APPSS, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); 32DEFINE_QNODE(qnm_ipa, SDX55_MASTER_IPA, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_AOSS, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_TLMM, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); 33DEFINE_QNODE(qnm_memnoc, SDX55_MASTER_MEM_NOC_SNOC, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_TLMM, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_APPSS, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); 34DEFINE_QNODE(qnm_memnoc_pcie, SDX55_MASTER_MEM_NOC_PCIE_SNOC, 1, 8, SDX55_SLAVE_PCIE_0); 35DEFINE_QNODE(qxm_crypto, SDX55_MASTER_CRYPTO_CORE_0, 1, 8, SDX55_SLAVE_AOSS, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP); 36DEFINE_QNODE(xm_emac, SDX55_MASTER_EMAC, 1, 8, SDX55_SLAVE_ANOC_SNOC); 37DEFINE_QNODE(xm_ipa2pcie_slv, SDX55_MASTER_IPA_PCIE, 1, 8, SDX55_SLAVE_PCIE_0); 38DEFINE_QNODE(xm_pcie, SDX55_MASTER_PCIE, 1, 8, SDX55_SLAVE_ANOC_SNOC); 39DEFINE_QNODE(xm_qdss_etr, SDX55_MASTER_QDSS_ETR, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_AOSS, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); 40DEFINE_QNODE(xm_sdc1, SDX55_MASTER_SDCC_1, 1, 8, SDX55_SLAVE_AOSS, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP, SDX55_SLAVE_AUDIO); 41DEFINE_QNODE(xm_usb3, SDX55_MASTER_USB3, 1, 8, SDX55_SLAVE_ANOC_SNOC); 42DEFINE_QNODE(ebi, SDX55_SLAVE_EBI_CH0, 1, 4); 43DEFINE_QNODE(qns_llcc, SDX55_SLAVE_LLCC, 1, 16, SDX55_SLAVE_EBI_CH0); 44DEFINE_QNODE(qns_memnoc_snoc, SDX55_SLAVE_MEM_NOC_SNOC, 1, 8, SDX55_MASTER_MEM_NOC_SNOC); 45DEFINE_QNODE(qns_sys_pcie, SDX55_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SDX55_MASTER_MEM_NOC_PCIE_SNOC); 46DEFINE_QNODE(qhs_aop, SDX55_SLAVE_AOP, 1, 4); 47DEFINE_QNODE(qhs_aoss, SDX55_SLAVE_AOSS, 1, 4); 48DEFINE_QNODE(qhs_apss, SDX55_SLAVE_APPSS, 1, 4); 49DEFINE_QNODE(qhs_audio, SDX55_SLAVE_AUDIO, 1, 4); 50DEFINE_QNODE(qhs_blsp1, SDX55_SLAVE_BLSP_1, 1, 4); 51DEFINE_QNODE(qhs_clk_ctl, SDX55_SLAVE_CLK_CTL, 1, 4); 52DEFINE_QNODE(qhs_crypto0_cfg, SDX55_SLAVE_CRYPTO_0_CFG, 1, 4); 53DEFINE_QNODE(qhs_ddrss_cfg, SDX55_SLAVE_CNOC_DDRSS, 1, 4); 54DEFINE_QNODE(qhs_ecc_cfg, SDX55_SLAVE_ECC_CFG, 1, 4); 55DEFINE_QNODE(qhs_emac_cfg, SDX55_SLAVE_EMAC_CFG, 1, 4); 56DEFINE_QNODE(qhs_imem_cfg, SDX55_SLAVE_IMEM_CFG, 1, 4); 57DEFINE_QNODE(qhs_ipa, SDX55_SLAVE_IPA_CFG, 1, 4); 58DEFINE_QNODE(qhs_mss_cfg, SDX55_SLAVE_CNOC_MSS, 1, 4); 59DEFINE_QNODE(qhs_pcie_parf, SDX55_SLAVE_PCIE_PARF, 1, 4); 60DEFINE_QNODE(qhs_pdm, SDX55_SLAVE_PDM, 1, 4); 61DEFINE_QNODE(qhs_prng, SDX55_SLAVE_PRNG, 1, 4); 62DEFINE_QNODE(qhs_qdss_cfg, SDX55_SLAVE_QDSS_CFG, 1, 4); 63DEFINE_QNODE(qhs_qpic, SDX55_SLAVE_QPIC, 1, 4); 64DEFINE_QNODE(qhs_sdc1, SDX55_SLAVE_SDCC_1, 1, 4); 65DEFINE_QNODE(qhs_snoc_cfg, SDX55_SLAVE_SNOC_CFG, 1, 4, SDX55_MASTER_SNOC_CFG); 66DEFINE_QNODE(qhs_spmi_fetcher, SDX55_SLAVE_SPMI_FETCHER, 1, 4); 67DEFINE_QNODE(qhs_spmi_vgi_coex, SDX55_SLAVE_SPMI_VGI_COEX, 1, 4); 68DEFINE_QNODE(qhs_tcsr, SDX55_SLAVE_TCSR, 1, 4); 69DEFINE_QNODE(qhs_tlmm, SDX55_SLAVE_TLMM, 1, 4); 70DEFINE_QNODE(qhs_usb3, SDX55_SLAVE_USB3, 1, 4); 71DEFINE_QNODE(qhs_usb3_phy, SDX55_SLAVE_USB3_PHY_CFG, 1, 4); 72DEFINE_QNODE(qns_aggre_noc, SDX55_SLAVE_ANOC_SNOC, 1, 8, SDX55_MASTER_ANOC_SNOC); 73DEFINE_QNODE(qns_snoc_memnoc, SDX55_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDX55_MASTER_SNOC_GC_MEM_NOC); 74DEFINE_QNODE(qxs_imem, SDX55_SLAVE_OCIMEM, 1, 8); 75DEFINE_QNODE(srvc_snoc, SDX55_SLAVE_SERVICE_SNOC, 1, 4); 76DEFINE_QNODE(xs_pcie, SDX55_SLAVE_PCIE_0, 1, 8); 77DEFINE_QNODE(xs_qdss_stm, SDX55_SLAVE_QDSS_STM, 1, 4); 78DEFINE_QNODE(xs_sys_tcu_cfg, SDX55_SLAVE_TCU, 1, 8); 79 80DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); 81DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); 82DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); 83DEFINE_QBCM(bcm_pn0, "PN0", false, &qhm_snoc_cfg); 84DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr); 85DEFINE_QBCM(bcm_sh4, "SH4", false, &qns_memnoc_snoc, &qns_sys_pcie); 86DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_snoc_memnoc); 87DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); 88DEFINE_QBCM(bcm_pn1, "PN1", false, &xm_sdc1); 89DEFINE_QBCM(bcm_pn2, "PN2", false, &qhm_audio, &qhm_spmi_fetcher1); 90DEFINE_QBCM(bcm_sn3, "SN3", false, &xs_qdss_stm); 91DEFINE_QBCM(bcm_pn3, "PN3", false, &qhm_blsp1, &qhm_qpic); 92DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_sys_tcu_cfg); 93DEFINE_QBCM(bcm_pn5, "PN5", false, &qxm_crypto); 94DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie); 95DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre_noc, &xm_emac, &xm_emac, &xm_usb3, 96 &qns_aggre_noc); 97DEFINE_QBCM(bcm_sn8, "SN8", false, &qhm_qdss_bam, &xm_qdss_etr); 98DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_memnoc); 99DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_memnoc_pcie); 100DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_ipa, &xm_ipa2pcie_slv); 101 102static struct qcom_icc_bcm * const mc_virt_bcms[] = { 103 &bcm_mc0, 104}; 105 106static struct qcom_icc_node * const mc_virt_nodes[] = { 107 [MASTER_LLCC] = &llcc_mc, 108 [SLAVE_EBI_CH0] = &ebi, 109}; 110 111static const struct qcom_icc_desc sdx55_mc_virt = { 112 .nodes = mc_virt_nodes, 113 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 114 .bcms = mc_virt_bcms, 115 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 116}; 117 118static struct qcom_icc_bcm * const mem_noc_bcms[] = { 119 &bcm_sh0, 120 &bcm_sh3, 121 &bcm_sh4, 122}; 123 124static struct qcom_icc_node * const mem_noc_nodes[] = { 125 [MASTER_TCU_0] = &acm_tcu, 126 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 127 [MASTER_AMPSS_M0] = &xm_apps_rdwr, 128 [SLAVE_LLCC] = &qns_llcc, 129 [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc, 130 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie, 131}; 132 133static const struct qcom_icc_desc sdx55_mem_noc = { 134 .nodes = mem_noc_nodes, 135 .num_nodes = ARRAY_SIZE(mem_noc_nodes), 136 .bcms = mem_noc_bcms, 137 .num_bcms = ARRAY_SIZE(mem_noc_bcms), 138}; 139 140static struct qcom_icc_bcm * const system_noc_bcms[] = { 141 &bcm_ce0, 142 &bcm_pn0, 143 &bcm_pn1, 144 &bcm_pn2, 145 &bcm_pn3, 146 &bcm_pn5, 147 &bcm_sn0, 148 &bcm_sn1, 149 &bcm_sn3, 150 &bcm_sn4, 151 &bcm_sn6, 152 &bcm_sn7, 153 &bcm_sn8, 154 &bcm_sn9, 155 &bcm_sn10, 156 &bcm_sn11, 157}; 158 159static struct qcom_icc_node * const system_noc_nodes[] = { 160 [MASTER_AUDIO] = &qhm_audio, 161 [MASTER_BLSP_1] = &qhm_blsp1, 162 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 163 [MASTER_QPIC] = &qhm_qpic, 164 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 165 [MASTER_SPMI_FETCHER] = &qhm_spmi_fetcher1, 166 [MASTER_ANOC_SNOC] = &qnm_aggre_noc, 167 [MASTER_IPA] = &qnm_ipa, 168 [MASTER_MEM_NOC_SNOC] = &qnm_memnoc, 169 [MASTER_MEM_NOC_PCIE_SNOC] = &qnm_memnoc_pcie, 170 [MASTER_CRYPTO_CORE_0] = &qxm_crypto, 171 [MASTER_EMAC] = &xm_emac, 172 [MASTER_IPA_PCIE] = &xm_ipa2pcie_slv, 173 [MASTER_PCIE] = &xm_pcie, 174 [MASTER_QDSS_ETR] = &xm_qdss_etr, 175 [MASTER_SDCC_1] = &xm_sdc1, 176 [MASTER_USB3] = &xm_usb3, 177 [SLAVE_AOP] = &qhs_aop, 178 [SLAVE_AOSS] = &qhs_aoss, 179 [SLAVE_APPSS] = &qhs_apss, 180 [SLAVE_AUDIO] = &qhs_audio, 181 [SLAVE_BLSP_1] = &qhs_blsp1, 182 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 183 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 184 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 185 [SLAVE_ECC_CFG] = &qhs_ecc_cfg, 186 [SLAVE_EMAC_CFG] = &qhs_emac_cfg, 187 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 188 [SLAVE_IPA_CFG] = &qhs_ipa, 189 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 190 [SLAVE_PCIE_PARF] = &qhs_pcie_parf, 191 [SLAVE_PDM] = &qhs_pdm, 192 [SLAVE_PRNG] = &qhs_prng, 193 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 194 [SLAVE_QPIC] = &qhs_qpic, 195 [SLAVE_SDCC_1] = &qhs_sdc1, 196 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 197 [SLAVE_SPMI_FETCHER] = &qhs_spmi_fetcher, 198 [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex, 199 [SLAVE_TCSR] = &qhs_tcsr, 200 [SLAVE_TLMM] = &qhs_tlmm, 201 [SLAVE_USB3] = &qhs_usb3, 202 [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy, 203 [SLAVE_ANOC_SNOC] = &qns_aggre_noc, 204 [SLAVE_SNOC_MEM_NOC_GC] = &qns_snoc_memnoc, 205 [SLAVE_OCIMEM] = &qxs_imem, 206 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 207 [SLAVE_PCIE_0] = &xs_pcie, 208 [SLAVE_QDSS_STM] = &xs_qdss_stm, 209 [SLAVE_TCU] = &xs_sys_tcu_cfg, 210}; 211 212static const struct qcom_icc_desc sdx55_system_noc = { 213 .nodes = system_noc_nodes, 214 .num_nodes = ARRAY_SIZE(system_noc_nodes), 215 .bcms = system_noc_bcms, 216 .num_bcms = ARRAY_SIZE(system_noc_bcms), 217}; 218 219static const struct of_device_id qnoc_of_match[] = { 220 { .compatible = "qcom,sdx55-mc-virt", 221 .data = &sdx55_mc_virt}, 222 { .compatible = "qcom,sdx55-mem-noc", 223 .data = &sdx55_mem_noc}, 224 { .compatible = "qcom,sdx55-system-noc", 225 .data = &sdx55_system_noc}, 226 { } 227}; 228MODULE_DEVICE_TABLE(of, qnoc_of_match); 229 230static struct platform_driver qnoc_driver = { 231 .probe = qcom_icc_rpmh_probe, 232 .remove = qcom_icc_rpmh_remove, 233 .driver = { 234 .name = "qnoc-sdx55", 235 .of_match_table = qnoc_of_match, 236 .sync_state = icc_sync_state, 237 }, 238}; 239module_platform_driver(qnoc_driver); 240 241MODULE_DESCRIPTION("Qualcomm SDX55 NoC driver"); 242MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 243MODULE_LICENSE("GPL v2");