amd_iommu.h (4697B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2009-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 */ 6 7#ifndef AMD_IOMMU_H 8#define AMD_IOMMU_H 9 10#include <linux/iommu.h> 11 12#include "amd_iommu_types.h" 13 14extern irqreturn_t amd_iommu_int_thread(int irq, void *data); 15extern irqreturn_t amd_iommu_int_handler(int irq, void *data); 16extern void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid); 17extern void amd_iommu_restart_event_logging(struct amd_iommu *iommu); 18extern int amd_iommu_init_devices(void); 19extern void amd_iommu_uninit_devices(void); 20extern void amd_iommu_init_notifier(void); 21extern int amd_iommu_init_api(void); 22extern void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid); 23 24#ifdef CONFIG_AMD_IOMMU_DEBUGFS 25void amd_iommu_debugfs_setup(struct amd_iommu *iommu); 26#else 27static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {} 28#endif 29 30/* Needed for interrupt remapping */ 31extern int amd_iommu_prepare(void); 32extern int amd_iommu_enable(void); 33extern void amd_iommu_disable(void); 34extern int amd_iommu_reenable(int); 35extern int amd_iommu_enable_faulting(void); 36extern int amd_iommu_guest_ir; 37extern enum io_pgtable_fmt amd_iommu_pgtable; 38 39/* IOMMUv2 specific functions */ 40struct iommu_domain; 41 42extern bool amd_iommu_v2_supported(void); 43extern struct amd_iommu *get_amd_iommu(unsigned int idx); 44extern u8 amd_iommu_pc_get_max_banks(unsigned int idx); 45extern bool amd_iommu_pc_supported(void); 46extern u8 amd_iommu_pc_get_max_counters(unsigned int idx); 47extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 48 u8 fxn, u64 *value); 49extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 50 u8 fxn, u64 *value); 51 52extern int amd_iommu_register_ppr_notifier(struct notifier_block *nb); 53extern int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb); 54extern void amd_iommu_domain_direct_map(struct iommu_domain *dom); 55extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids); 56extern int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid, 57 u64 address); 58extern void amd_iommu_update_and_flush_device_table(struct protection_domain *domain); 59extern void amd_iommu_domain_update(struct protection_domain *domain); 60extern void amd_iommu_domain_flush_complete(struct protection_domain *domain); 61extern void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain); 62extern int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid); 63extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid, 64 unsigned long cr3); 65extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid); 66 67#ifdef CONFIG_IRQ_REMAP 68extern int amd_iommu_create_irq_domain(struct amd_iommu *iommu); 69#else 70static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu) 71{ 72 return 0; 73} 74#endif 75 76#define PPR_SUCCESS 0x0 77#define PPR_INVALID 0x1 78#define PPR_FAILURE 0xf 79 80extern int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid, 81 int status, int tag); 82 83static inline bool is_rd890_iommu(struct pci_dev *pdev) 84{ 85 return (pdev->vendor == PCI_VENDOR_ID_ATI) && 86 (pdev->device == PCI_DEVICE_ID_RD890_IOMMU); 87} 88 89static inline bool iommu_feature(struct amd_iommu *iommu, u64 mask) 90{ 91 return !!(iommu->features & mask); 92} 93 94static inline u64 iommu_virt_to_phys(void *vaddr) 95{ 96 return (u64)__sme_set(virt_to_phys(vaddr)); 97} 98 99static inline void *iommu_phys_to_virt(unsigned long paddr) 100{ 101 return phys_to_virt(__sme_clr(paddr)); 102} 103 104static inline 105void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root) 106{ 107 atomic64_set(&domain->iop.pt_root, root); 108 domain->iop.root = (u64 *)(root & PAGE_MASK); 109 domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */ 110} 111 112static inline 113void amd_iommu_domain_clr_pt_root(struct protection_domain *domain) 114{ 115 amd_iommu_domain_set_pt_root(domain, 0); 116} 117 118static inline int get_pci_sbdf_id(struct pci_dev *pdev) 119{ 120 int seg = pci_domain_nr(pdev->bus); 121 u16 devid = pci_dev_id(pdev); 122 123 return PCI_SEG_DEVID_TO_SBDF(seg, devid); 124} 125 126extern bool translation_pre_enabled(struct amd_iommu *iommu); 127extern bool amd_iommu_is_attach_deferred(struct device *dev); 128extern int __init add_special_device(u8 type, u8 id, u32 *devid, 129 bool cmd_line); 130 131#ifdef CONFIG_DMI 132void amd_iommu_apply_ivrs_quirks(void); 133#else 134static inline void amd_iommu_apply_ivrs_quirks(void) { } 135#endif 136 137extern void amd_iommu_domain_set_pgtable(struct protection_domain *domain, 138 u64 *root, int mode); 139extern struct dev_table_entry *get_dev_table(struct amd_iommu *iommu); 140 141extern u64 amd_iommu_efr; 142extern u64 amd_iommu_efr2; 143 144extern bool amd_iommu_snp_en; 145#endif