cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
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rockchip-iommu.c (37865B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * IOMMU API for Rockchip
      4 *
      5 * Module Authors:	Simon Xue <xxm@rock-chips.com>
      6 *			Daniel Kurtz <djkurtz@chromium.org>
      7 */
      8
      9#include <linux/clk.h>
     10#include <linux/compiler.h>
     11#include <linux/delay.h>
     12#include <linux/device.h>
     13#include <linux/dma-mapping.h>
     14#include <linux/errno.h>
     15#include <linux/interrupt.h>
     16#include <linux/io.h>
     17#include <linux/iommu.h>
     18#include <linux/iopoll.h>
     19#include <linux/list.h>
     20#include <linux/mm.h>
     21#include <linux/init.h>
     22#include <linux/of.h>
     23#include <linux/of_platform.h>
     24#include <linux/platform_device.h>
     25#include <linux/pm_runtime.h>
     26#include <linux/slab.h>
     27#include <linux/spinlock.h>
     28
     29/** MMU register offsets */
     30#define RK_MMU_DTE_ADDR		0x00	/* Directory table address */
     31#define RK_MMU_STATUS		0x04
     32#define RK_MMU_COMMAND		0x08
     33#define RK_MMU_PAGE_FAULT_ADDR	0x0C	/* IOVA of last page fault */
     34#define RK_MMU_ZAP_ONE_LINE	0x10	/* Shootdown one IOTLB entry */
     35#define RK_MMU_INT_RAWSTAT	0x14	/* IRQ status ignoring mask */
     36#define RK_MMU_INT_CLEAR	0x18	/* Acknowledge and re-arm irq */
     37#define RK_MMU_INT_MASK		0x1C	/* IRQ enable */
     38#define RK_MMU_INT_STATUS	0x20	/* IRQ status after masking */
     39#define RK_MMU_AUTO_GATING	0x24
     40
     41#define DTE_ADDR_DUMMY		0xCAFEBABE
     42
     43#define RK_MMU_POLL_PERIOD_US		100
     44#define RK_MMU_FORCE_RESET_TIMEOUT_US	100000
     45#define RK_MMU_POLL_TIMEOUT_US		1000
     46
     47/* RK_MMU_STATUS fields */
     48#define RK_MMU_STATUS_PAGING_ENABLED       BIT(0)
     49#define RK_MMU_STATUS_PAGE_FAULT_ACTIVE    BIT(1)
     50#define RK_MMU_STATUS_STALL_ACTIVE         BIT(2)
     51#define RK_MMU_STATUS_IDLE                 BIT(3)
     52#define RK_MMU_STATUS_REPLAY_BUFFER_EMPTY  BIT(4)
     53#define RK_MMU_STATUS_PAGE_FAULT_IS_WRITE  BIT(5)
     54#define RK_MMU_STATUS_STALL_NOT_ACTIVE     BIT(31)
     55
     56/* RK_MMU_COMMAND command values */
     57#define RK_MMU_CMD_ENABLE_PAGING    0  /* Enable memory translation */
     58#define RK_MMU_CMD_DISABLE_PAGING   1  /* Disable memory translation */
     59#define RK_MMU_CMD_ENABLE_STALL     2  /* Stall paging to allow other cmds */
     60#define RK_MMU_CMD_DISABLE_STALL    3  /* Stop stall re-enables paging */
     61#define RK_MMU_CMD_ZAP_CACHE        4  /* Shoot down entire IOTLB */
     62#define RK_MMU_CMD_PAGE_FAULT_DONE  5  /* Clear page fault */
     63#define RK_MMU_CMD_FORCE_RESET      6  /* Reset all registers */
     64
     65/* RK_MMU_INT_* register fields */
     66#define RK_MMU_IRQ_PAGE_FAULT    0x01  /* page fault */
     67#define RK_MMU_IRQ_BUS_ERROR     0x02  /* bus read error */
     68#define RK_MMU_IRQ_MASK          (RK_MMU_IRQ_PAGE_FAULT | RK_MMU_IRQ_BUS_ERROR)
     69
     70#define NUM_DT_ENTRIES 1024
     71#define NUM_PT_ENTRIES 1024
     72
     73#define SPAGE_ORDER 12
     74#define SPAGE_SIZE (1 << SPAGE_ORDER)
     75
     76 /*
     77  * Support mapping any size that fits in one page table:
     78  *   4 KiB to 4 MiB
     79  */
     80#define RK_IOMMU_PGSIZE_BITMAP 0x007ff000
     81
     82struct rk_iommu_domain {
     83	struct list_head iommus;
     84	u32 *dt; /* page directory table */
     85	dma_addr_t dt_dma;
     86	spinlock_t iommus_lock; /* lock for iommus list */
     87	spinlock_t dt_lock; /* lock for modifying page directory table */
     88
     89	struct iommu_domain domain;
     90};
     91
     92/* list of clocks required by IOMMU */
     93static const char * const rk_iommu_clocks[] = {
     94	"aclk", "iface",
     95};
     96
     97struct rk_iommu_ops {
     98	phys_addr_t (*pt_address)(u32 dte);
     99	u32 (*mk_dtentries)(dma_addr_t pt_dma);
    100	u32 (*mk_ptentries)(phys_addr_t page, int prot);
    101	phys_addr_t (*dte_addr_phys)(u32 addr);
    102	u32 (*dma_addr_dte)(dma_addr_t dt_dma);
    103	u64 dma_bit_mask;
    104};
    105
    106struct rk_iommu {
    107	struct device *dev;
    108	void __iomem **bases;
    109	int num_mmu;
    110	int num_irq;
    111	struct clk_bulk_data *clocks;
    112	int num_clocks;
    113	bool reset_disabled;
    114	struct iommu_device iommu;
    115	struct list_head node; /* entry in rk_iommu_domain.iommus */
    116	struct iommu_domain *domain; /* domain to which iommu is attached */
    117	struct iommu_group *group;
    118};
    119
    120struct rk_iommudata {
    121	struct device_link *link; /* runtime PM link from IOMMU to master */
    122	struct rk_iommu *iommu;
    123};
    124
    125static struct device *dma_dev;
    126static const struct rk_iommu_ops *rk_ops;
    127
    128static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma,
    129				  unsigned int count)
    130{
    131	size_t size = count * sizeof(u32); /* count of u32 entry */
    132
    133	dma_sync_single_for_device(dma_dev, dma, size, DMA_TO_DEVICE);
    134}
    135
    136static struct rk_iommu_domain *to_rk_domain(struct iommu_domain *dom)
    137{
    138	return container_of(dom, struct rk_iommu_domain, domain);
    139}
    140
    141/*
    142 * The Rockchip rk3288 iommu uses a 2-level page table.
    143 * The first level is the "Directory Table" (DT).
    144 * The DT consists of 1024 4-byte Directory Table Entries (DTEs), each pointing
    145 * to a "Page Table".
    146 * The second level is the 1024 Page Tables (PT).
    147 * Each PT consists of 1024 4-byte Page Table Entries (PTEs), each pointing to
    148 * a 4 KB page of physical memory.
    149 *
    150 * The DT and each PT fits in a single 4 KB page (4-bytes * 1024 entries).
    151 * Each iommu device has a MMU_DTE_ADDR register that contains the physical
    152 * address of the start of the DT page.
    153 *
    154 * The structure of the page table is as follows:
    155 *
    156 *                   DT
    157 * MMU_DTE_ADDR -> +-----+
    158 *                 |     |
    159 *                 +-----+     PT
    160 *                 | DTE | -> +-----+
    161 *                 +-----+    |     |     Memory
    162 *                 |     |    +-----+     Page
    163 *                 |     |    | PTE | -> +-----+
    164 *                 +-----+    +-----+    |     |
    165 *                            |     |    |     |
    166 *                            |     |    |     |
    167 *                            +-----+    |     |
    168 *                                       |     |
    169 *                                       |     |
    170 *                                       +-----+
    171 */
    172
    173/*
    174 * Each DTE has a PT address and a valid bit:
    175 * +---------------------+-----------+-+
    176 * | PT address          | Reserved  |V|
    177 * +---------------------+-----------+-+
    178 *  31:12 - PT address (PTs always starts on a 4 KB boundary)
    179 *  11: 1 - Reserved
    180 *      0 - 1 if PT @ PT address is valid
    181 */
    182#define RK_DTE_PT_ADDRESS_MASK    0xfffff000
    183#define RK_DTE_PT_VALID           BIT(0)
    184
    185static inline phys_addr_t rk_dte_pt_address(u32 dte)
    186{
    187	return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK;
    188}
    189
    190/*
    191 * In v2:
    192 * 31:12 - PT address bit 31:0
    193 * 11: 8 - PT address bit 35:32
    194 *  7: 4 - PT address bit 39:36
    195 *  3: 1 - Reserved
    196 *     0 - 1 if PT @ PT address is valid
    197 */
    198#define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4)
    199#define DTE_HI_MASK1	GENMASK(11, 8)
    200#define DTE_HI_MASK2	GENMASK(7, 4)
    201#define DTE_HI_SHIFT1	24 /* shift bit 8 to bit 32 */
    202#define DTE_HI_SHIFT2	32 /* shift bit 4 to bit 36 */
    203#define PAGE_DESC_HI_MASK1	GENMASK_ULL(35, 32)
    204#define PAGE_DESC_HI_MASK2	GENMASK_ULL(39, 36)
    205
    206static inline phys_addr_t rk_dte_pt_address_v2(u32 dte)
    207{
    208	u64 dte_v2 = dte;
    209
    210	dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) |
    211		 ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) |
    212		 (dte_v2 & RK_DTE_PT_ADDRESS_MASK);
    213
    214	return (phys_addr_t)dte_v2;
    215}
    216
    217static inline bool rk_dte_is_pt_valid(u32 dte)
    218{
    219	return dte & RK_DTE_PT_VALID;
    220}
    221
    222static inline u32 rk_mk_dte(dma_addr_t pt_dma)
    223{
    224	return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID;
    225}
    226
    227static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma)
    228{
    229	pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) |
    230		 ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) |
    231		 (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2;
    232
    233	return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID;
    234}
    235
    236/*
    237 * Each PTE has a Page address, some flags and a valid bit:
    238 * +---------------------+---+-------+-+
    239 * | Page address        |Rsv| Flags |V|
    240 * +---------------------+---+-------+-+
    241 *  31:12 - Page address (Pages always start on a 4 KB boundary)
    242 *  11: 9 - Reserved
    243 *   8: 1 - Flags
    244 *      8 - Read allocate - allocate cache space on read misses
    245 *      7 - Read cache - enable cache & prefetch of data
    246 *      6 - Write buffer - enable delaying writes on their way to memory
    247 *      5 - Write allocate - allocate cache space on write misses
    248 *      4 - Write cache - different writes can be merged together
    249 *      3 - Override cache attributes
    250 *          if 1, bits 4-8 control cache attributes
    251 *          if 0, the system bus defaults are used
    252 *      2 - Writable
    253 *      1 - Readable
    254 *      0 - 1 if Page @ Page address is valid
    255 */
    256#define RK_PTE_PAGE_ADDRESS_MASK  0xfffff000
    257#define RK_PTE_PAGE_FLAGS_MASK    0x000001fe
    258#define RK_PTE_PAGE_WRITABLE      BIT(2)
    259#define RK_PTE_PAGE_READABLE      BIT(1)
    260#define RK_PTE_PAGE_VALID         BIT(0)
    261
    262static inline bool rk_pte_is_page_valid(u32 pte)
    263{
    264	return pte & RK_PTE_PAGE_VALID;
    265}
    266
    267/* TODO: set cache flags per prot IOMMU_CACHE */
    268static u32 rk_mk_pte(phys_addr_t page, int prot)
    269{
    270	u32 flags = 0;
    271	flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0;
    272	flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0;
    273	page &= RK_PTE_PAGE_ADDRESS_MASK;
    274	return page | flags | RK_PTE_PAGE_VALID;
    275}
    276
    277/*
    278 * In v2:
    279 * 31:12 - Page address bit 31:0
    280 *  11:9 - Page address bit 34:32
    281 *   8:4 - Page address bit 39:35
    282 *     3 - Security
    283 *     2 - Readable
    284 *     1 - Writable
    285 *     0 - 1 if Page @ Page address is valid
    286 */
    287#define RK_PTE_PAGE_READABLE_V2      BIT(2)
    288#define RK_PTE_PAGE_WRITABLE_V2      BIT(1)
    289
    290static u32 rk_mk_pte_v2(phys_addr_t page, int prot)
    291{
    292	u32 flags = 0;
    293
    294	flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE_V2 : 0;
    295	flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE_V2 : 0;
    296
    297	return rk_mk_dte_v2(page) | flags;
    298}
    299
    300static u32 rk_mk_pte_invalid(u32 pte)
    301{
    302	return pte & ~RK_PTE_PAGE_VALID;
    303}
    304
    305/*
    306 * rk3288 iova (IOMMU Virtual Address) format
    307 *  31       22.21       12.11          0
    308 * +-----------+-----------+-------------+
    309 * | DTE index | PTE index | Page offset |
    310 * +-----------+-----------+-------------+
    311 *  31:22 - DTE index   - index of DTE in DT
    312 *  21:12 - PTE index   - index of PTE in PT @ DTE.pt_address
    313 *  11: 0 - Page offset - offset into page @ PTE.page_address
    314 */
    315#define RK_IOVA_DTE_MASK    0xffc00000
    316#define RK_IOVA_DTE_SHIFT   22
    317#define RK_IOVA_PTE_MASK    0x003ff000
    318#define RK_IOVA_PTE_SHIFT   12
    319#define RK_IOVA_PAGE_MASK   0x00000fff
    320#define RK_IOVA_PAGE_SHIFT  0
    321
    322static u32 rk_iova_dte_index(dma_addr_t iova)
    323{
    324	return (u32)(iova & RK_IOVA_DTE_MASK) >> RK_IOVA_DTE_SHIFT;
    325}
    326
    327static u32 rk_iova_pte_index(dma_addr_t iova)
    328{
    329	return (u32)(iova & RK_IOVA_PTE_MASK) >> RK_IOVA_PTE_SHIFT;
    330}
    331
    332static u32 rk_iova_page_offset(dma_addr_t iova)
    333{
    334	return (u32)(iova & RK_IOVA_PAGE_MASK) >> RK_IOVA_PAGE_SHIFT;
    335}
    336
    337static u32 rk_iommu_read(void __iomem *base, u32 offset)
    338{
    339	return readl(base + offset);
    340}
    341
    342static void rk_iommu_write(void __iomem *base, u32 offset, u32 value)
    343{
    344	writel(value, base + offset);
    345}
    346
    347static void rk_iommu_command(struct rk_iommu *iommu, u32 command)
    348{
    349	int i;
    350
    351	for (i = 0; i < iommu->num_mmu; i++)
    352		writel(command, iommu->bases[i] + RK_MMU_COMMAND);
    353}
    354
    355static void rk_iommu_base_command(void __iomem *base, u32 command)
    356{
    357	writel(command, base + RK_MMU_COMMAND);
    358}
    359static void rk_iommu_zap_lines(struct rk_iommu *iommu, dma_addr_t iova_start,
    360			       size_t size)
    361{
    362	int i;
    363	dma_addr_t iova_end = iova_start + size;
    364	/*
    365	 * TODO(djkurtz): Figure out when it is more efficient to shootdown the
    366	 * entire iotlb rather than iterate over individual iovas.
    367	 */
    368	for (i = 0; i < iommu->num_mmu; i++) {
    369		dma_addr_t iova;
    370
    371		for (iova = iova_start; iova < iova_end; iova += SPAGE_SIZE)
    372			rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova);
    373	}
    374}
    375
    376static bool rk_iommu_is_stall_active(struct rk_iommu *iommu)
    377{
    378	bool active = true;
    379	int i;
    380
    381	for (i = 0; i < iommu->num_mmu; i++)
    382		active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
    383					   RK_MMU_STATUS_STALL_ACTIVE);
    384
    385	return active;
    386}
    387
    388static bool rk_iommu_is_paging_enabled(struct rk_iommu *iommu)
    389{
    390	bool enable = true;
    391	int i;
    392
    393	for (i = 0; i < iommu->num_mmu; i++)
    394		enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
    395					   RK_MMU_STATUS_PAGING_ENABLED);
    396
    397	return enable;
    398}
    399
    400static bool rk_iommu_is_reset_done(struct rk_iommu *iommu)
    401{
    402	bool done = true;
    403	int i;
    404
    405	for (i = 0; i < iommu->num_mmu; i++)
    406		done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0;
    407
    408	return done;
    409}
    410
    411static int rk_iommu_enable_stall(struct rk_iommu *iommu)
    412{
    413	int ret, i;
    414	bool val;
    415
    416	if (rk_iommu_is_stall_active(iommu))
    417		return 0;
    418
    419	/* Stall can only be enabled if paging is enabled */
    420	if (!rk_iommu_is_paging_enabled(iommu))
    421		return 0;
    422
    423	rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_STALL);
    424
    425	ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val,
    426				 val, RK_MMU_POLL_PERIOD_US,
    427				 RK_MMU_POLL_TIMEOUT_US);
    428	if (ret)
    429		for (i = 0; i < iommu->num_mmu; i++)
    430			dev_err(iommu->dev, "Enable stall request timed out, status: %#08x\n",
    431				rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
    432
    433	return ret;
    434}
    435
    436static int rk_iommu_disable_stall(struct rk_iommu *iommu)
    437{
    438	int ret, i;
    439	bool val;
    440
    441	if (!rk_iommu_is_stall_active(iommu))
    442		return 0;
    443
    444	rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_STALL);
    445
    446	ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val,
    447				 !val, RK_MMU_POLL_PERIOD_US,
    448				 RK_MMU_POLL_TIMEOUT_US);
    449	if (ret)
    450		for (i = 0; i < iommu->num_mmu; i++)
    451			dev_err(iommu->dev, "Disable stall request timed out, status: %#08x\n",
    452				rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
    453
    454	return ret;
    455}
    456
    457static int rk_iommu_enable_paging(struct rk_iommu *iommu)
    458{
    459	int ret, i;
    460	bool val;
    461
    462	if (rk_iommu_is_paging_enabled(iommu))
    463		return 0;
    464
    465	rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_PAGING);
    466
    467	ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val,
    468				 val, RK_MMU_POLL_PERIOD_US,
    469				 RK_MMU_POLL_TIMEOUT_US);
    470	if (ret)
    471		for (i = 0; i < iommu->num_mmu; i++)
    472			dev_err(iommu->dev, "Enable paging request timed out, status: %#08x\n",
    473				rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
    474
    475	return ret;
    476}
    477
    478static int rk_iommu_disable_paging(struct rk_iommu *iommu)
    479{
    480	int ret, i;
    481	bool val;
    482
    483	if (!rk_iommu_is_paging_enabled(iommu))
    484		return 0;
    485
    486	rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_PAGING);
    487
    488	ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val,
    489				 !val, RK_MMU_POLL_PERIOD_US,
    490				 RK_MMU_POLL_TIMEOUT_US);
    491	if (ret)
    492		for (i = 0; i < iommu->num_mmu; i++)
    493			dev_err(iommu->dev, "Disable paging request timed out, status: %#08x\n",
    494				rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
    495
    496	return ret;
    497}
    498
    499static int rk_iommu_force_reset(struct rk_iommu *iommu)
    500{
    501	int ret, i;
    502	u32 dte_addr;
    503	bool val;
    504
    505	if (iommu->reset_disabled)
    506		return 0;
    507
    508	/*
    509	 * Check if register DTE_ADDR is working by writing DTE_ADDR_DUMMY
    510	 * and verifying that upper 5 nybbles are read back.
    511	 */
    512	for (i = 0; i < iommu->num_mmu; i++) {
    513		dte_addr = rk_ops->pt_address(DTE_ADDR_DUMMY);
    514		rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, dte_addr);
    515
    516		if (dte_addr != rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR)) {
    517			dev_err(iommu->dev, "Error during raw reset. MMU_DTE_ADDR is not functioning\n");
    518			return -EFAULT;
    519		}
    520	}
    521
    522	rk_iommu_command(iommu, RK_MMU_CMD_FORCE_RESET);
    523
    524	ret = readx_poll_timeout(rk_iommu_is_reset_done, iommu, val,
    525				 val, RK_MMU_FORCE_RESET_TIMEOUT_US,
    526				 RK_MMU_POLL_TIMEOUT_US);
    527	if (ret) {
    528		dev_err(iommu->dev, "FORCE_RESET command timed out\n");
    529		return ret;
    530	}
    531
    532	return 0;
    533}
    534
    535static inline phys_addr_t rk_dte_addr_phys(u32 addr)
    536{
    537	return (phys_addr_t)addr;
    538}
    539
    540static inline u32 rk_dma_addr_dte(dma_addr_t dt_dma)
    541{
    542	return dt_dma;
    543}
    544
    545#define DT_HI_MASK GENMASK_ULL(39, 32)
    546#define DTE_BASE_HI_MASK GENMASK(11, 4)
    547#define DT_SHIFT   28
    548
    549static inline phys_addr_t rk_dte_addr_phys_v2(u32 addr)
    550{
    551	u64 addr64 = addr;
    552	return (phys_addr_t)(addr64 & RK_DTE_PT_ADDRESS_MASK) |
    553	       ((addr64 & DTE_BASE_HI_MASK) << DT_SHIFT);
    554}
    555
    556static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma)
    557{
    558	return (dt_dma & RK_DTE_PT_ADDRESS_MASK) |
    559	       ((dt_dma & DT_HI_MASK) >> DT_SHIFT);
    560}
    561
    562static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
    563{
    564	void __iomem *base = iommu->bases[index];
    565	u32 dte_index, pte_index, page_offset;
    566	u32 mmu_dte_addr;
    567	phys_addr_t mmu_dte_addr_phys, dte_addr_phys;
    568	u32 *dte_addr;
    569	u32 dte;
    570	phys_addr_t pte_addr_phys = 0;
    571	u32 *pte_addr = NULL;
    572	u32 pte = 0;
    573	phys_addr_t page_addr_phys = 0;
    574	u32 page_flags = 0;
    575
    576	dte_index = rk_iova_dte_index(iova);
    577	pte_index = rk_iova_pte_index(iova);
    578	page_offset = rk_iova_page_offset(iova);
    579
    580	mmu_dte_addr = rk_iommu_read(base, RK_MMU_DTE_ADDR);
    581	mmu_dte_addr_phys = rk_ops->dte_addr_phys(mmu_dte_addr);
    582
    583	dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index);
    584	dte_addr = phys_to_virt(dte_addr_phys);
    585	dte = *dte_addr;
    586
    587	if (!rk_dte_is_pt_valid(dte))
    588		goto print_it;
    589
    590	pte_addr_phys = rk_ops->pt_address(dte) + (pte_index * 4);
    591	pte_addr = phys_to_virt(pte_addr_phys);
    592	pte = *pte_addr;
    593
    594	if (!rk_pte_is_page_valid(pte))
    595		goto print_it;
    596
    597	page_addr_phys = rk_ops->pt_address(pte) + page_offset;
    598	page_flags = pte & RK_PTE_PAGE_FLAGS_MASK;
    599
    600print_it:
    601	dev_err(iommu->dev, "iova = %pad: dte_index: %#03x pte_index: %#03x page_offset: %#03x\n",
    602		&iova, dte_index, pte_index, page_offset);
    603	dev_err(iommu->dev, "mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n",
    604		&mmu_dte_addr_phys, &dte_addr_phys, dte,
    605		rk_dte_is_pt_valid(dte), &pte_addr_phys, pte,
    606		rk_pte_is_page_valid(pte), &page_addr_phys, page_flags);
    607}
    608
    609static irqreturn_t rk_iommu_irq(int irq, void *dev_id)
    610{
    611	struct rk_iommu *iommu = dev_id;
    612	u32 status;
    613	u32 int_status;
    614	dma_addr_t iova;
    615	irqreturn_t ret = IRQ_NONE;
    616	int i, err;
    617
    618	err = pm_runtime_get_if_in_use(iommu->dev);
    619	if (!err || WARN_ON_ONCE(err < 0))
    620		return ret;
    621
    622	if (WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks)))
    623		goto out;
    624
    625	for (i = 0; i < iommu->num_mmu; i++) {
    626		int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS);
    627		if (int_status == 0)
    628			continue;
    629
    630		ret = IRQ_HANDLED;
    631		iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR);
    632
    633		if (int_status & RK_MMU_IRQ_PAGE_FAULT) {
    634			int flags;
    635
    636			status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS);
    637			flags = (status & RK_MMU_STATUS_PAGE_FAULT_IS_WRITE) ?
    638					IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
    639
    640			dev_err(iommu->dev, "Page fault at %pad of type %s\n",
    641				&iova,
    642				(flags == IOMMU_FAULT_WRITE) ? "write" : "read");
    643
    644			log_iova(iommu, i, iova);
    645
    646			/*
    647			 * Report page fault to any installed handlers.
    648			 * Ignore the return code, though, since we always zap cache
    649			 * and clear the page fault anyway.
    650			 */
    651			if (iommu->domain)
    652				report_iommu_fault(iommu->domain, iommu->dev, iova,
    653						   flags);
    654			else
    655				dev_err(iommu->dev, "Page fault while iommu not attached to domain?\n");
    656
    657			rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
    658			rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE);
    659		}
    660
    661		if (int_status & RK_MMU_IRQ_BUS_ERROR)
    662			dev_err(iommu->dev, "BUS_ERROR occurred at %pad\n", &iova);
    663
    664		if (int_status & ~RK_MMU_IRQ_MASK)
    665			dev_err(iommu->dev, "unexpected int_status: %#08x\n",
    666				int_status);
    667
    668		rk_iommu_write(iommu->bases[i], RK_MMU_INT_CLEAR, int_status);
    669	}
    670
    671	clk_bulk_disable(iommu->num_clocks, iommu->clocks);
    672
    673out:
    674	pm_runtime_put(iommu->dev);
    675	return ret;
    676}
    677
    678static phys_addr_t rk_iommu_iova_to_phys(struct iommu_domain *domain,
    679					 dma_addr_t iova)
    680{
    681	struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
    682	unsigned long flags;
    683	phys_addr_t pt_phys, phys = 0;
    684	u32 dte, pte;
    685	u32 *page_table;
    686
    687	spin_lock_irqsave(&rk_domain->dt_lock, flags);
    688
    689	dte = rk_domain->dt[rk_iova_dte_index(iova)];
    690	if (!rk_dte_is_pt_valid(dte))
    691		goto out;
    692
    693	pt_phys = rk_ops->pt_address(dte);
    694	page_table = (u32 *)phys_to_virt(pt_phys);
    695	pte = page_table[rk_iova_pte_index(iova)];
    696	if (!rk_pte_is_page_valid(pte))
    697		goto out;
    698
    699	phys = rk_ops->pt_address(pte) + rk_iova_page_offset(iova);
    700out:
    701	spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
    702
    703	return phys;
    704}
    705
    706static void rk_iommu_zap_iova(struct rk_iommu_domain *rk_domain,
    707			      dma_addr_t iova, size_t size)
    708{
    709	struct list_head *pos;
    710	unsigned long flags;
    711
    712	/* shootdown these iova from all iommus using this domain */
    713	spin_lock_irqsave(&rk_domain->iommus_lock, flags);
    714	list_for_each(pos, &rk_domain->iommus) {
    715		struct rk_iommu *iommu;
    716		int ret;
    717
    718		iommu = list_entry(pos, struct rk_iommu, node);
    719
    720		/* Only zap TLBs of IOMMUs that are powered on. */
    721		ret = pm_runtime_get_if_in_use(iommu->dev);
    722		if (WARN_ON_ONCE(ret < 0))
    723			continue;
    724		if (ret) {
    725			WARN_ON(clk_bulk_enable(iommu->num_clocks,
    726						iommu->clocks));
    727			rk_iommu_zap_lines(iommu, iova, size);
    728			clk_bulk_disable(iommu->num_clocks, iommu->clocks);
    729			pm_runtime_put(iommu->dev);
    730		}
    731	}
    732	spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
    733}
    734
    735static void rk_iommu_zap_iova_first_last(struct rk_iommu_domain *rk_domain,
    736					 dma_addr_t iova, size_t size)
    737{
    738	rk_iommu_zap_iova(rk_domain, iova, SPAGE_SIZE);
    739	if (size > SPAGE_SIZE)
    740		rk_iommu_zap_iova(rk_domain, iova + size - SPAGE_SIZE,
    741					SPAGE_SIZE);
    742}
    743
    744static u32 *rk_dte_get_page_table(struct rk_iommu_domain *rk_domain,
    745				  dma_addr_t iova)
    746{
    747	u32 *page_table, *dte_addr;
    748	u32 dte_index, dte;
    749	phys_addr_t pt_phys;
    750	dma_addr_t pt_dma;
    751
    752	assert_spin_locked(&rk_domain->dt_lock);
    753
    754	dte_index = rk_iova_dte_index(iova);
    755	dte_addr = &rk_domain->dt[dte_index];
    756	dte = *dte_addr;
    757	if (rk_dte_is_pt_valid(dte))
    758		goto done;
    759
    760	page_table = (u32 *)get_zeroed_page(GFP_ATOMIC | GFP_DMA32);
    761	if (!page_table)
    762		return ERR_PTR(-ENOMEM);
    763
    764	pt_dma = dma_map_single(dma_dev, page_table, SPAGE_SIZE, DMA_TO_DEVICE);
    765	if (dma_mapping_error(dma_dev, pt_dma)) {
    766		dev_err(dma_dev, "DMA mapping error while allocating page table\n");
    767		free_page((unsigned long)page_table);
    768		return ERR_PTR(-ENOMEM);
    769	}
    770
    771	dte = rk_ops->mk_dtentries(pt_dma);
    772	*dte_addr = dte;
    773
    774	rk_table_flush(rk_domain,
    775		       rk_domain->dt_dma + dte_index * sizeof(u32), 1);
    776done:
    777	pt_phys = rk_ops->pt_address(dte);
    778	return (u32 *)phys_to_virt(pt_phys);
    779}
    780
    781static size_t rk_iommu_unmap_iova(struct rk_iommu_domain *rk_domain,
    782				  u32 *pte_addr, dma_addr_t pte_dma,
    783				  size_t size)
    784{
    785	unsigned int pte_count;
    786	unsigned int pte_total = size / SPAGE_SIZE;
    787
    788	assert_spin_locked(&rk_domain->dt_lock);
    789
    790	for (pte_count = 0; pte_count < pte_total; pte_count++) {
    791		u32 pte = pte_addr[pte_count];
    792		if (!rk_pte_is_page_valid(pte))
    793			break;
    794
    795		pte_addr[pte_count] = rk_mk_pte_invalid(pte);
    796	}
    797
    798	rk_table_flush(rk_domain, pte_dma, pte_count);
    799
    800	return pte_count * SPAGE_SIZE;
    801}
    802
    803static int rk_iommu_map_iova(struct rk_iommu_domain *rk_domain, u32 *pte_addr,
    804			     dma_addr_t pte_dma, dma_addr_t iova,
    805			     phys_addr_t paddr, size_t size, int prot)
    806{
    807	unsigned int pte_count;
    808	unsigned int pte_total = size / SPAGE_SIZE;
    809	phys_addr_t page_phys;
    810
    811	assert_spin_locked(&rk_domain->dt_lock);
    812
    813	for (pte_count = 0; pte_count < pte_total; pte_count++) {
    814		u32 pte = pte_addr[pte_count];
    815
    816		if (rk_pte_is_page_valid(pte))
    817			goto unwind;
    818
    819		pte_addr[pte_count] = rk_ops->mk_ptentries(paddr, prot);
    820
    821		paddr += SPAGE_SIZE;
    822	}
    823
    824	rk_table_flush(rk_domain, pte_dma, pte_total);
    825
    826	/*
    827	 * Zap the first and last iova to evict from iotlb any previously
    828	 * mapped cachelines holding stale values for its dte and pte.
    829	 * We only zap the first and last iova, since only they could have
    830	 * dte or pte shared with an existing mapping.
    831	 */
    832	rk_iommu_zap_iova_first_last(rk_domain, iova, size);
    833
    834	return 0;
    835unwind:
    836	/* Unmap the range of iovas that we just mapped */
    837	rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma,
    838			    pte_count * SPAGE_SIZE);
    839
    840	iova += pte_count * SPAGE_SIZE;
    841	page_phys = rk_ops->pt_address(pte_addr[pte_count]);
    842	pr_err("iova: %pad already mapped to %pa cannot remap to phys: %pa prot: %#x\n",
    843	       &iova, &page_phys, &paddr, prot);
    844
    845	return -EADDRINUSE;
    846}
    847
    848static int rk_iommu_map(struct iommu_domain *domain, unsigned long _iova,
    849			phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
    850{
    851	struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
    852	unsigned long flags;
    853	dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
    854	u32 *page_table, *pte_addr;
    855	u32 dte_index, pte_index;
    856	int ret;
    857
    858	spin_lock_irqsave(&rk_domain->dt_lock, flags);
    859
    860	/*
    861	 * pgsize_bitmap specifies iova sizes that fit in one page table
    862	 * (1024 4-KiB pages = 4 MiB).
    863	 * So, size will always be 4096 <= size <= 4194304.
    864	 * Since iommu_map() guarantees that both iova and size will be
    865	 * aligned, we will always only be mapping from a single dte here.
    866	 */
    867	page_table = rk_dte_get_page_table(rk_domain, iova);
    868	if (IS_ERR(page_table)) {
    869		spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
    870		return PTR_ERR(page_table);
    871	}
    872
    873	dte_index = rk_domain->dt[rk_iova_dte_index(iova)];
    874	pte_index = rk_iova_pte_index(iova);
    875	pte_addr = &page_table[pte_index];
    876
    877	pte_dma = rk_ops->pt_address(dte_index) + pte_index * sizeof(u32);
    878	ret = rk_iommu_map_iova(rk_domain, pte_addr, pte_dma, iova,
    879				paddr, size, prot);
    880
    881	spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
    882
    883	return ret;
    884}
    885
    886static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova,
    887			     size_t size, struct iommu_iotlb_gather *gather)
    888{
    889	struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
    890	unsigned long flags;
    891	dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
    892	phys_addr_t pt_phys;
    893	u32 dte;
    894	u32 *pte_addr;
    895	size_t unmap_size;
    896
    897	spin_lock_irqsave(&rk_domain->dt_lock, flags);
    898
    899	/*
    900	 * pgsize_bitmap specifies iova sizes that fit in one page table
    901	 * (1024 4-KiB pages = 4 MiB).
    902	 * So, size will always be 4096 <= size <= 4194304.
    903	 * Since iommu_unmap() guarantees that both iova and size will be
    904	 * aligned, we will always only be unmapping from a single dte here.
    905	 */
    906	dte = rk_domain->dt[rk_iova_dte_index(iova)];
    907	/* Just return 0 if iova is unmapped */
    908	if (!rk_dte_is_pt_valid(dte)) {
    909		spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
    910		return 0;
    911	}
    912
    913	pt_phys = rk_ops->pt_address(dte);
    914	pte_addr = (u32 *)phys_to_virt(pt_phys) + rk_iova_pte_index(iova);
    915	pte_dma = pt_phys + rk_iova_pte_index(iova) * sizeof(u32);
    916	unmap_size = rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, size);
    917
    918	spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
    919
    920	/* Shootdown iotlb entries for iova range that was just unmapped */
    921	rk_iommu_zap_iova(rk_domain, iova, unmap_size);
    922
    923	return unmap_size;
    924}
    925
    926static struct rk_iommu *rk_iommu_from_dev(struct device *dev)
    927{
    928	struct rk_iommudata *data = dev_iommu_priv_get(dev);
    929
    930	return data ? data->iommu : NULL;
    931}
    932
    933/* Must be called with iommu powered on and attached */
    934static void rk_iommu_disable(struct rk_iommu *iommu)
    935{
    936	int i;
    937
    938	/* Ignore error while disabling, just keep going */
    939	WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks));
    940	rk_iommu_enable_stall(iommu);
    941	rk_iommu_disable_paging(iommu);
    942	for (i = 0; i < iommu->num_mmu; i++) {
    943		rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0);
    944		rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 0);
    945	}
    946	rk_iommu_disable_stall(iommu);
    947	clk_bulk_disable(iommu->num_clocks, iommu->clocks);
    948}
    949
    950/* Must be called with iommu powered on and attached */
    951static int rk_iommu_enable(struct rk_iommu *iommu)
    952{
    953	struct iommu_domain *domain = iommu->domain;
    954	struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
    955	int ret, i;
    956
    957	ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks);
    958	if (ret)
    959		return ret;
    960
    961	ret = rk_iommu_enable_stall(iommu);
    962	if (ret)
    963		goto out_disable_clocks;
    964
    965	ret = rk_iommu_force_reset(iommu);
    966	if (ret)
    967		goto out_disable_stall;
    968
    969	for (i = 0; i < iommu->num_mmu; i++) {
    970		rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR,
    971			       rk_ops->dma_addr_dte(rk_domain->dt_dma));
    972		rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
    973		rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK);
    974	}
    975
    976	ret = rk_iommu_enable_paging(iommu);
    977
    978out_disable_stall:
    979	rk_iommu_disable_stall(iommu);
    980out_disable_clocks:
    981	clk_bulk_disable(iommu->num_clocks, iommu->clocks);
    982	return ret;
    983}
    984
    985static void rk_iommu_detach_device(struct iommu_domain *domain,
    986				   struct device *dev)
    987{
    988	struct rk_iommu *iommu;
    989	struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
    990	unsigned long flags;
    991	int ret;
    992
    993	/* Allow 'virtual devices' (eg drm) to detach from domain */
    994	iommu = rk_iommu_from_dev(dev);
    995	if (!iommu)
    996		return;
    997
    998	dev_dbg(dev, "Detaching from iommu domain\n");
    999
   1000	/* iommu already detached */
   1001	if (iommu->domain != domain)
   1002		return;
   1003
   1004	iommu->domain = NULL;
   1005
   1006	spin_lock_irqsave(&rk_domain->iommus_lock, flags);
   1007	list_del_init(&iommu->node);
   1008	spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
   1009
   1010	ret = pm_runtime_get_if_in_use(iommu->dev);
   1011	WARN_ON_ONCE(ret < 0);
   1012	if (ret > 0) {
   1013		rk_iommu_disable(iommu);
   1014		pm_runtime_put(iommu->dev);
   1015	}
   1016}
   1017
   1018static int rk_iommu_attach_device(struct iommu_domain *domain,
   1019		struct device *dev)
   1020{
   1021	struct rk_iommu *iommu;
   1022	struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
   1023	unsigned long flags;
   1024	int ret;
   1025
   1026	/*
   1027	 * Allow 'virtual devices' (e.g., drm) to attach to domain.
   1028	 * Such a device does not belong to an iommu group.
   1029	 */
   1030	iommu = rk_iommu_from_dev(dev);
   1031	if (!iommu)
   1032		return 0;
   1033
   1034	dev_dbg(dev, "Attaching to iommu domain\n");
   1035
   1036	/* iommu already attached */
   1037	if (iommu->domain == domain)
   1038		return 0;
   1039
   1040	if (iommu->domain)
   1041		rk_iommu_detach_device(iommu->domain, dev);
   1042
   1043	iommu->domain = domain;
   1044
   1045	spin_lock_irqsave(&rk_domain->iommus_lock, flags);
   1046	list_add_tail(&iommu->node, &rk_domain->iommus);
   1047	spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
   1048
   1049	ret = pm_runtime_get_if_in_use(iommu->dev);
   1050	if (!ret || WARN_ON_ONCE(ret < 0))
   1051		return 0;
   1052
   1053	ret = rk_iommu_enable(iommu);
   1054	if (ret)
   1055		rk_iommu_detach_device(iommu->domain, dev);
   1056
   1057	pm_runtime_put(iommu->dev);
   1058
   1059	return ret;
   1060}
   1061
   1062static struct iommu_domain *rk_iommu_domain_alloc(unsigned type)
   1063{
   1064	struct rk_iommu_domain *rk_domain;
   1065
   1066	if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
   1067		return NULL;
   1068
   1069	if (!dma_dev)
   1070		return NULL;
   1071
   1072	rk_domain = kzalloc(sizeof(*rk_domain), GFP_KERNEL);
   1073	if (!rk_domain)
   1074		return NULL;
   1075
   1076	/*
   1077	 * rk32xx iommus use a 2 level pagetable.
   1078	 * Each level1 (dt) and level2 (pt) table has 1024 4-byte entries.
   1079	 * Allocate one 4 KiB page for each table.
   1080	 */
   1081	rk_domain->dt = (u32 *)get_zeroed_page(GFP_KERNEL | GFP_DMA32);
   1082	if (!rk_domain->dt)
   1083		goto err_free_domain;
   1084
   1085	rk_domain->dt_dma = dma_map_single(dma_dev, rk_domain->dt,
   1086					   SPAGE_SIZE, DMA_TO_DEVICE);
   1087	if (dma_mapping_error(dma_dev, rk_domain->dt_dma)) {
   1088		dev_err(dma_dev, "DMA map error for DT\n");
   1089		goto err_free_dt;
   1090	}
   1091
   1092	spin_lock_init(&rk_domain->iommus_lock);
   1093	spin_lock_init(&rk_domain->dt_lock);
   1094	INIT_LIST_HEAD(&rk_domain->iommus);
   1095
   1096	rk_domain->domain.geometry.aperture_start = 0;
   1097	rk_domain->domain.geometry.aperture_end   = DMA_BIT_MASK(32);
   1098	rk_domain->domain.geometry.force_aperture = true;
   1099
   1100	return &rk_domain->domain;
   1101
   1102err_free_dt:
   1103	free_page((unsigned long)rk_domain->dt);
   1104err_free_domain:
   1105	kfree(rk_domain);
   1106
   1107	return NULL;
   1108}
   1109
   1110static void rk_iommu_domain_free(struct iommu_domain *domain)
   1111{
   1112	struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
   1113	int i;
   1114
   1115	WARN_ON(!list_empty(&rk_domain->iommus));
   1116
   1117	for (i = 0; i < NUM_DT_ENTRIES; i++) {
   1118		u32 dte = rk_domain->dt[i];
   1119		if (rk_dte_is_pt_valid(dte)) {
   1120			phys_addr_t pt_phys = rk_ops->pt_address(dte);
   1121			u32 *page_table = phys_to_virt(pt_phys);
   1122			dma_unmap_single(dma_dev, pt_phys,
   1123					 SPAGE_SIZE, DMA_TO_DEVICE);
   1124			free_page((unsigned long)page_table);
   1125		}
   1126	}
   1127
   1128	dma_unmap_single(dma_dev, rk_domain->dt_dma,
   1129			 SPAGE_SIZE, DMA_TO_DEVICE);
   1130	free_page((unsigned long)rk_domain->dt);
   1131
   1132	kfree(rk_domain);
   1133}
   1134
   1135static struct iommu_device *rk_iommu_probe_device(struct device *dev)
   1136{
   1137	struct rk_iommudata *data;
   1138	struct rk_iommu *iommu;
   1139
   1140	data = dev_iommu_priv_get(dev);
   1141	if (!data)
   1142		return ERR_PTR(-ENODEV);
   1143
   1144	iommu = rk_iommu_from_dev(dev);
   1145
   1146	data->link = device_link_add(dev, iommu->dev,
   1147				     DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
   1148
   1149	return &iommu->iommu;
   1150}
   1151
   1152static void rk_iommu_release_device(struct device *dev)
   1153{
   1154	struct rk_iommudata *data = dev_iommu_priv_get(dev);
   1155
   1156	device_link_del(data->link);
   1157}
   1158
   1159static struct iommu_group *rk_iommu_device_group(struct device *dev)
   1160{
   1161	struct rk_iommu *iommu;
   1162
   1163	iommu = rk_iommu_from_dev(dev);
   1164
   1165	return iommu_group_ref_get(iommu->group);
   1166}
   1167
   1168static int rk_iommu_of_xlate(struct device *dev,
   1169			     struct of_phandle_args *args)
   1170{
   1171	struct platform_device *iommu_dev;
   1172	struct rk_iommudata *data;
   1173
   1174	data = devm_kzalloc(dma_dev, sizeof(*data), GFP_KERNEL);
   1175	if (!data)
   1176		return -ENOMEM;
   1177
   1178	iommu_dev = of_find_device_by_node(args->np);
   1179
   1180	data->iommu = platform_get_drvdata(iommu_dev);
   1181	dev_iommu_priv_set(dev, data);
   1182
   1183	platform_device_put(iommu_dev);
   1184
   1185	return 0;
   1186}
   1187
   1188static const struct iommu_ops rk_iommu_ops = {
   1189	.domain_alloc = rk_iommu_domain_alloc,
   1190	.probe_device = rk_iommu_probe_device,
   1191	.release_device = rk_iommu_release_device,
   1192	.device_group = rk_iommu_device_group,
   1193	.pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP,
   1194	.of_xlate = rk_iommu_of_xlate,
   1195	.default_domain_ops = &(const struct iommu_domain_ops) {
   1196		.attach_dev	= rk_iommu_attach_device,
   1197		.detach_dev	= rk_iommu_detach_device,
   1198		.map		= rk_iommu_map,
   1199		.unmap		= rk_iommu_unmap,
   1200		.iova_to_phys	= rk_iommu_iova_to_phys,
   1201		.free		= rk_iommu_domain_free,
   1202	}
   1203};
   1204
   1205static int rk_iommu_probe(struct platform_device *pdev)
   1206{
   1207	struct device *dev = &pdev->dev;
   1208	struct rk_iommu *iommu;
   1209	struct resource *res;
   1210	const struct rk_iommu_ops *ops;
   1211	int num_res = pdev->num_resources;
   1212	int err, i;
   1213
   1214	iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL);
   1215	if (!iommu)
   1216		return -ENOMEM;
   1217
   1218	platform_set_drvdata(pdev, iommu);
   1219	iommu->dev = dev;
   1220	iommu->num_mmu = 0;
   1221
   1222	ops = of_device_get_match_data(dev);
   1223	if (!rk_ops)
   1224		rk_ops = ops;
   1225
   1226	/*
   1227	 * That should not happen unless different versions of the
   1228	 * hardware block are embedded the same SoC
   1229	 */
   1230	if (WARN_ON(rk_ops != ops))
   1231		return -EINVAL;
   1232
   1233	iommu->bases = devm_kcalloc(dev, num_res, sizeof(*iommu->bases),
   1234				    GFP_KERNEL);
   1235	if (!iommu->bases)
   1236		return -ENOMEM;
   1237
   1238	for (i = 0; i < num_res; i++) {
   1239		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
   1240		if (!res)
   1241			continue;
   1242		iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res);
   1243		if (IS_ERR(iommu->bases[i]))
   1244			continue;
   1245		iommu->num_mmu++;
   1246	}
   1247	if (iommu->num_mmu == 0)
   1248		return PTR_ERR(iommu->bases[0]);
   1249
   1250	iommu->num_irq = platform_irq_count(pdev);
   1251	if (iommu->num_irq < 0)
   1252		return iommu->num_irq;
   1253
   1254	iommu->reset_disabled = device_property_read_bool(dev,
   1255					"rockchip,disable-mmu-reset");
   1256
   1257	iommu->num_clocks = ARRAY_SIZE(rk_iommu_clocks);
   1258	iommu->clocks = devm_kcalloc(iommu->dev, iommu->num_clocks,
   1259				     sizeof(*iommu->clocks), GFP_KERNEL);
   1260	if (!iommu->clocks)
   1261		return -ENOMEM;
   1262
   1263	for (i = 0; i < iommu->num_clocks; ++i)
   1264		iommu->clocks[i].id = rk_iommu_clocks[i];
   1265
   1266	/*
   1267	 * iommu clocks should be present for all new devices and devicetrees
   1268	 * but there are older devicetrees without clocks out in the wild.
   1269	 * So clocks as optional for the time being.
   1270	 */
   1271	err = devm_clk_bulk_get(iommu->dev, iommu->num_clocks, iommu->clocks);
   1272	if (err == -ENOENT)
   1273		iommu->num_clocks = 0;
   1274	else if (err)
   1275		return err;
   1276
   1277	err = clk_bulk_prepare(iommu->num_clocks, iommu->clocks);
   1278	if (err)
   1279		return err;
   1280
   1281	iommu->group = iommu_group_alloc();
   1282	if (IS_ERR(iommu->group)) {
   1283		err = PTR_ERR(iommu->group);
   1284		goto err_unprepare_clocks;
   1285	}
   1286
   1287	err = iommu_device_sysfs_add(&iommu->iommu, dev, NULL, dev_name(dev));
   1288	if (err)
   1289		goto err_put_group;
   1290
   1291	err = iommu_device_register(&iommu->iommu, &rk_iommu_ops, dev);
   1292	if (err)
   1293		goto err_remove_sysfs;
   1294
   1295	/*
   1296	 * Use the first registered IOMMU device for domain to use with DMA
   1297	 * API, since a domain might not physically correspond to a single
   1298	 * IOMMU device..
   1299	 */
   1300	if (!dma_dev)
   1301		dma_dev = &pdev->dev;
   1302
   1303	bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
   1304
   1305	pm_runtime_enable(dev);
   1306
   1307	for (i = 0; i < iommu->num_irq; i++) {
   1308		int irq = platform_get_irq(pdev, i);
   1309
   1310		if (irq < 0)
   1311			return irq;
   1312
   1313		err = devm_request_irq(iommu->dev, irq, rk_iommu_irq,
   1314				       IRQF_SHARED, dev_name(dev), iommu);
   1315		if (err) {
   1316			pm_runtime_disable(dev);
   1317			goto err_remove_sysfs;
   1318		}
   1319	}
   1320
   1321	dma_set_mask_and_coherent(dev, rk_ops->dma_bit_mask);
   1322
   1323	return 0;
   1324err_remove_sysfs:
   1325	iommu_device_sysfs_remove(&iommu->iommu);
   1326err_put_group:
   1327	iommu_group_put(iommu->group);
   1328err_unprepare_clocks:
   1329	clk_bulk_unprepare(iommu->num_clocks, iommu->clocks);
   1330	return err;
   1331}
   1332
   1333static void rk_iommu_shutdown(struct platform_device *pdev)
   1334{
   1335	struct rk_iommu *iommu = platform_get_drvdata(pdev);
   1336	int i;
   1337
   1338	for (i = 0; i < iommu->num_irq; i++) {
   1339		int irq = platform_get_irq(pdev, i);
   1340
   1341		devm_free_irq(iommu->dev, irq, iommu);
   1342	}
   1343
   1344	pm_runtime_force_suspend(&pdev->dev);
   1345}
   1346
   1347static int __maybe_unused rk_iommu_suspend(struct device *dev)
   1348{
   1349	struct rk_iommu *iommu = dev_get_drvdata(dev);
   1350
   1351	if (!iommu->domain)
   1352		return 0;
   1353
   1354	rk_iommu_disable(iommu);
   1355	return 0;
   1356}
   1357
   1358static int __maybe_unused rk_iommu_resume(struct device *dev)
   1359{
   1360	struct rk_iommu *iommu = dev_get_drvdata(dev);
   1361
   1362	if (!iommu->domain)
   1363		return 0;
   1364
   1365	return rk_iommu_enable(iommu);
   1366}
   1367
   1368static const struct dev_pm_ops rk_iommu_pm_ops = {
   1369	SET_RUNTIME_PM_OPS(rk_iommu_suspend, rk_iommu_resume, NULL)
   1370	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
   1371				pm_runtime_force_resume)
   1372};
   1373
   1374static struct rk_iommu_ops iommu_data_ops_v1 = {
   1375	.pt_address = &rk_dte_pt_address,
   1376	.mk_dtentries = &rk_mk_dte,
   1377	.mk_ptentries = &rk_mk_pte,
   1378	.dte_addr_phys = &rk_dte_addr_phys,
   1379	.dma_addr_dte = &rk_dma_addr_dte,
   1380	.dma_bit_mask = DMA_BIT_MASK(32),
   1381};
   1382
   1383static struct rk_iommu_ops iommu_data_ops_v2 = {
   1384	.pt_address = &rk_dte_pt_address_v2,
   1385	.mk_dtentries = &rk_mk_dte_v2,
   1386	.mk_ptentries = &rk_mk_pte_v2,
   1387	.dte_addr_phys = &rk_dte_addr_phys_v2,
   1388	.dma_addr_dte = &rk_dma_addr_dte_v2,
   1389	.dma_bit_mask = DMA_BIT_MASK(40),
   1390};
   1391
   1392static const struct of_device_id rk_iommu_dt_ids[] = {
   1393	{	.compatible = "rockchip,iommu",
   1394		.data = &iommu_data_ops_v1,
   1395	},
   1396	{	.compatible = "rockchip,rk3568-iommu",
   1397		.data = &iommu_data_ops_v2,
   1398	},
   1399	{ /* sentinel */ }
   1400};
   1401
   1402static struct platform_driver rk_iommu_driver = {
   1403	.probe = rk_iommu_probe,
   1404	.shutdown = rk_iommu_shutdown,
   1405	.driver = {
   1406		   .name = "rk_iommu",
   1407		   .of_match_table = rk_iommu_dt_ids,
   1408		   .pm = &rk_iommu_pm_ops,
   1409		   .suppress_bind_attrs = true,
   1410	},
   1411};
   1412builtin_platform_driver(rk_iommu_driver);