irq-realtek-rtl.c (4610B)
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2020 Birger Koblitz <mail@birger-koblitz.de> 4 * Copyright (C) 2020 Bert Vermeulen <bert@biot.com> 5 * Copyright (C) 2020 John Crispin <john@phrozen.org> 6 */ 7 8#include <linux/of_irq.h> 9#include <linux/irqchip.h> 10#include <linux/spinlock.h> 11#include <linux/of_address.h> 12#include <linux/irqchip/chained_irq.h> 13 14/* Global Interrupt Mask Register */ 15#define RTL_ICTL_GIMR 0x00 16/* Global Interrupt Status Register */ 17#define RTL_ICTL_GISR 0x04 18/* Interrupt Routing Registers */ 19#define RTL_ICTL_IRR0 0x08 20#define RTL_ICTL_IRR1 0x0c 21#define RTL_ICTL_IRR2 0x10 22#define RTL_ICTL_IRR3 0x14 23 24#define REG(x) (realtek_ictl_base + x) 25 26static DEFINE_RAW_SPINLOCK(irq_lock); 27static void __iomem *realtek_ictl_base; 28 29static void realtek_ictl_unmask_irq(struct irq_data *i) 30{ 31 unsigned long flags; 32 u32 value; 33 34 raw_spin_lock_irqsave(&irq_lock, flags); 35 36 value = readl(REG(RTL_ICTL_GIMR)); 37 value |= BIT(i->hwirq); 38 writel(value, REG(RTL_ICTL_GIMR)); 39 40 raw_spin_unlock_irqrestore(&irq_lock, flags); 41} 42 43static void realtek_ictl_mask_irq(struct irq_data *i) 44{ 45 unsigned long flags; 46 u32 value; 47 48 raw_spin_lock_irqsave(&irq_lock, flags); 49 50 value = readl(REG(RTL_ICTL_GIMR)); 51 value &= ~BIT(i->hwirq); 52 writel(value, REG(RTL_ICTL_GIMR)); 53 54 raw_spin_unlock_irqrestore(&irq_lock, flags); 55} 56 57static struct irq_chip realtek_ictl_irq = { 58 .name = "realtek-rtl-intc", 59 .irq_mask = realtek_ictl_mask_irq, 60 .irq_unmask = realtek_ictl_unmask_irq, 61}; 62 63static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) 64{ 65 irq_set_chip_and_handler(irq, &realtek_ictl_irq, handle_level_irq); 66 67 return 0; 68} 69 70static const struct irq_domain_ops irq_domain_ops = { 71 .map = intc_map, 72 .xlate = irq_domain_xlate_onecell, 73}; 74 75static void realtek_irq_dispatch(struct irq_desc *desc) 76{ 77 struct irq_chip *chip = irq_desc_get_chip(desc); 78 struct irq_domain *domain; 79 unsigned long pending; 80 unsigned int soc_int; 81 82 chained_irq_enter(chip, desc); 83 pending = readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR)); 84 85 if (unlikely(!pending)) { 86 spurious_interrupt(); 87 goto out; 88 } 89 90 domain = irq_desc_get_handler_data(desc); 91 for_each_set_bit(soc_int, &pending, 32) 92 generic_handle_domain_irq(domain, soc_int); 93 94out: 95 chained_irq_exit(chip, desc); 96} 97 98/* 99 * SoC interrupts are cascaded to MIPS CPU interrupts according to the 100 * interrupt-map in the device tree. Each SoC interrupt gets 4 bits for 101 * the CPU interrupt in an Interrupt Routing Register. Max 32 SoC interrupts 102 * thus go into 4 IRRs. A routing value of '0' means the interrupt is left 103 * disconnected. Routing values {1..15} connect to output lines {0..14}. 104 */ 105static int __init map_interrupts(struct device_node *node, struct irq_domain *domain) 106{ 107 struct device_node *cpu_ictl; 108 const __be32 *imap; 109 u32 imaplen, soc_int, cpu_int, tmp, regs[4]; 110 int ret, i, irr_regs[] = { 111 RTL_ICTL_IRR3, 112 RTL_ICTL_IRR2, 113 RTL_ICTL_IRR1, 114 RTL_ICTL_IRR0, 115 }; 116 u8 mips_irqs_set; 117 118 ret = of_property_read_u32(node, "#address-cells", &tmp); 119 if (ret || tmp) 120 return -EINVAL; 121 122 imap = of_get_property(node, "interrupt-map", &imaplen); 123 if (!imap || imaplen % 3) 124 return -EINVAL; 125 126 mips_irqs_set = 0; 127 memset(regs, 0, sizeof(regs)); 128 for (i = 0; i < imaplen; i += 3 * sizeof(u32)) { 129 soc_int = be32_to_cpup(imap); 130 if (soc_int > 31) 131 return -EINVAL; 132 133 cpu_ictl = of_find_node_by_phandle(be32_to_cpup(imap + 1)); 134 if (!cpu_ictl) 135 return -EINVAL; 136 ret = of_property_read_u32(cpu_ictl, "#interrupt-cells", &tmp); 137 of_node_put(cpu_ictl); 138 if (ret || tmp != 1) 139 return -EINVAL; 140 141 cpu_int = be32_to_cpup(imap + 2); 142 if (cpu_int > 7 || cpu_int < 2) 143 return -EINVAL; 144 145 if (!(mips_irqs_set & BIT(cpu_int))) { 146 irq_set_chained_handler_and_data(cpu_int, realtek_irq_dispatch, 147 domain); 148 mips_irqs_set |= BIT(cpu_int); 149 } 150 151 /* Use routing values (1..6) for CPU interrupts (2..7) */ 152 regs[(soc_int * 4) / 32] |= (cpu_int - 1) << (soc_int * 4) % 32; 153 imap += 3; 154 } 155 156 for (i = 0; i < 4; i++) 157 writel(regs[i], REG(irr_regs[i])); 158 159 return 0; 160} 161 162static int __init realtek_rtl_of_init(struct device_node *node, struct device_node *parent) 163{ 164 struct irq_domain *domain; 165 int ret; 166 167 realtek_ictl_base = of_iomap(node, 0); 168 if (!realtek_ictl_base) 169 return -ENXIO; 170 171 /* Disable all cascaded interrupts */ 172 writel(0, REG(RTL_ICTL_GIMR)); 173 174 domain = irq_domain_add_simple(node, 32, 0, 175 &irq_domain_ops, NULL); 176 177 ret = map_interrupts(node, domain); 178 if (ret) { 179 pr_err("invalid interrupt map\n"); 180 return ret; 181 } 182 183 return 0; 184} 185 186IRQCHIP_DECLARE(realtek_rtl_intc, "realtek,rtl-intc", realtek_rtl_of_init);