cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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platform_mhu.c (4496B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (C) 2016 BayLibre SAS.
      4 * Author: Neil Armstrong <narmstrong@baylibre.com>
      5 * Synchronised with arm_mhu.c from :
      6 * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
      7 * Copyright (C) 2015 Linaro Ltd.
      8 * Author: Jassi Brar <jaswinder.singh@linaro.org>
      9 */
     10
     11#include <linux/interrupt.h>
     12#include <linux/spinlock.h>
     13#include <linux/mutex.h>
     14#include <linux/delay.h>
     15#include <linux/slab.h>
     16#include <linux/err.h>
     17#include <linux/io.h>
     18#include <linux/module.h>
     19#include <linux/platform_device.h>
     20#include <linux/mailbox_controller.h>
     21
     22#define INTR_SET_OFS	0x0
     23#define INTR_STAT_OFS	0x4
     24#define INTR_CLR_OFS	0x8
     25
     26#define MHU_SEC_OFFSET	0x0
     27#define MHU_LP_OFFSET	0xc
     28#define MHU_HP_OFFSET	0x18
     29#define TX_REG_OFFSET	0x24
     30
     31#define MHU_CHANS	3
     32
     33struct platform_mhu_link {
     34	int irq;
     35	void __iomem *tx_reg;
     36	void __iomem *rx_reg;
     37};
     38
     39struct platform_mhu {
     40	void __iomem *base;
     41	struct platform_mhu_link mlink[MHU_CHANS];
     42	struct mbox_chan chan[MHU_CHANS];
     43	struct mbox_controller mbox;
     44};
     45
     46static irqreturn_t platform_mhu_rx_interrupt(int irq, void *p)
     47{
     48	struct mbox_chan *chan = p;
     49	struct platform_mhu_link *mlink = chan->con_priv;
     50	u32 val;
     51
     52	val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS);
     53	if (!val)
     54		return IRQ_NONE;
     55
     56	mbox_chan_received_data(chan, (void *)&val);
     57
     58	writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
     59
     60	return IRQ_HANDLED;
     61}
     62
     63static bool platform_mhu_last_tx_done(struct mbox_chan *chan)
     64{
     65	struct platform_mhu_link *mlink = chan->con_priv;
     66	u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
     67
     68	return (val == 0);
     69}
     70
     71static int platform_mhu_send_data(struct mbox_chan *chan, void *data)
     72{
     73	struct platform_mhu_link *mlink = chan->con_priv;
     74	u32 *arg = data;
     75
     76	writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
     77
     78	return 0;
     79}
     80
     81static int platform_mhu_startup(struct mbox_chan *chan)
     82{
     83	struct platform_mhu_link *mlink = chan->con_priv;
     84	u32 val;
     85	int ret;
     86
     87	val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
     88	writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
     89
     90	ret = request_irq(mlink->irq, platform_mhu_rx_interrupt,
     91			  IRQF_SHARED, "platform_mhu_link", chan);
     92	if (ret) {
     93		dev_err(chan->mbox->dev,
     94			"Unable to acquire IRQ %d\n", mlink->irq);
     95		return ret;
     96	}
     97
     98	return 0;
     99}
    100
    101static void platform_mhu_shutdown(struct mbox_chan *chan)
    102{
    103	struct platform_mhu_link *mlink = chan->con_priv;
    104
    105	free_irq(mlink->irq, chan);
    106}
    107
    108static const struct mbox_chan_ops platform_mhu_ops = {
    109	.send_data = platform_mhu_send_data,
    110	.startup = platform_mhu_startup,
    111	.shutdown = platform_mhu_shutdown,
    112	.last_tx_done = platform_mhu_last_tx_done,
    113};
    114
    115static int platform_mhu_probe(struct platform_device *pdev)
    116{
    117	int i, err;
    118	struct platform_mhu *mhu;
    119	struct device *dev = &pdev->dev;
    120	int platform_mhu_reg[MHU_CHANS] = {
    121		MHU_SEC_OFFSET, MHU_LP_OFFSET, MHU_HP_OFFSET
    122	};
    123
    124	/* Allocate memory for device */
    125	mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
    126	if (!mhu)
    127		return -ENOMEM;
    128
    129	mhu->base = devm_platform_ioremap_resource(pdev, 0);
    130	if (IS_ERR(mhu->base)) {
    131		dev_err(dev, "ioremap failed\n");
    132		return PTR_ERR(mhu->base);
    133	}
    134
    135	for (i = 0; i < MHU_CHANS; i++) {
    136		mhu->chan[i].con_priv = &mhu->mlink[i];
    137		mhu->mlink[i].irq = platform_get_irq(pdev, i);
    138		if (mhu->mlink[i].irq < 0) {
    139			dev_err(dev, "failed to get irq%d\n", i);
    140			return mhu->mlink[i].irq;
    141		}
    142		mhu->mlink[i].rx_reg = mhu->base + platform_mhu_reg[i];
    143		mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET;
    144	}
    145
    146	mhu->mbox.dev = dev;
    147	mhu->mbox.chans = &mhu->chan[0];
    148	mhu->mbox.num_chans = MHU_CHANS;
    149	mhu->mbox.ops = &platform_mhu_ops;
    150	mhu->mbox.txdone_irq = false;
    151	mhu->mbox.txdone_poll = true;
    152	mhu->mbox.txpoll_period = 1;
    153
    154	platform_set_drvdata(pdev, mhu);
    155
    156	err = devm_mbox_controller_register(dev, &mhu->mbox);
    157	if (err) {
    158		dev_err(dev, "Failed to register mailboxes %d\n", err);
    159		return err;
    160	}
    161
    162	dev_info(dev, "Platform MHU Mailbox registered\n");
    163	return 0;
    164}
    165
    166static const struct of_device_id platform_mhu_dt_ids[] = {
    167	{ .compatible = "amlogic,meson-gxbb-mhu", },
    168	{ /* sentinel */ },
    169};
    170MODULE_DEVICE_TABLE(of, platform_mhu_dt_ids);
    171
    172static struct platform_driver platform_mhu_driver = {
    173	.probe	= platform_mhu_probe,
    174	.driver = {
    175		.name = "platform-mhu",
    176		.of_match_table	= platform_mhu_dt_ids,
    177	},
    178};
    179
    180module_platform_driver(platform_mhu_driver);
    181
    182MODULE_LICENSE("GPL v2");
    183MODULE_ALIAS("platform:platform-mhu");
    184MODULE_DESCRIPTION("Platform MHU Driver");
    185MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");