cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

mxl5xx_regs.h (15864B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved
      4 *
      5 * This program may alternatively be licensed under a proprietary license from
      6 * MaxLinear, Inc.
      7 *
      8 */
      9
     10#ifndef __MXL58X_REGISTERS_H__
     11#define __MXL58X_REGISTERS_H__
     12
     13#define HYDRA_INTR_STATUS_REG               0x80030008
     14#define HYDRA_INTR_MASK_REG                 0x8003000C
     15
     16#define HYDRA_CRYSTAL_SETTING               0x3FFFC5F0 /* 0 - 24 MHz & 1 - 27 MHz */
     17#define HYDRA_CRYSTAL_CAP                   0x3FFFEDA4 /* 0 - 24 MHz & 1 - 27 MHz */
     18
     19#define HYDRA_CPU_RESET_REG                 0x8003003C
     20#define HYDRA_CPU_RESET_DATA                0x00000400
     21
     22#define HYDRA_RESET_TRANSPORT_FIFO_REG      0x80030028
     23#define HYDRA_RESET_TRANSPORT_FIFO_DATA     0x00000000
     24
     25#define HYDRA_RESET_BBAND_REG               0x80030024
     26#define HYDRA_RESET_BBAND_DATA              0x00000000
     27
     28#define HYDRA_RESET_XBAR_REG                0x80030020
     29#define HYDRA_RESET_XBAR_DATA               0x00000000
     30
     31#define HYDRA_MODULES_CLK_1_REG             0x80030014
     32#define HYDRA_DISABLE_CLK_1                 0x00000000
     33
     34#define HYDRA_MODULES_CLK_2_REG             0x8003001C
     35#define HYDRA_DISABLE_CLK_2                 0x0000000B
     36
     37#define HYDRA_PRCM_ROOT_CLK_REG             0x80030018
     38#define HYDRA_PRCM_ROOT_CLK_DISABLE         0x00000000
     39
     40#define HYDRA_CPU_RESET_CHECK_REG           0x80030008
     41#define HYDRA_CPU_RESET_CHECK_OFFSET        0x40000000  /* <bit 30> */
     42
     43#define HYDRA_SKU_ID_REG                    0x90000190
     44
     45#define FW_DL_SIGN_ADDR                     0x3FFFEAE0
     46
     47/* Register to check if FW is running or not */
     48#define HYDRA_HEAR_BEAT                     0x3FFFEDDC
     49
     50/* Firmware version */
     51#define HYDRA_FIRMWARE_VERSION              0x3FFFEDB8
     52#define HYDRA_FW_RC_VERSION                 0x3FFFCFAC
     53
     54/* Firmware patch version */
     55#define HYDRA_FIRMWARE_PATCH_VERSION        0x3FFFEDC2
     56
     57/* SOC operating temperature in C */
     58#define HYDRA_TEMPARATURE                   0x3FFFEDB4
     59
     60/* Demod & Tuner status registers */
     61/* Demod 0 status base address */
     62#define HYDRA_DEMOD_0_BASE_ADDR             0x3FFFC64C
     63
     64/* Tuner 0 status base address */
     65#define HYDRA_TUNER_0_BASE_ADDR             0x3FFFCE4C
     66
     67#define POWER_FROM_ADCRSSI_READBACK         0x3FFFEB6C
     68
     69/* Macros to determine base address of respective demod or tuner */
     70#define HYDRA_DMD_STATUS_OFFSET(demodID)        ((demodID) * 0x100)
     71#define HYDRA_TUNER_STATUS_OFFSET(tunerID)      ((tunerID) * 0x40)
     72
     73/* Demod status address offset from respective demod's base address */
     74#define HYDRA_DMD_AGC_DIG_LEVEL_ADDR_OFFSET               0x3FFFC64C
     75#define HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET                 0x3FFFC650
     76#define HYDRA_DMD_ACQ_STATUS_ADDR_OFFSET                  0x3FFFC654
     77
     78#define HYDRA_DMD_STANDARD_ADDR_OFFSET                    0x3FFFC658
     79#define HYDRA_DMD_SPECTRUM_INVERSION_ADDR_OFFSET          0x3FFFC65C
     80#define HYDRA_DMD_SPECTRUM_ROLL_OFF_ADDR_OFFSET           0x3FFFC660
     81#define HYDRA_DMD_SYMBOL_RATE_ADDR_OFFSET                 0x3FFFC664
     82#define HYDRA_DMD_MODULATION_SCHEME_ADDR_OFFSET           0x3FFFC668
     83#define HYDRA_DMD_FEC_CODE_RATE_ADDR_OFFSET               0x3FFFC66C
     84
     85#define HYDRA_DMD_SNR_ADDR_OFFSET                         0x3FFFC670
     86#define HYDRA_DMD_FREQ_OFFSET_ADDR_OFFSET                 0x3FFFC674
     87#define HYDRA_DMD_CTL_FREQ_OFFSET_ADDR_OFFSET             0x3FFFC678
     88#define HYDRA_DMD_STR_FREQ_OFFSET_ADDR_OFFSET             0x3FFFC67C
     89#define HYDRA_DMD_FTL_FREQ_OFFSET_ADDR_OFFSET             0x3FFFC680
     90#define HYDRA_DMD_STR_NBC_SYNC_LOCK_ADDR_OFFSET           0x3FFFC684
     91#define HYDRA_DMD_CYCLE_SLIP_COUNT_ADDR_OFFSET            0x3FFFC688
     92
     93#define HYDRA_DMD_DISPLAY_I_ADDR_OFFSET                   0x3FFFC68C
     94#define HYDRA_DMD_DISPLAY_Q_ADDR_OFFSET                   0x3FFFC68E
     95
     96#define HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET            0x3FFFC690
     97#define HYDRA_DMD_DVBS2_PER_COUNT_ADDR_OFFSET             0x3FFFC694
     98#define HYDRA_DMD_DVBS2_PER_WINDOW_ADDR_OFFSET            0x3FFFC698
     99
    100#define HYDRA_DMD_DVBS_CORR_RS_ERRORS_ADDR_OFFSET         0x3FFFC69C
    101#define HYDRA_DMD_DVBS_UNCORR_RS_ERRORS_ADDR_OFFSET       0x3FFFC6A0
    102#define HYDRA_DMD_DVBS_BER_COUNT_ADDR_OFFSET              0x3FFFC6A4
    103#define HYDRA_DMD_DVBS_BER_WINDOW_ADDR_OFFSET             0x3FFFC6A8
    104
    105/* Debug-purpose DVB-S DMD 0 */
    106#define HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET     0x3FFFC6C8  /* corrected RS Errors: 1st iteration */
    107#define HYDRA_DMD_DVBS_1ST_UNCORR_RS_ERRORS_ADDR_OFFSET   0x3FFFC6CC  /* uncorrected RS Errors: 1st iteration */
    108#define HYDRA_DMD_DVBS_BER_COUNT_1ST_ADDR_OFFSET          0x3FFFC6D0
    109#define HYDRA_DMD_DVBS_BER_WINDOW_1ST_ADDR_OFFSET         0x3FFFC6D4
    110
    111#define HYDRA_DMD_TUNER_ID_ADDR_OFFSET                    0x3FFFC6AC
    112#define HYDRA_DMD_DVBS2_PILOT_ON_OFF_ADDR_OFFSET          0x3FFFC6B0
    113#define HYDRA_DMD_FREQ_SEARCH_RANGE_KHZ_ADDR_OFFSET       0x3FFFC6B4
    114#define HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET                 0x3FFFC6B8
    115#define HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR          0x3FFFC704
    116#define HYDRA_DMD_STATUS_INPUT_POWER_ADDR                 0x3FFFC708
    117
    118/* DVB-S new scaled_BER_count for a new BER API, see HYDRA-1343 "DVB-S post viterbi information" */
    119#define DMD0_STATUS_DVBS_1ST_SCALED_BER_COUNT_ADDR        0x3FFFC710 /* DMD 0: 1st iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR */
    120#define DMD0_STATUS_DVBS_SCALED_BER_COUNT_ADDR            0x3FFFC714 /* DMD 0: 2nd iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR */
    121
    122#define DMD0_SPECTRUM_MIN_GAIN_STATUS                     0x3FFFC73C
    123#define DMD0_SPECTRUM_MIN_GAIN_WB_SAGC_VALUE              0x3FFFC740
    124#define DMD0_SPECTRUM_MIN_GAIN_NB_SAGC_VALUE              0x3FFFC744
    125
    126#define HYDRA_DMD_STATUS_END_ADDR_OFFSET                  0x3FFFC748
    127
    128/* Tuner status address offset from respective tuners's base address */
    129#define HYDRA_TUNER_DEMOD_ID_ADDR_OFFSET                  0x3FFFCE4C
    130#define HYDRA_TUNER_AGC_LOCK_OFFSET                       0x3FFFCE50
    131#define HYDRA_TUNER_SPECTRUM_STATUS_OFFSET                0x3FFFCE54
    132#define HYDRA_TUNER_SPECTRUM_BIN_SIZE_OFFSET              0x3FFFCE58
    133#define HYDRA_TUNER_SPECTRUM_ADDRESS_OFFSET               0x3FFFCE5C
    134#define HYDRA_TUNER_ENABLE_COMPLETE                       0x3FFFEB78
    135
    136#define HYDRA_DEMOD_STATUS_LOCK(devId, demodId)   write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_YES)
    137#define HYDRA_DEMOD_STATUS_UNLOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_NO)
    138
    139#define HYDRA_VERSION                                     0x3FFFEDB8
    140#define HYDRA_DEMOD0_VERSION                              0x3FFFEDBC
    141#define HYDRA_DEMOD1_VERSION                              0x3FFFEDC0
    142#define HYDRA_DEMOD2_VERSION                              0x3FFFEDC4
    143#define HYDRA_DEMOD3_VERSION                              0x3FFFEDC8
    144#define HYDRA_DEMOD4_VERSION                              0x3FFFEDCC
    145#define HYDRA_DEMOD5_VERSION                              0x3FFFEDD0
    146#define HYDRA_DEMOD6_VERSION                              0x3FFFEDD4
    147#define HYDRA_DEMOD7_VERSION                              0x3FFFEDD8
    148#define HYDRA_HEAR_BEAT                                   0x3FFFEDDC
    149#define HYDRA_SKU_MGMT                                    0x3FFFEBC0
    150
    151#define MXL_HYDRA_FPGA_A_ADDRESS                          0x91C00000
    152#define MXL_HYDRA_FPGA_B_ADDRESS                          0x91D00000
    153
    154/* TS control base address */
    155#define HYDRA_TS_CTRL_BASE_ADDR                           0x90700000
    156
    157#define MPEG_MUX_MODE_SLICE0_REG            (HYDRA_TS_CTRL_BASE_ADDR + 0x08)
    158
    159#define MPEG_MUX_MODE_SLICE1_REG            (HYDRA_TS_CTRL_BASE_ADDR + 0x08)
    160
    161#define PID_BANK_SEL_SLICE0_REG             (HYDRA_TS_CTRL_BASE_ADDR + 0x190)
    162#define PID_BANK_SEL_SLICE1_REG             (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0)
    163
    164#define MPEG_CLK_GATED_REG                  (HYDRA_TS_CTRL_BASE_ADDR + 0x20)
    165
    166#define MPEG_CLK_ALWAYS_ON_REG              (HYDRA_TS_CTRL_BASE_ADDR + 0x1D4)
    167
    168#define HYDRA_REGULAR_PID_BANK_A_REG        (HYDRA_TS_CTRL_BASE_ADDR + 0x190)
    169
    170#define HYDRA_FIXED_PID_BANK_A_REG          (HYDRA_TS_CTRL_BASE_ADDR + 0x190)
    171
    172#define HYDRA_REGULAR_PID_BANK_B_REG        (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0)
    173
    174#define HYDRA_FIXED_PID_BANK_B_REG          (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0)
    175
    176#define FIXED_PID_TBL_REG_ADDRESS_0         (HYDRA_TS_CTRL_BASE_ADDR + 0x9000)
    177#define FIXED_PID_TBL_REG_ADDRESS_1         (HYDRA_TS_CTRL_BASE_ADDR + 0x9100)
    178#define FIXED_PID_TBL_REG_ADDRESS_2         (HYDRA_TS_CTRL_BASE_ADDR + 0x9200)
    179#define FIXED_PID_TBL_REG_ADDRESS_3         (HYDRA_TS_CTRL_BASE_ADDR + 0x9300)
    180
    181#define FIXED_PID_TBL_REG_ADDRESS_4         (HYDRA_TS_CTRL_BASE_ADDR + 0xB000)
    182#define FIXED_PID_TBL_REG_ADDRESS_5         (HYDRA_TS_CTRL_BASE_ADDR + 0xB100)
    183#define FIXED_PID_TBL_REG_ADDRESS_6         (HYDRA_TS_CTRL_BASE_ADDR + 0xB200)
    184#define FIXED_PID_TBL_REG_ADDRESS_7         (HYDRA_TS_CTRL_BASE_ADDR + 0xB300)
    185
    186#define REGULAR_PID_TBL_REG_ADDRESS_0       (HYDRA_TS_CTRL_BASE_ADDR + 0x8000)
    187#define REGULAR_PID_TBL_REG_ADDRESS_1       (HYDRA_TS_CTRL_BASE_ADDR + 0x8200)
    188#define REGULAR_PID_TBL_REG_ADDRESS_2       (HYDRA_TS_CTRL_BASE_ADDR + 0x8400)
    189#define REGULAR_PID_TBL_REG_ADDRESS_3       (HYDRA_TS_CTRL_BASE_ADDR + 0x8600)
    190
    191#define REGULAR_PID_TBL_REG_ADDRESS_4       (HYDRA_TS_CTRL_BASE_ADDR + 0xA000)
    192#define REGULAR_PID_TBL_REG_ADDRESS_5       (HYDRA_TS_CTRL_BASE_ADDR + 0xA200)
    193#define REGULAR_PID_TBL_REG_ADDRESS_6       (HYDRA_TS_CTRL_BASE_ADDR + 0xA400)
    194#define REGULAR_PID_TBL_REG_ADDRESS_7       (HYDRA_TS_CTRL_BASE_ADDR + 0xA600)
    195
    196/***************************************************************************/
    197
    198#define PAD_MUX_GPIO_00_SYNC_BASEADDR                          0x90000188
    199
    200
    201#define PAD_MUX_UART_RX_C_PINMUX_BASEADDR 0x9000001C
    202
    203#define   XPT_PACKET_GAP_MIN_BASEADDR                            0x90700044
    204#define   XPT_NCO_COUNT_BASEADDR                                 0x90700238
    205
    206#define   XPT_NCO_COUNT_BASEADDR1                                0x9070023C
    207
    208/* V2 DigRF status register */
    209
    210#define   XPT_PID_BASEADDR                                       0x90708000
    211
    212#define   XPT_PID_REMAP_BASEADDR                                 0x90708004
    213
    214#define   XPT_KNOWN_PID_BASEADDR                                 0x90709000
    215
    216#define   XPT_PID_BASEADDR1                                      0x9070A000
    217
    218#define   XPT_PID_REMAP_BASEADDR1                                0x9070A004
    219
    220#define   XPT_KNOWN_PID_BASEADDR1                                0x9070B000
    221
    222#define   XPT_BERT_LOCK_BASEADDR                                 0x907000B8
    223
    224#define   XPT_BERT_BASEADDR                                      0x907000BC
    225
    226#define   XPT_BERT_INVERT_BASEADDR                               0x907000C0
    227
    228#define   XPT_BERT_HEADER_BASEADDR                               0x907000C4
    229
    230#define   XPT_BERT_BASEADDR1                                     0x907000C8
    231
    232#define   XPT_BERT_BIT_COUNT0_BASEADDR                           0x907000CC
    233
    234#define   XPT_BERT_BIT_COUNT0_BASEADDR1                          0x907000D0
    235
    236#define   XPT_BERT_BIT_COUNT1_BASEADDR                           0x907000D4
    237
    238#define   XPT_BERT_BIT_COUNT1_BASEADDR1                          0x907000D8
    239
    240#define   XPT_BERT_BIT_COUNT2_BASEADDR                           0x907000DC
    241
    242#define   XPT_BERT_BIT_COUNT2_BASEADDR1                          0x907000E0
    243
    244#define   XPT_BERT_BIT_COUNT3_BASEADDR                           0x907000E4
    245
    246#define   XPT_BERT_BIT_COUNT3_BASEADDR1                          0x907000E8
    247
    248#define   XPT_BERT_BIT_COUNT4_BASEADDR                           0x907000EC
    249
    250#define   XPT_BERT_BIT_COUNT4_BASEADDR1                          0x907000F0
    251
    252#define   XPT_BERT_BIT_COUNT5_BASEADDR                           0x907000F4
    253
    254#define   XPT_BERT_BIT_COUNT5_BASEADDR1                          0x907000F8
    255
    256#define   XPT_BERT_BIT_COUNT6_BASEADDR                           0x907000FC
    257
    258#define   XPT_BERT_BIT_COUNT6_BASEADDR1                          0x90700100
    259
    260#define   XPT_BERT_BIT_COUNT7_BASEADDR                           0x90700104
    261
    262#define   XPT_BERT_BIT_COUNT7_BASEADDR1                          0x90700108
    263
    264#define   XPT_BERT_ERR_COUNT0_BASEADDR                           0x9070010C
    265
    266#define   XPT_BERT_ERR_COUNT0_BASEADDR1                          0x90700110
    267
    268#define   XPT_BERT_ERR_COUNT1_BASEADDR                           0x90700114
    269
    270#define   XPT_BERT_ERR_COUNT1_BASEADDR1                          0x90700118
    271
    272#define   XPT_BERT_ERR_COUNT2_BASEADDR                           0x9070011C
    273
    274#define   XPT_BERT_ERR_COUNT2_BASEADDR1                          0x90700120
    275
    276#define   XPT_BERT_ERR_COUNT3_BASEADDR                           0x90700124
    277
    278#define   XPT_BERT_ERR_COUNT3_BASEADDR1                          0x90700128
    279
    280#define   XPT_BERT_ERR_COUNT4_BASEADDR                           0x9070012C
    281
    282#define   XPT_BERT_ERR_COUNT4_BASEADDR1                          0x90700130
    283
    284#define   XPT_BERT_ERR_COUNT5_BASEADDR                           0x90700134
    285
    286#define   XPT_BERT_ERR_COUNT5_BASEADDR1                          0x90700138
    287
    288#define   XPT_BERT_ERR_COUNT6_BASEADDR                           0x9070013C
    289
    290#define   XPT_BERT_ERR_COUNT6_BASEADDR1                          0x90700140
    291
    292#define   XPT_BERT_ERR_COUNT7_BASEADDR                           0x90700144
    293
    294#define   XPT_BERT_ERR_COUNT7_BASEADDR1                          0x90700148
    295
    296#define   XPT_BERT_ERROR_BASEADDR                                0x9070014C
    297
    298#define   XPT_BERT_ANALYZER_BASEADDR                             0x90700150
    299
    300#define   XPT_BERT_ANALYZER_BASEADDR1                            0x90700154
    301
    302#define   XPT_BERT_ANALYZER_BASEADDR2                            0x90700158
    303
    304#define   XPT_BERT_ANALYZER_BASEADDR3                            0x9070015C
    305
    306#define   XPT_BERT_ANALYZER_BASEADDR4                            0x90700160
    307
    308#define   XPT_BERT_ANALYZER_BASEADDR5                            0x90700164
    309
    310#define   XPT_BERT_ANALYZER_BASEADDR6                            0x90700168
    311
    312#define   XPT_BERT_ANALYZER_BASEADDR7                            0x9070016C
    313
    314#define   XPT_BERT_ANALYZER_BASEADDR8                            0x90700170
    315
    316#define   XPT_BERT_ANALYZER_BASEADDR9                            0x90700174
    317
    318#define   XPT_DMD0_BASEADDR                                      0x9070024C
    319
    320/* V2 AGC Gain Freeze & step */
    321#define   DBG_ENABLE_DISABLE_AGC                                 (0x3FFFCF60) /* 1: DISABLE, 0:ENABLE */
    322#define   WB_DFE0_DFE_FB_RF1_BASEADDR                            0x903004A4
    323
    324#define   WB_DFE1_DFE_FB_RF1_BASEADDR                            0x904004A4
    325
    326#define   WB_DFE2_DFE_FB_RF1_BASEADDR                            0x905004A4
    327
    328#define   WB_DFE3_DFE_FB_RF1_BASEADDR                            0x906004A4
    329
    330#define   AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR                0x90200104
    331
    332#define   AFE_REG_AFE_REG_SPARE_BASEADDR                         0x902000A0
    333
    334#define   AFE_REG_AFE_REG_SPARE_BASEADDR1                        0x902000B4
    335
    336#define   AFE_REG_AFE_REG_SPARE_BASEADDR2                        0x902000C4
    337
    338#define   AFE_REG_AFE_REG_SPARE_BASEADDR3                        0x902000D4
    339
    340#define   WB_DFE0_DFE_FB_AGC_BASEADDR                            0x90300498
    341
    342#define   WB_DFE1_DFE_FB_AGC_BASEADDR                            0x90400498
    343
    344#define   WB_DFE2_DFE_FB_AGC_BASEADDR                            0x90500498
    345
    346#define   WB_DFE3_DFE_FB_AGC_BASEADDR                            0x90600498
    347
    348#define   WDT_WD_INT_BASEADDR                                    0x8002000C
    349
    350#define   FSK_TX_FTM_BASEADDR                                    0x80090000
    351
    352#define   FSK_TX_FTM_TX_CNT_BASEADDR                             0x80090018
    353
    354#define   AFE_REG_D2A_FSK_BIAS_BASEADDR                          0x90200040
    355
    356#define   DMD_TEI_BASEADDR                                       0x3FFFEBE0
    357
    358#endif /* __MXL58X_REGISTERS_H__ */