cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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aptina-pll.h (865B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Aptina Sensor PLL Configuration
      4 *
      5 * Copyright (C) 2012 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
      6 */
      7
      8#ifndef __APTINA_PLL_H
      9#define __APTINA_PLL_H
     10
     11struct aptina_pll {
     12	unsigned int ext_clock;
     13	unsigned int pix_clock;
     14
     15	unsigned int n;
     16	unsigned int m;
     17	unsigned int p1;
     18};
     19
     20struct aptina_pll_limits {
     21	unsigned int ext_clock_min;
     22	unsigned int ext_clock_max;
     23	unsigned int int_clock_min;
     24	unsigned int int_clock_max;
     25	unsigned int out_clock_min;
     26	unsigned int out_clock_max;
     27	unsigned int pix_clock_max;
     28
     29	unsigned int n_min;
     30	unsigned int n_max;
     31	unsigned int m_min;
     32	unsigned int m_max;
     33	unsigned int p1_min;
     34	unsigned int p1_max;
     35};
     36
     37struct device;
     38
     39int aptina_pll_calculate(struct device *dev,
     40			 const struct aptina_pll_limits *limits,
     41			 struct aptina_pll *pll);
     42
     43#endif /* __APTINA_PLL_H */