cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ccs-quirk.c (6828B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * drivers/media/i2c/ccs/ccs-quirk.c
      4 *
      5 * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
      6 *
      7 * Copyright (C) 2020 Intel Corporation
      8 * Copyright (C) 2011--2012 Nokia Corporation
      9 * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
     10 */
     11
     12#include <linux/delay.h>
     13
     14#include "ccs.h"
     15#include "ccs-limits.h"
     16
     17static int ccs_write_addr_8s(struct ccs_sensor *sensor,
     18			     const struct ccs_reg_8 *regs, int len)
     19{
     20	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
     21	int rval;
     22
     23	for (; len > 0; len--, regs++) {
     24		rval = ccs_write_addr(sensor, regs->reg, regs->val);
     25		if (rval < 0) {
     26			dev_err(&client->dev,
     27				"error %d writing reg 0x%4.4x, val 0x%2.2x",
     28				rval, regs->reg, regs->val);
     29			return rval;
     30		}
     31	}
     32
     33	return 0;
     34}
     35
     36static int jt8ew9_limits(struct ccs_sensor *sensor)
     37{
     38	if (sensor->minfo.revision_number < 0x0300)
     39		sensor->frame_skip = 1;
     40
     41	/* Below 24 gain doesn't have effect at all, */
     42	/* but ~59 is needed for full dynamic range */
     43	ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MIN, 0, 59);
     44	ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MAX, 0, 6000);
     45
     46	return 0;
     47}
     48
     49static int jt8ew9_post_poweron(struct ccs_sensor *sensor)
     50{
     51	static const struct ccs_reg_8 regs[] = {
     52		{ 0x30a3, 0xd8 }, /* Output port control : LVDS ports only */
     53		{ 0x30ae, 0x00 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
     54		{ 0x30af, 0xd0 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
     55		{ 0x322d, 0x04 }, /* Adjusting Processing Image Size to Scaler Toshiba Recommendation Setting */
     56		{ 0x3255, 0x0f }, /* Horizontal Noise Reduction Control Toshiba Recommendation Setting */
     57		{ 0x3256, 0x15 }, /* Horizontal Noise Reduction Control Toshiba Recommendation Setting */
     58		{ 0x3258, 0x70 }, /* Analog Gain Control Toshiba Recommendation Setting */
     59		{ 0x3259, 0x70 }, /* Analog Gain Control Toshiba Recommendation Setting */
     60		{ 0x325f, 0x7c }, /* Analog Gain Control Toshiba Recommendation Setting */
     61		{ 0x3302, 0x06 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
     62		{ 0x3304, 0x00 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
     63		{ 0x3307, 0x22 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
     64		{ 0x3308, 0x8d }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
     65		{ 0x331e, 0x0f }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
     66		{ 0x3320, 0x30 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
     67		{ 0x3321, 0x11 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
     68		{ 0x3322, 0x98 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
     69		{ 0x3323, 0x64 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
     70		{ 0x3325, 0x83 }, /* Read Out Timing Control Toshiba Recommendation Setting */
     71		{ 0x3330, 0x18 }, /* Read Out Timing Control Toshiba Recommendation Setting */
     72		{ 0x333c, 0x01 }, /* Read Out Timing Control Toshiba Recommendation Setting */
     73		{ 0x3345, 0x2f }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
     74		{ 0x33de, 0x38 }, /* Horizontal Noise Reduction Control Toshiba Recommendation Setting */
     75		/* Taken from v03. No idea what the rest are. */
     76		{ 0x32e0, 0x05 },
     77		{ 0x32e1, 0x05 },
     78		{ 0x32e2, 0x04 },
     79		{ 0x32e5, 0x04 },
     80		{ 0x32e6, 0x04 },
     81
     82	};
     83
     84	return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
     85}
     86
     87const struct ccs_quirk smiapp_jt8ew9_quirk = {
     88	.limits = jt8ew9_limits,
     89	.post_poweron = jt8ew9_post_poweron,
     90};
     91
     92static int imx125es_post_poweron(struct ccs_sensor *sensor)
     93{
     94	/* Taken from v02. No idea what the other two are. */
     95	static const struct ccs_reg_8 regs[] = {
     96		/*
     97		 * 0x3302: clk during frame blanking:
     98		 * 0x00 - HS mode, 0x01 - LP11
     99		 */
    100		{ 0x3302, 0x01 },
    101		{ 0x302d, 0x00 },
    102		{ 0x3b08, 0x8c },
    103	};
    104
    105	return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
    106}
    107
    108const struct ccs_quirk smiapp_imx125es_quirk = {
    109	.post_poweron = imx125es_post_poweron,
    110};
    111
    112static int jt8ev1_limits(struct ccs_sensor *sensor)
    113{
    114	ccs_replace_limit(sensor, CCS_L_X_ADDR_MAX, 0, 4271);
    115	ccs_replace_limit(sensor, CCS_L_MIN_LINE_BLANKING_PCK_BIN, 0, 184);
    116
    117	return 0;
    118}
    119
    120static int jt8ev1_post_poweron(struct ccs_sensor *sensor)
    121{
    122	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
    123	int rval;
    124	static const struct ccs_reg_8 regs[] = {
    125		{ 0x3031, 0xcd }, /* For digital binning (EQ_MONI) */
    126		{ 0x30a3, 0xd0 }, /* FLASH STROBE enable */
    127		{ 0x3237, 0x00 }, /* For control of pulse timing for ADC */
    128		{ 0x3238, 0x43 },
    129		{ 0x3301, 0x06 }, /* For analog bias for sensor */
    130		{ 0x3302, 0x06 },
    131		{ 0x3304, 0x00 },
    132		{ 0x3305, 0x88 },
    133		{ 0x332a, 0x14 },
    134		{ 0x332c, 0x6b },
    135		{ 0x3336, 0x01 },
    136		{ 0x333f, 0x1f },
    137		{ 0x3355, 0x00 },
    138		{ 0x3356, 0x20 },
    139		{ 0x33bf, 0x20 }, /* Adjust the FBC speed */
    140		{ 0x33c9, 0x20 },
    141		{ 0x33ce, 0x30 }, /* Adjust the parameter for logic function */
    142		{ 0x33cf, 0xec }, /* For Black sun */
    143		{ 0x3328, 0x80 }, /* Ugh. No idea what's this. */
    144	};
    145	static const struct ccs_reg_8 regs_96[] = {
    146		{ 0x30ae, 0x00 }, /* For control of ADC clock */
    147		{ 0x30af, 0xd0 },
    148		{ 0x30b0, 0x01 },
    149	};
    150
    151	rval = ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
    152	if (rval < 0)
    153		return rval;
    154
    155	switch (sensor->hwcfg.ext_clk) {
    156	case 9600000:
    157		return ccs_write_addr_8s(sensor, regs_96,
    158				       ARRAY_SIZE(regs_96));
    159	default:
    160		dev_warn(&client->dev, "no MSRs for %d Hz ext_clk\n",
    161			 sensor->hwcfg.ext_clk);
    162		return 0;
    163	}
    164}
    165
    166static int jt8ev1_pre_streamon(struct ccs_sensor *sensor)
    167{
    168	return ccs_write_addr(sensor, 0x3328, 0x00);
    169}
    170
    171static int jt8ev1_post_streamoff(struct ccs_sensor *sensor)
    172{
    173	int rval;
    174
    175	/* Workaround: allows fast standby to work properly */
    176	rval = ccs_write_addr(sensor, 0x3205, 0x04);
    177	if (rval < 0)
    178		return rval;
    179
    180	/* Wait for 1 ms + one line => 2 ms is likely enough */
    181	usleep_range(2000, 2050);
    182
    183	/* Restore it */
    184	rval = ccs_write_addr(sensor, 0x3205, 0x00);
    185	if (rval < 0)
    186		return rval;
    187
    188	return ccs_write_addr(sensor, 0x3328, 0x80);
    189}
    190
    191static int jt8ev1_init(struct ccs_sensor *sensor)
    192{
    193	sensor->pll.flags |= CCS_PLL_FLAG_LANE_SPEED_MODEL |
    194		CCS_PLL_FLAG_LINK_DECOUPLED;
    195	sensor->pll.vt_lanes = 1;
    196	sensor->pll.op_lanes = sensor->pll.csi2.lanes;
    197
    198	return 0;
    199}
    200
    201const struct ccs_quirk smiapp_jt8ev1_quirk = {
    202	.limits = jt8ev1_limits,
    203	.post_poweron = jt8ev1_post_poweron,
    204	.pre_streamon = jt8ev1_pre_streamon,
    205	.post_streamoff = jt8ev1_post_streamoff,
    206	.init = jt8ev1_init,
    207};
    208
    209static int tcm8500md_limits(struct ccs_sensor *sensor)
    210{
    211	ccs_replace_limit(sensor, CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ, 0, 2700000);
    212
    213	return 0;
    214}
    215
    216const struct ccs_quirk smiapp_tcm8500md_quirk = {
    217	.limits = tcm8500md_limits,
    218};