cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ccs-quirk.h (2630B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * drivers/media/i2c/ccs/ccs-quirk.h
      4 *
      5 * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
      6 *
      7 * Copyright (C) 2020 Intel Corporation
      8 * Copyright (C) 2011--2012 Nokia Corporation
      9 * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
     10 */
     11
     12#ifndef __CCS_QUIRK__
     13#define __CCS_QUIRK__
     14
     15struct ccs_sensor;
     16
     17/**
     18 * struct ccs_quirk - quirks for sensors that deviate from SMIA++ standard
     19 *
     20 * @limits: Replace sensor->limits with values which can't be read from
     21 *	    sensor registers. Called the first time the sensor is powered up.
     22 * @post_poweron: Called always after the sensor has been fully powered on.
     23 * @pre_streamon: Called just before streaming is enabled.
     24 * @post_streamoff: Called right after stopping streaming.
     25 * @pll_flags: Return flags for the PLL calculator.
     26 * @init: Quirk initialisation, called the last in probe(). This is
     27 *	  also appropriate for adding sensor specific controls, for instance.
     28 * @reg_access: Register access quirk. The quirk may divert the access
     29 *		to another register, or no register at all.
     30 *
     31 *		@write: Is this read (false) or write (true) access?
     32 *		@reg: Pointer to the register to access
     33 *		@value: Register value, set by the caller on write, or
     34 *			by the quirk on read
     35 *
     36 * @flags: Quirk flags
     37 *
     38 *		@return: 0 on success, -ENOIOCTLCMD if no register
     39 *			 access may be done by the caller (default read
     40 *			 value is zero), else negative error code on error
     41 */
     42struct ccs_quirk {
     43	int (*limits)(struct ccs_sensor *sensor);
     44	int (*post_poweron)(struct ccs_sensor *sensor);
     45	int (*pre_streamon)(struct ccs_sensor *sensor);
     46	int (*post_streamoff)(struct ccs_sensor *sensor);
     47	unsigned long (*pll_flags)(struct ccs_sensor *sensor);
     48	int (*init)(struct ccs_sensor *sensor);
     49	int (*reg_access)(struct ccs_sensor *sensor, bool write, u32 *reg,
     50			  u32 *val);
     51	unsigned long flags;
     52};
     53
     54#define CCS_QUIRK_FLAG_8BIT_READ_ONLY			(1 << 0)
     55
     56struct ccs_reg_8 {
     57	u16 reg;
     58	u8 val;
     59};
     60
     61#define CCS_MK_QUIRK_REG_8(_reg, _val) \
     62	{				\
     63		.reg = (u16)_reg,	\
     64		.val = _val,		\
     65	}
     66
     67#define ccs_call_quirk(sensor, _quirk, ...)				\
     68	((sensor)->minfo.quirk &&					\
     69	 (sensor)->minfo.quirk->_quirk ?				\
     70	 (sensor)->minfo.quirk->_quirk(sensor, ##__VA_ARGS__) : 0)
     71
     72#define ccs_needs_quirk(sensor, _quirk)		\
     73	((sensor)->minfo.quirk ?			\
     74	 (sensor)->minfo.quirk->flags & _quirk : 0)
     75
     76extern const struct ccs_quirk smiapp_jt8ev1_quirk;
     77extern const struct ccs_quirk smiapp_imx125es_quirk;
     78extern const struct ccs_quirk smiapp_jt8ew9_quirk;
     79extern const struct ccs_quirk smiapp_tcm8500md_quirk;
     80
     81#endif /* __CCS_QUIRK__ */