cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ov7251.c (43565B)


      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Driver for the OV7251 camera sensor.
      4 *
      5 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
      6 * Copyright (c) 2017-2018, Linaro Ltd.
      7 */
      8
      9#include <linux/bitops.h>
     10#include <linux/clk.h>
     11#include <linux/delay.h>
     12#include <linux/device.h>
     13#include <linux/gpio/consumer.h>
     14#include <linux/i2c.h>
     15#include <linux/init.h>
     16#include <linux/module.h>
     17#include <linux/mod_devicetable.h>
     18#include <linux/pm_runtime.h>
     19#include <linux/regulator/consumer.h>
     20#include <linux/slab.h>
     21#include <linux/types.h>
     22#include <media/v4l2-ctrls.h>
     23#include <media/v4l2-fwnode.h>
     24#include <media/v4l2-subdev.h>
     25
     26#define OV7251_SC_MODE_SELECT		0x0100
     27#define OV7251_SC_MODE_SELECT_SW_STANDBY	0x0
     28#define OV7251_SC_MODE_SELECT_STREAMING		0x1
     29
     30#define OV7251_CHIP_ID_HIGH		0x300a
     31#define OV7251_CHIP_ID_HIGH_BYTE	0x77
     32#define OV7251_CHIP_ID_LOW		0x300b
     33#define OV7251_CHIP_ID_LOW_BYTE		0x50
     34#define OV7251_SC_GP_IO_IN1		0x3029
     35#define OV7251_AEC_EXPO_0		0x3500
     36#define OV7251_AEC_EXPO_1		0x3501
     37#define OV7251_AEC_EXPO_2		0x3502
     38#define OV7251_AEC_AGC_ADJ_0		0x350a
     39#define OV7251_AEC_AGC_ADJ_1		0x350b
     40#define OV7251_TIMING_FORMAT1		0x3820
     41#define OV7251_TIMING_FORMAT1_VFLIP	BIT(2)
     42#define OV7251_TIMING_FORMAT2		0x3821
     43#define OV7251_TIMING_FORMAT2_MIRROR	BIT(2)
     44#define OV7251_PRE_ISP_00		0x5e00
     45#define OV7251_PRE_ISP_00_TEST_PATTERN	BIT(7)
     46#define OV7251_PLL1_PRE_DIV_REG		0x30b4
     47#define OV7251_PLL1_MULT_REG		0x30b3
     48#define OV7251_PLL1_DIVIDER_REG		0x30b1
     49#define OV7251_PLL1_PIX_DIV_REG		0x30b0
     50#define OV7251_PLL1_MIPI_DIV_REG	0x30b5
     51#define OV7251_PLL2_PRE_DIV_REG		0x3098
     52#define OV7251_PLL2_MULT_REG		0x3099
     53#define OV7251_PLL2_DIVIDER_REG		0x309d
     54#define OV7251_PLL2_SYS_DIV_REG		0x309a
     55#define OV7251_PLL2_ADC_DIV_REG		0x309b
     56
     57#define OV7251_NATIVE_WIDTH		656
     58#define OV7251_NATIVE_HEIGHT		496
     59#define OV7251_ACTIVE_START_LEFT	4
     60#define OV7251_ACTIVE_START_TOP		4
     61#define OV7251_ACTIVE_WIDTH		648
     62#define OV7251_ACTIVE_HEIGHT		488
     63
     64#define OV7251_FIXED_PPL		928
     65#define OV7251_TIMING_VTS_REG		0x380e
     66#define OV7251_TIMING_MIN_VTS		1
     67#define OV7251_TIMING_MAX_VTS		0xffff
     68#define OV7251_INTEGRATION_MARGIN	20
     69
     70struct reg_value {
     71	u16 reg;
     72	u8 val;
     73};
     74
     75struct ov7251_mode_info {
     76	u32 width;
     77	u32 height;
     78	u32 vts;
     79	const struct reg_value *data;
     80	u32 data_size;
     81	u32 pixel_clock;
     82	u32 link_freq;
     83	u16 exposure_max;
     84	u16 exposure_def;
     85	struct v4l2_fract timeperframe;
     86};
     87
     88struct ov7251_pll1_cfg {
     89	unsigned int pre_div;
     90	unsigned int mult;
     91	unsigned int div;
     92	unsigned int pix_div;
     93	unsigned int mipi_div;
     94};
     95
     96struct ov7251_pll2_cfg {
     97	unsigned int pre_div;
     98	unsigned int mult;
     99	unsigned int div;
    100	unsigned int sys_div;
    101	unsigned int adc_div;
    102};
    103
    104/*
    105 * Rubbish ordering, but only PLL1 needs to have a separate configuration per
    106 * link frequency and the array member needs to be last.
    107 */
    108struct ov7251_pll_cfgs {
    109	const struct ov7251_pll2_cfg *pll2;
    110	const struct ov7251_pll1_cfg *pll1[];
    111};
    112
    113enum xclk_rate {
    114	OV7251_19_2_MHZ,
    115	OV7251_24_MHZ,
    116	OV7251_NUM_SUPPORTED_RATES
    117};
    118
    119enum supported_link_freqs {
    120	OV7251_LINK_FREQ_240_MHZ,
    121	OV7251_LINK_FREQ_319_2_MHZ,
    122	OV7251_NUM_SUPPORTED_LINK_FREQS
    123};
    124
    125struct ov7251 {
    126	struct i2c_client *i2c_client;
    127	struct device *dev;
    128	struct v4l2_subdev sd;
    129	struct media_pad pad;
    130	struct v4l2_fwnode_endpoint ep;
    131	struct v4l2_mbus_framefmt fmt;
    132	struct v4l2_rect crop;
    133	struct clk *xclk;
    134	u32 xclk_freq;
    135
    136	struct regulator *io_regulator;
    137	struct regulator *core_regulator;
    138	struct regulator *analog_regulator;
    139
    140	const struct ov7251_pll_cfgs *pll_cfgs;
    141	enum supported_link_freqs link_freq_idx;
    142	const struct ov7251_mode_info *current_mode;
    143
    144	struct v4l2_ctrl_handler ctrls;
    145	struct v4l2_ctrl *pixel_clock;
    146	struct v4l2_ctrl *link_freq;
    147	struct v4l2_ctrl *exposure;
    148	struct v4l2_ctrl *gain;
    149	struct v4l2_ctrl *hblank;
    150	struct v4l2_ctrl *vblank;
    151
    152	/* Cached register values */
    153	u8 aec_pk_manual;
    154	u8 pre_isp_00;
    155	u8 timing_format1;
    156	u8 timing_format2;
    157
    158	struct mutex lock; /* lock to protect power state, ctrls and mode */
    159	bool power_on;
    160
    161	struct gpio_desc *enable_gpio;
    162};
    163
    164static inline struct ov7251 *to_ov7251(struct v4l2_subdev *sd)
    165{
    166	return container_of(sd, struct ov7251, sd);
    167}
    168
    169static const struct ov7251_pll1_cfg ov7251_pll1_cfg_19_2_mhz_240_mhz = {
    170	.pre_div = 0x03,
    171	.mult = 0x4b,
    172	.div = 0x01,
    173	.pix_div = 0x0a,
    174	.mipi_div = 0x05,
    175};
    176
    177static const struct ov7251_pll1_cfg ov7251_pll1_cfg_19_2_mhz_319_2_mhz = {
    178	.pre_div = 0x01,
    179	.mult = 0x85,
    180	.div = 0x04,
    181	.pix_div = 0x0a,
    182	.mipi_div = 0x05,
    183};
    184
    185static const struct ov7251_pll1_cfg ov7251_pll1_cfg_24_mhz_240_mhz = {
    186	.pre_div = 0x03,
    187	.mult = 0x64,
    188	.div = 0x01,
    189	.pix_div = 0x0a,
    190	.mipi_div = 0x05,
    191};
    192
    193static const struct ov7251_pll1_cfg ov7251_pll1_cfg_24_mhz_319_2_mhz = {
    194	.pre_div = 0x05,
    195	.mult = 0x85,
    196	.div = 0x02,
    197	.pix_div = 0x0a,
    198	.mipi_div = 0x05,
    199};
    200
    201static const struct ov7251_pll2_cfg ov7251_pll2_cfg_19_2_mhz = {
    202	.pre_div = 0x04,
    203	.mult = 0x32,
    204	.div = 0x00,
    205	.sys_div = 0x05,
    206	.adc_div = 0x04,
    207};
    208
    209static const struct ov7251_pll2_cfg ov7251_pll2_cfg_24_mhz = {
    210	.pre_div = 0x04,
    211	.mult = 0x28,
    212	.div = 0x00,
    213	.sys_div = 0x05,
    214	.adc_div = 0x04,
    215};
    216
    217static const struct ov7251_pll_cfgs ov7251_pll_cfgs_19_2_mhz = {
    218	.pll2 = &ov7251_pll2_cfg_19_2_mhz,
    219	.pll1 = {
    220		[OV7251_LINK_FREQ_240_MHZ] = &ov7251_pll1_cfg_19_2_mhz_240_mhz,
    221		[OV7251_LINK_FREQ_319_2_MHZ] = &ov7251_pll1_cfg_19_2_mhz_319_2_mhz,
    222	},
    223};
    224
    225static const struct ov7251_pll_cfgs ov7251_pll_cfgs_24_mhz = {
    226	.pll2 = &ov7251_pll2_cfg_24_mhz,
    227	.pll1 = {
    228		[OV7251_LINK_FREQ_240_MHZ] = &ov7251_pll1_cfg_24_mhz_240_mhz,
    229		[OV7251_LINK_FREQ_319_2_MHZ] = &ov7251_pll1_cfg_24_mhz_319_2_mhz,
    230	},
    231};
    232
    233static const struct ov7251_pll_cfgs *ov7251_pll_cfgs[] = {
    234	[OV7251_19_2_MHZ] = &ov7251_pll_cfgs_19_2_mhz,
    235	[OV7251_24_MHZ] = &ov7251_pll_cfgs_24_mhz,
    236};
    237
    238static const struct reg_value ov7251_global_init_setting[] = {
    239	{ 0x0103, 0x01 },
    240	{ 0x303b, 0x02 },
    241};
    242
    243static const struct reg_value ov7251_setting_vga_30fps[] = {
    244	{ 0x3005, 0x00 },
    245	{ 0x3012, 0xc0 },
    246	{ 0x3013, 0xd2 },
    247	{ 0x3014, 0x04 },
    248	{ 0x3016, 0xf0 },
    249	{ 0x3017, 0xf0 },
    250	{ 0x3018, 0xf0 },
    251	{ 0x301a, 0xf0 },
    252	{ 0x301b, 0xf0 },
    253	{ 0x301c, 0xf0 },
    254	{ 0x3023, 0x05 },
    255	{ 0x3037, 0xf0 },
    256	{ 0x3106, 0xda },
    257	{ 0x3503, 0x07 },
    258	{ 0x3509, 0x10 },
    259	{ 0x3600, 0x1c },
    260	{ 0x3602, 0x62 },
    261	{ 0x3620, 0xb7 },
    262	{ 0x3622, 0x04 },
    263	{ 0x3626, 0x21 },
    264	{ 0x3627, 0x30 },
    265	{ 0x3630, 0x44 },
    266	{ 0x3631, 0x35 },
    267	{ 0x3634, 0x60 },
    268	{ 0x3636, 0x00 },
    269	{ 0x3662, 0x01 },
    270	{ 0x3663, 0x70 },
    271	{ 0x3664, 0x50 },
    272	{ 0x3666, 0x0a },
    273	{ 0x3669, 0x1a },
    274	{ 0x366a, 0x00 },
    275	{ 0x366b, 0x50 },
    276	{ 0x3673, 0x01 },
    277	{ 0x3674, 0xff },
    278	{ 0x3675, 0x03 },
    279	{ 0x3705, 0xc1 },
    280	{ 0x3709, 0x40 },
    281	{ 0x373c, 0x08 },
    282	{ 0x3742, 0x00 },
    283	{ 0x3757, 0xb3 },
    284	{ 0x3788, 0x00 },
    285	{ 0x37a8, 0x01 },
    286	{ 0x37a9, 0xc0 },
    287	{ 0x3800, 0x00 },
    288	{ 0x3801, 0x04 },
    289	{ 0x3802, 0x00 },
    290	{ 0x3803, 0x04 },
    291	{ 0x3804, 0x02 },
    292	{ 0x3805, 0x8b },
    293	{ 0x3806, 0x01 },
    294	{ 0x3807, 0xeb },
    295	{ 0x3808, 0x02 }, /* width high */
    296	{ 0x3809, 0x80 }, /* width low */
    297	{ 0x380a, 0x01 }, /* height high */
    298	{ 0x380b, 0xe0 }, /* height low */
    299	{ 0x380c, 0x03 }, /* total horiz timing high */
    300	{ 0x380d, 0xa0 }, /* total horiz timing low */
    301	{ 0x380e, 0x06 }, /* total vertical timing high */
    302	{ 0x380f, 0xbc }, /* total vertical timing low */
    303	{ 0x3810, 0x00 },
    304	{ 0x3811, 0x04 },
    305	{ 0x3812, 0x00 },
    306	{ 0x3813, 0x05 },
    307	{ 0x3814, 0x11 },
    308	{ 0x3815, 0x11 },
    309	{ 0x3820, 0x40 },
    310	{ 0x3821, 0x00 },
    311	{ 0x382f, 0x0e },
    312	{ 0x3832, 0x00 },
    313	{ 0x3833, 0x05 },
    314	{ 0x3834, 0x00 },
    315	{ 0x3835, 0x0c },
    316	{ 0x3837, 0x00 },
    317	{ 0x3b80, 0x00 },
    318	{ 0x3b81, 0xa5 },
    319	{ 0x3b82, 0x10 },
    320	{ 0x3b83, 0x00 },
    321	{ 0x3b84, 0x08 },
    322	{ 0x3b85, 0x00 },
    323	{ 0x3b86, 0x01 },
    324	{ 0x3b87, 0x00 },
    325	{ 0x3b88, 0x00 },
    326	{ 0x3b89, 0x00 },
    327	{ 0x3b8a, 0x00 },
    328	{ 0x3b8b, 0x05 },
    329	{ 0x3b8c, 0x00 },
    330	{ 0x3b8d, 0x00 },
    331	{ 0x3b8e, 0x00 },
    332	{ 0x3b8f, 0x1a },
    333	{ 0x3b94, 0x05 },
    334	{ 0x3b95, 0xf2 },
    335	{ 0x3b96, 0x40 },
    336	{ 0x3c00, 0x89 },
    337	{ 0x3c01, 0x63 },
    338	{ 0x3c02, 0x01 },
    339	{ 0x3c03, 0x00 },
    340	{ 0x3c04, 0x00 },
    341	{ 0x3c05, 0x03 },
    342	{ 0x3c06, 0x00 },
    343	{ 0x3c07, 0x06 },
    344	{ 0x3c0c, 0x01 },
    345	{ 0x3c0d, 0xd0 },
    346	{ 0x3c0e, 0x02 },
    347	{ 0x3c0f, 0x0a },
    348	{ 0x4001, 0x42 },
    349	{ 0x4004, 0x04 },
    350	{ 0x4005, 0x00 },
    351	{ 0x404e, 0x01 },
    352	{ 0x4300, 0xff },
    353	{ 0x4301, 0x00 },
    354	{ 0x4315, 0x00 },
    355	{ 0x4501, 0x48 },
    356	{ 0x4600, 0x00 },
    357	{ 0x4601, 0x4e },
    358	{ 0x4801, 0x0f },
    359	{ 0x4806, 0x0f },
    360	{ 0x4819, 0xaa },
    361	{ 0x4823, 0x3e },
    362	{ 0x4837, 0x19 },
    363	{ 0x4a0d, 0x00 },
    364	{ 0x4a47, 0x7f },
    365	{ 0x4a49, 0xf0 },
    366	{ 0x4a4b, 0x30 },
    367	{ 0x5000, 0x85 },
    368	{ 0x5001, 0x80 },
    369};
    370
    371static const struct reg_value ov7251_setting_vga_60fps[] = {
    372	{ 0x3005, 0x00 },
    373	{ 0x3012, 0xc0 },
    374	{ 0x3013, 0xd2 },
    375	{ 0x3014, 0x04 },
    376	{ 0x3016, 0x10 },
    377	{ 0x3017, 0x00 },
    378	{ 0x3018, 0x00 },
    379	{ 0x301a, 0x00 },
    380	{ 0x301b, 0x00 },
    381	{ 0x301c, 0x00 },
    382	{ 0x3023, 0x05 },
    383	{ 0x3037, 0xf0 },
    384	{ 0x3106, 0xda },
    385	{ 0x3503, 0x07 },
    386	{ 0x3509, 0x10 },
    387	{ 0x3600, 0x1c },
    388	{ 0x3602, 0x62 },
    389	{ 0x3620, 0xb7 },
    390	{ 0x3622, 0x04 },
    391	{ 0x3626, 0x21 },
    392	{ 0x3627, 0x30 },
    393	{ 0x3630, 0x44 },
    394	{ 0x3631, 0x35 },
    395	{ 0x3634, 0x60 },
    396	{ 0x3636, 0x00 },
    397	{ 0x3662, 0x01 },
    398	{ 0x3663, 0x70 },
    399	{ 0x3664, 0x50 },
    400	{ 0x3666, 0x0a },
    401	{ 0x3669, 0x1a },
    402	{ 0x366a, 0x00 },
    403	{ 0x366b, 0x50 },
    404	{ 0x3673, 0x01 },
    405	{ 0x3674, 0xff },
    406	{ 0x3675, 0x03 },
    407	{ 0x3705, 0xc1 },
    408	{ 0x3709, 0x40 },
    409	{ 0x373c, 0x08 },
    410	{ 0x3742, 0x00 },
    411	{ 0x3757, 0xb3 },
    412	{ 0x3788, 0x00 },
    413	{ 0x37a8, 0x01 },
    414	{ 0x37a9, 0xc0 },
    415	{ 0x3800, 0x00 },
    416	{ 0x3801, 0x04 },
    417	{ 0x3802, 0x00 },
    418	{ 0x3803, 0x04 },
    419	{ 0x3804, 0x02 },
    420	{ 0x3805, 0x8b },
    421	{ 0x3806, 0x01 },
    422	{ 0x3807, 0xeb },
    423	{ 0x3808, 0x02 }, /* width high */
    424	{ 0x3809, 0x80 }, /* width low */
    425	{ 0x380a, 0x01 }, /* height high */
    426	{ 0x380b, 0xe0 }, /* height low */
    427	{ 0x380c, 0x03 }, /* total horiz timing high */
    428	{ 0x380d, 0xa0 }, /* total horiz timing low */
    429	{ 0x380e, 0x03 }, /* total vertical timing high */
    430	{ 0x380f, 0x5c }, /* total vertical timing low */
    431	{ 0x3810, 0x00 },
    432	{ 0x3811, 0x04 },
    433	{ 0x3812, 0x00 },
    434	{ 0x3813, 0x05 },
    435	{ 0x3814, 0x11 },
    436	{ 0x3815, 0x11 },
    437	{ 0x3820, 0x40 },
    438	{ 0x3821, 0x00 },
    439	{ 0x382f, 0x0e },
    440	{ 0x3832, 0x00 },
    441	{ 0x3833, 0x05 },
    442	{ 0x3834, 0x00 },
    443	{ 0x3835, 0x0c },
    444	{ 0x3837, 0x00 },
    445	{ 0x3b80, 0x00 },
    446	{ 0x3b81, 0xa5 },
    447	{ 0x3b82, 0x10 },
    448	{ 0x3b83, 0x00 },
    449	{ 0x3b84, 0x08 },
    450	{ 0x3b85, 0x00 },
    451	{ 0x3b86, 0x01 },
    452	{ 0x3b87, 0x00 },
    453	{ 0x3b88, 0x00 },
    454	{ 0x3b89, 0x00 },
    455	{ 0x3b8a, 0x00 },
    456	{ 0x3b8b, 0x05 },
    457	{ 0x3b8c, 0x00 },
    458	{ 0x3b8d, 0x00 },
    459	{ 0x3b8e, 0x00 },
    460	{ 0x3b8f, 0x1a },
    461	{ 0x3b94, 0x05 },
    462	{ 0x3b95, 0xf2 },
    463	{ 0x3b96, 0x40 },
    464	{ 0x3c00, 0x89 },
    465	{ 0x3c01, 0x63 },
    466	{ 0x3c02, 0x01 },
    467	{ 0x3c03, 0x00 },
    468	{ 0x3c04, 0x00 },
    469	{ 0x3c05, 0x03 },
    470	{ 0x3c06, 0x00 },
    471	{ 0x3c07, 0x06 },
    472	{ 0x3c0c, 0x01 },
    473	{ 0x3c0d, 0xd0 },
    474	{ 0x3c0e, 0x02 },
    475	{ 0x3c0f, 0x0a },
    476	{ 0x4001, 0x42 },
    477	{ 0x4004, 0x04 },
    478	{ 0x4005, 0x00 },
    479	{ 0x404e, 0x01 },
    480	{ 0x4300, 0xff },
    481	{ 0x4301, 0x00 },
    482	{ 0x4315, 0x00 },
    483	{ 0x4501, 0x48 },
    484	{ 0x4600, 0x00 },
    485	{ 0x4601, 0x4e },
    486	{ 0x4801, 0x0f },
    487	{ 0x4806, 0x0f },
    488	{ 0x4819, 0xaa },
    489	{ 0x4823, 0x3e },
    490	{ 0x4837, 0x19 },
    491	{ 0x4a0d, 0x00 },
    492	{ 0x4a47, 0x7f },
    493	{ 0x4a49, 0xf0 },
    494	{ 0x4a4b, 0x30 },
    495	{ 0x5000, 0x85 },
    496	{ 0x5001, 0x80 },
    497};
    498
    499static const struct reg_value ov7251_setting_vga_90fps[] = {
    500	{ 0x3005, 0x00 },
    501	{ 0x3012, 0xc0 },
    502	{ 0x3013, 0xd2 },
    503	{ 0x3014, 0x04 },
    504	{ 0x3016, 0x10 },
    505	{ 0x3017, 0x00 },
    506	{ 0x3018, 0x00 },
    507	{ 0x301a, 0x00 },
    508	{ 0x301b, 0x00 },
    509	{ 0x301c, 0x00 },
    510	{ 0x3023, 0x05 },
    511	{ 0x3037, 0xf0 },
    512	{ 0x3106, 0xda },
    513	{ 0x3503, 0x07 },
    514	{ 0x3509, 0x10 },
    515	{ 0x3600, 0x1c },
    516	{ 0x3602, 0x62 },
    517	{ 0x3620, 0xb7 },
    518	{ 0x3622, 0x04 },
    519	{ 0x3626, 0x21 },
    520	{ 0x3627, 0x30 },
    521	{ 0x3630, 0x44 },
    522	{ 0x3631, 0x35 },
    523	{ 0x3634, 0x60 },
    524	{ 0x3636, 0x00 },
    525	{ 0x3662, 0x01 },
    526	{ 0x3663, 0x70 },
    527	{ 0x3664, 0x50 },
    528	{ 0x3666, 0x0a },
    529	{ 0x3669, 0x1a },
    530	{ 0x366a, 0x00 },
    531	{ 0x366b, 0x50 },
    532	{ 0x3673, 0x01 },
    533	{ 0x3674, 0xff },
    534	{ 0x3675, 0x03 },
    535	{ 0x3705, 0xc1 },
    536	{ 0x3709, 0x40 },
    537	{ 0x373c, 0x08 },
    538	{ 0x3742, 0x00 },
    539	{ 0x3757, 0xb3 },
    540	{ 0x3788, 0x00 },
    541	{ 0x37a8, 0x01 },
    542	{ 0x37a9, 0xc0 },
    543	{ 0x3800, 0x00 },
    544	{ 0x3801, 0x04 },
    545	{ 0x3802, 0x00 },
    546	{ 0x3803, 0x04 },
    547	{ 0x3804, 0x02 },
    548	{ 0x3805, 0x8b },
    549	{ 0x3806, 0x01 },
    550	{ 0x3807, 0xeb },
    551	{ 0x3808, 0x02 }, /* width high */
    552	{ 0x3809, 0x80 }, /* width low */
    553	{ 0x380a, 0x01 }, /* height high */
    554	{ 0x380b, 0xe0 }, /* height low */
    555	{ 0x380c, 0x03 }, /* total horiz timing high */
    556	{ 0x380d, 0xa0 }, /* total horiz timing low */
    557	{ 0x380e, 0x02 }, /* total vertical timing high */
    558	{ 0x380f, 0x3c }, /* total vertical timing low */
    559	{ 0x3810, 0x00 },
    560	{ 0x3811, 0x04 },
    561	{ 0x3812, 0x00 },
    562	{ 0x3813, 0x05 },
    563	{ 0x3814, 0x11 },
    564	{ 0x3815, 0x11 },
    565	{ 0x3820, 0x40 },
    566	{ 0x3821, 0x00 },
    567	{ 0x382f, 0x0e },
    568	{ 0x3832, 0x00 },
    569	{ 0x3833, 0x05 },
    570	{ 0x3834, 0x00 },
    571	{ 0x3835, 0x0c },
    572	{ 0x3837, 0x00 },
    573	{ 0x3b80, 0x00 },
    574	{ 0x3b81, 0xa5 },
    575	{ 0x3b82, 0x10 },
    576	{ 0x3b83, 0x00 },
    577	{ 0x3b84, 0x08 },
    578	{ 0x3b85, 0x00 },
    579	{ 0x3b86, 0x01 },
    580	{ 0x3b87, 0x00 },
    581	{ 0x3b88, 0x00 },
    582	{ 0x3b89, 0x00 },
    583	{ 0x3b8a, 0x00 },
    584	{ 0x3b8b, 0x05 },
    585	{ 0x3b8c, 0x00 },
    586	{ 0x3b8d, 0x00 },
    587	{ 0x3b8e, 0x00 },
    588	{ 0x3b8f, 0x1a },
    589	{ 0x3b94, 0x05 },
    590	{ 0x3b95, 0xf2 },
    591	{ 0x3b96, 0x40 },
    592	{ 0x3c00, 0x89 },
    593	{ 0x3c01, 0x63 },
    594	{ 0x3c02, 0x01 },
    595	{ 0x3c03, 0x00 },
    596	{ 0x3c04, 0x00 },
    597	{ 0x3c05, 0x03 },
    598	{ 0x3c06, 0x00 },
    599	{ 0x3c07, 0x06 },
    600	{ 0x3c0c, 0x01 },
    601	{ 0x3c0d, 0xd0 },
    602	{ 0x3c0e, 0x02 },
    603	{ 0x3c0f, 0x0a },
    604	{ 0x4001, 0x42 },
    605	{ 0x4004, 0x04 },
    606	{ 0x4005, 0x00 },
    607	{ 0x404e, 0x01 },
    608	{ 0x4300, 0xff },
    609	{ 0x4301, 0x00 },
    610	{ 0x4315, 0x00 },
    611	{ 0x4501, 0x48 },
    612	{ 0x4600, 0x00 },
    613	{ 0x4601, 0x4e },
    614	{ 0x4801, 0x0f },
    615	{ 0x4806, 0x0f },
    616	{ 0x4819, 0xaa },
    617	{ 0x4823, 0x3e },
    618	{ 0x4837, 0x19 },
    619	{ 0x4a0d, 0x00 },
    620	{ 0x4a47, 0x7f },
    621	{ 0x4a49, 0xf0 },
    622	{ 0x4a4b, 0x30 },
    623	{ 0x5000, 0x85 },
    624	{ 0x5001, 0x80 },
    625};
    626
    627static const unsigned long supported_xclk_rates[] = {
    628	[OV7251_19_2_MHZ] = 19200000,
    629	[OV7251_24_MHZ] = 24000000,
    630};
    631
    632static const s64 link_freq[] = {
    633	[OV7251_LINK_FREQ_240_MHZ] = 240000000,
    634	[OV7251_LINK_FREQ_319_2_MHZ] = 319200000,
    635};
    636
    637static const s64 pixel_rates[] = {
    638	[OV7251_LINK_FREQ_240_MHZ] = 48000000,
    639	[OV7251_LINK_FREQ_319_2_MHZ] = 63840000,
    640};
    641
    642static const struct ov7251_mode_info ov7251_mode_info_data[] = {
    643	{
    644		.width = 640,
    645		.height = 480,
    646		.vts = 1724,
    647		.data = ov7251_setting_vga_30fps,
    648		.data_size = ARRAY_SIZE(ov7251_setting_vga_30fps),
    649		.exposure_max = 1704,
    650		.exposure_def = 504,
    651		.timeperframe = {
    652			.numerator = 100,
    653			.denominator = 3000
    654		}
    655	},
    656	{
    657		.width = 640,
    658		.height = 480,
    659		.vts = 860,
    660		.data = ov7251_setting_vga_60fps,
    661		.data_size = ARRAY_SIZE(ov7251_setting_vga_60fps),
    662		.exposure_max = 840,
    663		.exposure_def = 504,
    664		.timeperframe = {
    665			.numerator = 100,
    666			.denominator = 6014
    667		}
    668	},
    669	{
    670		.width = 640,
    671		.height = 480,
    672		.vts = 572,
    673		.data = ov7251_setting_vga_90fps,
    674		.data_size = ARRAY_SIZE(ov7251_setting_vga_90fps),
    675		.exposure_max = 552,
    676		.exposure_def = 504,
    677		.timeperframe = {
    678			.numerator = 100,
    679			.denominator = 9043
    680		}
    681	},
    682};
    683
    684static int ov7251_regulators_enable(struct ov7251 *ov7251)
    685{
    686	int ret;
    687
    688	/* OV7251 power up sequence requires core regulator
    689	 * to be enabled not earlier than io regulator
    690	 */
    691
    692	ret = regulator_enable(ov7251->io_regulator);
    693	if (ret < 0) {
    694		dev_err(ov7251->dev, "set io voltage failed\n");
    695		return ret;
    696	}
    697
    698	ret = regulator_enable(ov7251->analog_regulator);
    699	if (ret) {
    700		dev_err(ov7251->dev, "set analog voltage failed\n");
    701		goto err_disable_io;
    702	}
    703
    704	ret = regulator_enable(ov7251->core_regulator);
    705	if (ret) {
    706		dev_err(ov7251->dev, "set core voltage failed\n");
    707		goto err_disable_analog;
    708	}
    709
    710	return 0;
    711
    712err_disable_analog:
    713	regulator_disable(ov7251->analog_regulator);
    714
    715err_disable_io:
    716	regulator_disable(ov7251->io_regulator);
    717
    718	return ret;
    719}
    720
    721static void ov7251_regulators_disable(struct ov7251 *ov7251)
    722{
    723	int ret;
    724
    725	ret = regulator_disable(ov7251->core_regulator);
    726	if (ret < 0)
    727		dev_err(ov7251->dev, "core regulator disable failed\n");
    728
    729	ret = regulator_disable(ov7251->analog_regulator);
    730	if (ret < 0)
    731		dev_err(ov7251->dev, "analog regulator disable failed\n");
    732
    733	ret = regulator_disable(ov7251->io_regulator);
    734	if (ret < 0)
    735		dev_err(ov7251->dev, "io regulator disable failed\n");
    736}
    737
    738static int ov7251_write_reg(struct ov7251 *ov7251, u16 reg, u8 val)
    739{
    740	u8 regbuf[3];
    741	int ret;
    742
    743	regbuf[0] = reg >> 8;
    744	regbuf[1] = reg & 0xff;
    745	regbuf[2] = val;
    746
    747	ret = i2c_master_send(ov7251->i2c_client, regbuf, 3);
    748	if (ret < 0) {
    749		dev_err(ov7251->dev, "%s: write reg error %d: reg=%x, val=%x\n",
    750			__func__, ret, reg, val);
    751		return ret;
    752	}
    753
    754	return 0;
    755}
    756
    757static int ov7251_write_seq_regs(struct ov7251 *ov7251, u16 reg, u8 *val,
    758				 u8 num)
    759{
    760	u8 regbuf[5];
    761	u8 nregbuf = sizeof(reg) + num * sizeof(*val);
    762	int ret = 0;
    763
    764	if (nregbuf > sizeof(regbuf))
    765		return -EINVAL;
    766
    767	regbuf[0] = reg >> 8;
    768	regbuf[1] = reg & 0xff;
    769
    770	memcpy(regbuf + 2, val, num);
    771
    772	ret = i2c_master_send(ov7251->i2c_client, regbuf, nregbuf);
    773	if (ret < 0) {
    774		dev_err(ov7251->dev,
    775			"%s: write seq regs error %d: first reg=%x\n",
    776			__func__, ret, reg);
    777		return ret;
    778	}
    779
    780	return 0;
    781}
    782
    783static int ov7251_read_reg(struct ov7251 *ov7251, u16 reg, u8 *val)
    784{
    785	u8 regbuf[2];
    786	int ret;
    787
    788	regbuf[0] = reg >> 8;
    789	regbuf[1] = reg & 0xff;
    790
    791	ret = i2c_master_send(ov7251->i2c_client, regbuf, 2);
    792	if (ret < 0) {
    793		dev_err(ov7251->dev, "%s: write reg error %d: reg=%x\n",
    794			__func__, ret, reg);
    795		return ret;
    796	}
    797
    798	ret = i2c_master_recv(ov7251->i2c_client, val, 1);
    799	if (ret < 0) {
    800		dev_err(ov7251->dev, "%s: read reg error %d: reg=%x\n",
    801			__func__, ret, reg);
    802		return ret;
    803	}
    804
    805	return 0;
    806}
    807
    808static int ov7251_pll_configure(struct ov7251 *ov7251)
    809{
    810	const struct ov7251_pll_cfgs *configs;
    811	int ret;
    812
    813	configs = ov7251->pll_cfgs;
    814
    815	ret = ov7251_write_reg(ov7251, OV7251_PLL1_PRE_DIV_REG,
    816			       configs->pll1[ov7251->link_freq_idx]->pre_div);
    817	if (ret < 0)
    818		return ret;
    819
    820	ret = ov7251_write_reg(ov7251, OV7251_PLL1_MULT_REG,
    821			       configs->pll1[ov7251->link_freq_idx]->mult);
    822	if (ret < 0)
    823		return ret;
    824	ret = ov7251_write_reg(ov7251, OV7251_PLL1_DIVIDER_REG,
    825			       configs->pll1[ov7251->link_freq_idx]->div);
    826	if (ret < 0)
    827		return ret;
    828
    829	ret = ov7251_write_reg(ov7251, OV7251_PLL1_PIX_DIV_REG,
    830			       configs->pll1[ov7251->link_freq_idx]->pix_div);
    831	if (ret < 0)
    832		return ret;
    833
    834	ret = ov7251_write_reg(ov7251, OV7251_PLL1_MIPI_DIV_REG,
    835			       configs->pll1[ov7251->link_freq_idx]->mipi_div);
    836	if (ret < 0)
    837		return ret;
    838
    839	ret = ov7251_write_reg(ov7251, OV7251_PLL2_PRE_DIV_REG,
    840			       configs->pll2->pre_div);
    841	if (ret < 0)
    842		return ret;
    843
    844	ret = ov7251_write_reg(ov7251, OV7251_PLL2_MULT_REG,
    845			       configs->pll2->mult);
    846	if (ret < 0)
    847		return ret;
    848
    849	ret = ov7251_write_reg(ov7251, OV7251_PLL2_DIVIDER_REG,
    850			       configs->pll2->div);
    851	if (ret < 0)
    852		return ret;
    853
    854	ret = ov7251_write_reg(ov7251, OV7251_PLL2_SYS_DIV_REG,
    855			       configs->pll2->sys_div);
    856	if (ret < 0)
    857		return ret;
    858
    859	ret = ov7251_write_reg(ov7251, OV7251_PLL2_ADC_DIV_REG,
    860			       configs->pll2->adc_div);
    861
    862	return ret;
    863}
    864
    865static int ov7251_set_exposure(struct ov7251 *ov7251, s32 exposure)
    866{
    867	u16 reg;
    868	u8 val[3];
    869
    870	reg = OV7251_AEC_EXPO_0;
    871	val[0] = (exposure & 0xf000) >> 12; /* goes to OV7251_AEC_EXPO_0 */
    872	val[1] = (exposure & 0x0ff0) >> 4;  /* goes to OV7251_AEC_EXPO_1 */
    873	val[2] = (exposure & 0x000f) << 4;  /* goes to OV7251_AEC_EXPO_2 */
    874
    875	return ov7251_write_seq_regs(ov7251, reg, val, 3);
    876}
    877
    878static int ov7251_set_gain(struct ov7251 *ov7251, s32 gain)
    879{
    880	u16 reg;
    881	u8 val[2];
    882
    883	reg = OV7251_AEC_AGC_ADJ_0;
    884	val[0] = (gain & 0x0300) >> 8; /* goes to OV7251_AEC_AGC_ADJ_0 */
    885	val[1] = gain & 0xff;          /* goes to OV7251_AEC_AGC_ADJ_1 */
    886
    887	return ov7251_write_seq_regs(ov7251, reg, val, 2);
    888}
    889
    890static int ov7251_set_register_array(struct ov7251 *ov7251,
    891				     const struct reg_value *settings,
    892				     unsigned int num_settings)
    893{
    894	unsigned int i;
    895	int ret;
    896
    897	for (i = 0; i < num_settings; ++i, ++settings) {
    898		ret = ov7251_write_reg(ov7251, settings->reg, settings->val);
    899		if (ret < 0)
    900			return ret;
    901	}
    902
    903	return 0;
    904}
    905
    906static int ov7251_set_power_on(struct device *dev)
    907{
    908	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
    909	struct v4l2_subdev *sd = i2c_get_clientdata(client);
    910	struct ov7251 *ov7251 = to_ov7251(sd);
    911	int ret;
    912	u32 wait_us;
    913
    914	ret = ov7251_regulators_enable(ov7251);
    915	if (ret < 0)
    916		return ret;
    917
    918	ret = clk_prepare_enable(ov7251->xclk);
    919	if (ret < 0) {
    920		dev_err(ov7251->dev, "clk prepare enable failed\n");
    921		ov7251_regulators_disable(ov7251);
    922		return ret;
    923	}
    924
    925	gpiod_set_value_cansleep(ov7251->enable_gpio, 1);
    926
    927	/* wait at least 65536 external clock cycles */
    928	wait_us = DIV_ROUND_UP(65536 * 1000,
    929			       DIV_ROUND_UP(ov7251->xclk_freq, 1000));
    930	usleep_range(wait_us, wait_us + 1000);
    931
    932	ret = ov7251_set_register_array(ov7251,
    933					ov7251_global_init_setting,
    934					ARRAY_SIZE(ov7251_global_init_setting));
    935	if (ret < 0) {
    936		dev_err(ov7251->dev, "error during global init\n");
    937		ov7251_regulators_disable(ov7251);
    938		return ret;
    939	}
    940
    941	return ret;
    942}
    943
    944static int ov7251_set_power_off(struct device *dev)
    945{
    946	struct i2c_client *client = container_of(dev, struct i2c_client, dev);
    947	struct v4l2_subdev *sd = i2c_get_clientdata(client);
    948	struct ov7251 *ov7251 = to_ov7251(sd);
    949
    950	clk_disable_unprepare(ov7251->xclk);
    951	gpiod_set_value_cansleep(ov7251->enable_gpio, 0);
    952	ov7251_regulators_disable(ov7251);
    953
    954	return 0;
    955}
    956
    957static int ov7251_set_hflip(struct ov7251 *ov7251, s32 value)
    958{
    959	u8 val = ov7251->timing_format2;
    960	int ret;
    961
    962	if (value)
    963		val |= OV7251_TIMING_FORMAT2_MIRROR;
    964	else
    965		val &= ~OV7251_TIMING_FORMAT2_MIRROR;
    966
    967	ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT2, val);
    968	if (!ret)
    969		ov7251->timing_format2 = val;
    970
    971	return ret;
    972}
    973
    974static int ov7251_set_vflip(struct ov7251 *ov7251, s32 value)
    975{
    976	u8 val = ov7251->timing_format1;
    977	int ret;
    978
    979	if (value)
    980		val |= OV7251_TIMING_FORMAT1_VFLIP;
    981	else
    982		val &= ~OV7251_TIMING_FORMAT1_VFLIP;
    983
    984	ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT1, val);
    985	if (!ret)
    986		ov7251->timing_format1 = val;
    987
    988	return ret;
    989}
    990
    991static int ov7251_set_test_pattern(struct ov7251 *ov7251, s32 value)
    992{
    993	u8 val = ov7251->pre_isp_00;
    994	int ret;
    995
    996	if (value)
    997		val |= OV7251_PRE_ISP_00_TEST_PATTERN;
    998	else
    999		val &= ~OV7251_PRE_ISP_00_TEST_PATTERN;
   1000
   1001	ret = ov7251_write_reg(ov7251, OV7251_PRE_ISP_00, val);
   1002	if (!ret)
   1003		ov7251->pre_isp_00 = val;
   1004
   1005	return ret;
   1006}
   1007
   1008static const char * const ov7251_test_pattern_menu[] = {
   1009	"Disabled",
   1010	"Vertical Pattern Bars",
   1011};
   1012
   1013static int ov7251_vts_configure(struct ov7251 *ov7251, s32 vblank)
   1014{
   1015	u8 vts[2];
   1016
   1017	vts[0] = ((ov7251->current_mode->height + vblank) & 0xff00) >> 8;
   1018	vts[1] = ((ov7251->current_mode->height + vblank) & 0x00ff);
   1019
   1020	return ov7251_write_seq_regs(ov7251, OV7251_TIMING_VTS_REG, vts, 2);
   1021}
   1022
   1023static int ov7251_s_ctrl(struct v4l2_ctrl *ctrl)
   1024{
   1025	struct ov7251 *ov7251 = container_of(ctrl->handler,
   1026					     struct ov7251, ctrls);
   1027	int ret;
   1028
   1029	/* If VBLANK is altered we need to update exposure to compensate */
   1030	if (ctrl->id == V4L2_CID_VBLANK) {
   1031		int exposure_max;
   1032
   1033		exposure_max = ov7251->current_mode->height + ctrl->val -
   1034			       OV7251_INTEGRATION_MARGIN;
   1035		__v4l2_ctrl_modify_range(ov7251->exposure,
   1036					 ov7251->exposure->minimum,
   1037					 exposure_max,
   1038					 ov7251->exposure->step,
   1039					 min(ov7251->exposure->val,
   1040					     exposure_max));
   1041	}
   1042
   1043	/* v4l2_ctrl_lock() locks our mutex */
   1044
   1045	if (!pm_runtime_get_if_in_use(ov7251->dev))
   1046		return 0;
   1047
   1048	switch (ctrl->id) {
   1049	case V4L2_CID_EXPOSURE:
   1050		ret = ov7251_set_exposure(ov7251, ctrl->val);
   1051		break;
   1052	case V4L2_CID_GAIN:
   1053		ret = ov7251_set_gain(ov7251, ctrl->val);
   1054		break;
   1055	case V4L2_CID_TEST_PATTERN:
   1056		ret = ov7251_set_test_pattern(ov7251, ctrl->val);
   1057		break;
   1058	case V4L2_CID_HFLIP:
   1059		ret = ov7251_set_hflip(ov7251, ctrl->val);
   1060		break;
   1061	case V4L2_CID_VFLIP:
   1062		ret = ov7251_set_vflip(ov7251, ctrl->val);
   1063		break;
   1064	case V4L2_CID_VBLANK:
   1065		ret = ov7251_vts_configure(ov7251, ctrl->val);
   1066		break;
   1067	default:
   1068		ret = -EINVAL;
   1069		break;
   1070	}
   1071
   1072	pm_runtime_put(ov7251->dev);
   1073
   1074	return ret;
   1075}
   1076
   1077static const struct v4l2_ctrl_ops ov7251_ctrl_ops = {
   1078	.s_ctrl = ov7251_s_ctrl,
   1079};
   1080
   1081static int ov7251_enum_mbus_code(struct v4l2_subdev *sd,
   1082				 struct v4l2_subdev_state *sd_state,
   1083				 struct v4l2_subdev_mbus_code_enum *code)
   1084{
   1085	if (code->index > 0)
   1086		return -EINVAL;
   1087
   1088	code->code = MEDIA_BUS_FMT_Y10_1X10;
   1089
   1090	return 0;
   1091}
   1092
   1093static int ov7251_enum_frame_size(struct v4l2_subdev *subdev,
   1094				  struct v4l2_subdev_state *sd_state,
   1095				  struct v4l2_subdev_frame_size_enum *fse)
   1096{
   1097	if (fse->code != MEDIA_BUS_FMT_Y10_1X10)
   1098		return -EINVAL;
   1099
   1100	if (fse->index >= ARRAY_SIZE(ov7251_mode_info_data))
   1101		return -EINVAL;
   1102
   1103	fse->min_width = ov7251_mode_info_data[fse->index].width;
   1104	fse->max_width = ov7251_mode_info_data[fse->index].width;
   1105	fse->min_height = ov7251_mode_info_data[fse->index].height;
   1106	fse->max_height = ov7251_mode_info_data[fse->index].height;
   1107
   1108	return 0;
   1109}
   1110
   1111static int ov7251_enum_frame_ival(struct v4l2_subdev *subdev,
   1112				  struct v4l2_subdev_state *sd_state,
   1113				  struct v4l2_subdev_frame_interval_enum *fie)
   1114{
   1115	unsigned int index = fie->index;
   1116	unsigned int i;
   1117
   1118	for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) {
   1119		if (fie->width != ov7251_mode_info_data[i].width ||
   1120		    fie->height != ov7251_mode_info_data[i].height)
   1121			continue;
   1122
   1123		if (index-- == 0) {
   1124			fie->interval = ov7251_mode_info_data[i].timeperframe;
   1125			return 0;
   1126		}
   1127	}
   1128
   1129	return -EINVAL;
   1130}
   1131
   1132static struct v4l2_mbus_framefmt *
   1133__ov7251_get_pad_format(struct ov7251 *ov7251,
   1134			struct v4l2_subdev_state *sd_state,
   1135			unsigned int pad,
   1136			enum v4l2_subdev_format_whence which)
   1137{
   1138	switch (which) {
   1139	case V4L2_SUBDEV_FORMAT_TRY:
   1140		return v4l2_subdev_get_try_format(&ov7251->sd, sd_state, pad);
   1141	case V4L2_SUBDEV_FORMAT_ACTIVE:
   1142		return &ov7251->fmt;
   1143	default:
   1144		return NULL;
   1145	}
   1146}
   1147
   1148static int ov7251_get_format(struct v4l2_subdev *sd,
   1149			     struct v4l2_subdev_state *sd_state,
   1150			     struct v4l2_subdev_format *format)
   1151{
   1152	struct ov7251 *ov7251 = to_ov7251(sd);
   1153
   1154	mutex_lock(&ov7251->lock);
   1155	format->format = *__ov7251_get_pad_format(ov7251, sd_state,
   1156						  format->pad,
   1157						  format->which);
   1158	mutex_unlock(&ov7251->lock);
   1159
   1160	return 0;
   1161}
   1162
   1163static struct v4l2_rect *
   1164__ov7251_get_pad_crop(struct ov7251 *ov7251,
   1165		      struct v4l2_subdev_state *sd_state,
   1166		      unsigned int pad, enum v4l2_subdev_format_whence which)
   1167{
   1168	switch (which) {
   1169	case V4L2_SUBDEV_FORMAT_TRY:
   1170		return v4l2_subdev_get_try_crop(&ov7251->sd, sd_state, pad);
   1171	case V4L2_SUBDEV_FORMAT_ACTIVE:
   1172		return &ov7251->crop;
   1173	default:
   1174		return NULL;
   1175	}
   1176}
   1177
   1178static inline u32 avg_fps(const struct v4l2_fract *t)
   1179{
   1180	return (t->denominator + (t->numerator >> 1)) / t->numerator;
   1181}
   1182
   1183static const struct ov7251_mode_info *
   1184ov7251_find_mode_by_ival(struct ov7251 *ov7251, struct v4l2_fract *timeperframe)
   1185{
   1186	const struct ov7251_mode_info *mode = ov7251->current_mode;
   1187	unsigned int fps_req = avg_fps(timeperframe);
   1188	unsigned int max_dist_match = (unsigned int) -1;
   1189	unsigned int i, n = 0;
   1190
   1191	for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) {
   1192		unsigned int dist;
   1193		unsigned int fps_tmp;
   1194
   1195		if (mode->width != ov7251_mode_info_data[i].width ||
   1196		    mode->height != ov7251_mode_info_data[i].height)
   1197			continue;
   1198
   1199		fps_tmp = avg_fps(&ov7251_mode_info_data[i].timeperframe);
   1200
   1201		dist = abs(fps_req - fps_tmp);
   1202
   1203		if (dist < max_dist_match) {
   1204			n = i;
   1205			max_dist_match = dist;
   1206		}
   1207	}
   1208
   1209	return &ov7251_mode_info_data[n];
   1210}
   1211
   1212static int ov7251_set_format(struct v4l2_subdev *sd,
   1213			     struct v4l2_subdev_state *sd_state,
   1214			     struct v4l2_subdev_format *format)
   1215{
   1216	struct ov7251 *ov7251 = to_ov7251(sd);
   1217	struct v4l2_mbus_framefmt *__format;
   1218	int vblank_max, vblank_def;
   1219	struct v4l2_rect *__crop;
   1220	const struct ov7251_mode_info *new_mode;
   1221	int ret = 0;
   1222
   1223	mutex_lock(&ov7251->lock);
   1224
   1225	__crop = __ov7251_get_pad_crop(ov7251, sd_state, format->pad,
   1226				       format->which);
   1227
   1228	new_mode = v4l2_find_nearest_size(ov7251_mode_info_data,
   1229				ARRAY_SIZE(ov7251_mode_info_data),
   1230				width, height,
   1231				format->format.width, format->format.height);
   1232
   1233	__crop->width = new_mode->width;
   1234	__crop->height = new_mode->height;
   1235
   1236	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
   1237		ret = __v4l2_ctrl_modify_range(ov7251->exposure,
   1238					       1, new_mode->exposure_max,
   1239					       1, new_mode->exposure_def);
   1240		if (ret < 0)
   1241			goto exit;
   1242
   1243		ret = __v4l2_ctrl_s_ctrl(ov7251->exposure,
   1244					 new_mode->exposure_def);
   1245		if (ret < 0)
   1246			goto exit;
   1247
   1248		ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16);
   1249		if (ret < 0)
   1250			goto exit;
   1251
   1252		vblank_max = OV7251_TIMING_MAX_VTS - new_mode->height;
   1253		vblank_def = new_mode->vts - new_mode->height;
   1254		ret = __v4l2_ctrl_modify_range(ov7251->vblank,
   1255					       OV7251_TIMING_MIN_VTS,
   1256					       vblank_max, 1, vblank_def);
   1257		if (ret < 0)
   1258			goto exit;
   1259
   1260		ov7251->current_mode = new_mode;
   1261	}
   1262
   1263	__format = __ov7251_get_pad_format(ov7251, sd_state, format->pad,
   1264					   format->which);
   1265	__format->width = __crop->width;
   1266	__format->height = __crop->height;
   1267	__format->code = MEDIA_BUS_FMT_Y10_1X10;
   1268	__format->field = V4L2_FIELD_NONE;
   1269	__format->colorspace = V4L2_COLORSPACE_SRGB;
   1270	__format->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(__format->colorspace);
   1271	__format->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
   1272				__format->colorspace, __format->ycbcr_enc);
   1273	__format->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(__format->colorspace);
   1274
   1275	format->format = *__format;
   1276
   1277exit:
   1278	mutex_unlock(&ov7251->lock);
   1279
   1280	return ret;
   1281}
   1282
   1283static int ov7251_entity_init_cfg(struct v4l2_subdev *subdev,
   1284				  struct v4l2_subdev_state *sd_state)
   1285{
   1286	struct v4l2_subdev_format fmt = {
   1287		.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY
   1288		: V4L2_SUBDEV_FORMAT_ACTIVE,
   1289		.format = {
   1290			.width = 640,
   1291			.height = 480
   1292		}
   1293	};
   1294
   1295	ov7251_set_format(subdev, sd_state, &fmt);
   1296
   1297	return 0;
   1298}
   1299
   1300static int ov7251_get_selection(struct v4l2_subdev *sd,
   1301				struct v4l2_subdev_state *sd_state,
   1302				struct v4l2_subdev_selection *sel)
   1303{
   1304	struct ov7251 *ov7251 = to_ov7251(sd);
   1305
   1306	switch (sel->target) {
   1307	case V4L2_SEL_TGT_CROP_DEFAULT:
   1308	case V4L2_SEL_TGT_CROP:
   1309	mutex_lock(&ov7251->lock);
   1310		sel->r = *__ov7251_get_pad_crop(ov7251, sd_state, sel->pad,
   1311						sel->which);
   1312		mutex_unlock(&ov7251->lock);
   1313		break;
   1314	case V4L2_SEL_TGT_NATIVE_SIZE:
   1315		sel->r.top = 0;
   1316		sel->r.left = 0;
   1317		sel->r.width = OV7251_NATIVE_WIDTH;
   1318		sel->r.height = OV7251_NATIVE_HEIGHT;
   1319		break;
   1320	case V4L2_SEL_TGT_CROP_BOUNDS:
   1321		sel->r.top = OV7251_ACTIVE_START_TOP;
   1322		sel->r.left = OV7251_ACTIVE_START_LEFT;
   1323		sel->r.width = OV7251_ACTIVE_WIDTH;
   1324		sel->r.height = OV7251_ACTIVE_HEIGHT;
   1325		break;
   1326	default:
   1327		return -EINVAL;
   1328	}
   1329
   1330	return 0;
   1331}
   1332
   1333static int ov7251_s_stream(struct v4l2_subdev *subdev, int enable)
   1334{
   1335	struct ov7251 *ov7251 = to_ov7251(subdev);
   1336	int ret;
   1337
   1338	mutex_lock(&ov7251->lock);
   1339
   1340	if (enable) {
   1341		ret = pm_runtime_get_sync(ov7251->dev);
   1342		if (ret < 0)
   1343			goto unlock_out;
   1344
   1345		ret = ov7251_pll_configure(ov7251);
   1346		if (ret) {
   1347			dev_err(ov7251->dev, "error configuring PLLs\n");
   1348			goto err_power_down;
   1349		}
   1350
   1351		ret = ov7251_set_register_array(ov7251,
   1352					ov7251->current_mode->data,
   1353					ov7251->current_mode->data_size);
   1354		if (ret < 0) {
   1355			dev_err(ov7251->dev, "could not set mode %dx%d\n",
   1356				ov7251->current_mode->width,
   1357				ov7251->current_mode->height);
   1358			goto err_power_down;
   1359		}
   1360		ret = __v4l2_ctrl_handler_setup(&ov7251->ctrls);
   1361		if (ret < 0) {
   1362			dev_err(ov7251->dev, "could not sync v4l2 controls\n");
   1363			goto err_power_down;
   1364		}
   1365		ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT,
   1366				       OV7251_SC_MODE_SELECT_STREAMING);
   1367		if (ret)
   1368			goto err_power_down;
   1369	} else {
   1370		ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT,
   1371				       OV7251_SC_MODE_SELECT_SW_STANDBY);
   1372		pm_runtime_put(ov7251->dev);
   1373	}
   1374
   1375unlock_out:
   1376	mutex_unlock(&ov7251->lock);
   1377	return ret;
   1378
   1379err_power_down:
   1380	pm_runtime_put_noidle(ov7251->dev);
   1381	mutex_unlock(&ov7251->lock);
   1382	return ret;
   1383}
   1384
   1385static int ov7251_get_frame_interval(struct v4l2_subdev *subdev,
   1386				     struct v4l2_subdev_frame_interval *fi)
   1387{
   1388	struct ov7251 *ov7251 = to_ov7251(subdev);
   1389
   1390	mutex_lock(&ov7251->lock);
   1391	fi->interval = ov7251->current_mode->timeperframe;
   1392	mutex_unlock(&ov7251->lock);
   1393
   1394	return 0;
   1395}
   1396
   1397static int ov7251_set_frame_interval(struct v4l2_subdev *subdev,
   1398				     struct v4l2_subdev_frame_interval *fi)
   1399{
   1400	struct ov7251 *ov7251 = to_ov7251(subdev);
   1401	const struct ov7251_mode_info *new_mode;
   1402	int ret = 0;
   1403
   1404	mutex_lock(&ov7251->lock);
   1405	new_mode = ov7251_find_mode_by_ival(ov7251, &fi->interval);
   1406
   1407	if (new_mode != ov7251->current_mode) {
   1408		ret = __v4l2_ctrl_modify_range(ov7251->exposure,
   1409					       1, new_mode->exposure_max,
   1410					       1, new_mode->exposure_def);
   1411		if (ret < 0)
   1412			goto exit;
   1413
   1414		ret = __v4l2_ctrl_s_ctrl(ov7251->exposure,
   1415					 new_mode->exposure_def);
   1416		if (ret < 0)
   1417			goto exit;
   1418
   1419		ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16);
   1420		if (ret < 0)
   1421			goto exit;
   1422
   1423		ov7251->current_mode = new_mode;
   1424	}
   1425
   1426	fi->interval = ov7251->current_mode->timeperframe;
   1427
   1428exit:
   1429	mutex_unlock(&ov7251->lock);
   1430
   1431	return ret;
   1432}
   1433
   1434static const struct v4l2_subdev_video_ops ov7251_video_ops = {
   1435	.s_stream = ov7251_s_stream,
   1436	.g_frame_interval = ov7251_get_frame_interval,
   1437	.s_frame_interval = ov7251_set_frame_interval,
   1438};
   1439
   1440static const struct v4l2_subdev_pad_ops ov7251_subdev_pad_ops = {
   1441	.init_cfg = ov7251_entity_init_cfg,
   1442	.enum_mbus_code = ov7251_enum_mbus_code,
   1443	.enum_frame_size = ov7251_enum_frame_size,
   1444	.enum_frame_interval = ov7251_enum_frame_ival,
   1445	.get_fmt = ov7251_get_format,
   1446	.set_fmt = ov7251_set_format,
   1447	.get_selection = ov7251_get_selection,
   1448};
   1449
   1450static const struct v4l2_subdev_ops ov7251_subdev_ops = {
   1451	.video = &ov7251_video_ops,
   1452	.pad = &ov7251_subdev_pad_ops,
   1453};
   1454
   1455static int ov7251_check_hwcfg(struct ov7251 *ov7251)
   1456{
   1457	struct fwnode_handle *fwnode = dev_fwnode(ov7251->dev);
   1458	struct v4l2_fwnode_endpoint bus_cfg = {
   1459		.bus_type = V4L2_MBUS_CSI2_DPHY,
   1460	};
   1461	struct fwnode_handle *endpoint;
   1462	unsigned int i, j;
   1463	int ret;
   1464
   1465	endpoint = fwnode_graph_get_next_endpoint(fwnode, NULL);
   1466	if (!endpoint)
   1467		return -EPROBE_DEFER; /* could be provided by cio2-bridge */
   1468
   1469	ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg);
   1470	fwnode_handle_put(endpoint);
   1471	if (ret)
   1472		return dev_err_probe(ov7251->dev, ret,
   1473				     "parsing endpoint node failed\n");
   1474
   1475	if (!bus_cfg.nr_of_link_frequencies) {
   1476		ret = dev_err_probe(ov7251->dev, -EINVAL,
   1477				    "no link frequencies defined\n");
   1478		goto out_free_bus_cfg;
   1479	}
   1480
   1481	for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) {
   1482		for (j = 0; j < ARRAY_SIZE(link_freq); j++)
   1483			if (bus_cfg.link_frequencies[i] == link_freq[j])
   1484				break;
   1485
   1486		if (j < ARRAY_SIZE(link_freq))
   1487			break;
   1488	}
   1489
   1490	if (i == bus_cfg.nr_of_link_frequencies) {
   1491		ret = dev_err_probe(ov7251->dev, -EINVAL,
   1492				    "no supported link freq found\n");
   1493		goto out_free_bus_cfg;
   1494	}
   1495
   1496	ov7251->link_freq_idx = i;
   1497
   1498out_free_bus_cfg:
   1499	v4l2_fwnode_endpoint_free(&bus_cfg);
   1500
   1501	return ret;
   1502}
   1503
   1504static int ov7251_detect_chip(struct ov7251 *ov7251)
   1505{
   1506	u8 chip_id_high, chip_id_low, chip_rev;
   1507	int ret;
   1508
   1509	ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_HIGH, &chip_id_high);
   1510	if (ret < 0 || chip_id_high != OV7251_CHIP_ID_HIGH_BYTE)
   1511		return dev_err_probe(ov7251->dev, -ENODEV,
   1512				     "could not read ID high\n");
   1513
   1514	ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_LOW, &chip_id_low);
   1515	if (ret < 0 || chip_id_low != OV7251_CHIP_ID_LOW_BYTE)
   1516		return dev_err_probe(ov7251->dev, -ENODEV,
   1517				     "could not read ID low\n");
   1518
   1519	ret = ov7251_read_reg(ov7251, OV7251_SC_GP_IO_IN1, &chip_rev);
   1520	if (ret < 0)
   1521		return dev_err_probe(ov7251->dev, -ENODEV,
   1522				     "could not read revision\n");
   1523	chip_rev >>= 4;
   1524
   1525	dev_info(ov7251->dev,
   1526		 "OV7251 revision %x (%s) detected at address 0x%02x\n",
   1527		 chip_rev,
   1528		 chip_rev == 0x4 ? "1A / 1B" :
   1529		 chip_rev == 0x5 ? "1C / 1D" :
   1530		 chip_rev == 0x6 ? "1E" :
   1531		 chip_rev == 0x7 ? "1F" : "unknown",
   1532		 ov7251->i2c_client->addr);
   1533
   1534	return 0;
   1535}
   1536
   1537static int ov7251_init_ctrls(struct ov7251 *ov7251)
   1538{
   1539	int vblank_max, vblank_def;
   1540	s64 pixel_rate;
   1541	int hblank;
   1542
   1543	v4l2_ctrl_handler_init(&ov7251->ctrls, 7);
   1544	ov7251->ctrls.lock = &ov7251->lock;
   1545
   1546	v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
   1547			  V4L2_CID_HFLIP, 0, 1, 1, 0);
   1548	v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
   1549			  V4L2_CID_VFLIP, 0, 1, 1, 0);
   1550	ov7251->exposure = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
   1551					     V4L2_CID_EXPOSURE, 1, 32, 1, 32);
   1552	ov7251->gain = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
   1553					 V4L2_CID_GAIN, 16, 1023, 1, 16);
   1554	v4l2_ctrl_new_std_menu_items(&ov7251->ctrls, &ov7251_ctrl_ops,
   1555				     V4L2_CID_TEST_PATTERN,
   1556				     ARRAY_SIZE(ov7251_test_pattern_menu) - 1,
   1557				     0, 0, ov7251_test_pattern_menu);
   1558
   1559	pixel_rate = pixel_rates[ov7251->link_freq_idx];
   1560	ov7251->pixel_clock = v4l2_ctrl_new_std(&ov7251->ctrls,
   1561						&ov7251_ctrl_ops,
   1562						V4L2_CID_PIXEL_RATE,
   1563						pixel_rate, INT_MAX,
   1564						pixel_rate, pixel_rate);
   1565	ov7251->link_freq = v4l2_ctrl_new_int_menu(&ov7251->ctrls,
   1566						   &ov7251_ctrl_ops,
   1567						   V4L2_CID_LINK_FREQ,
   1568						   ARRAY_SIZE(link_freq) - 1,
   1569						   ov7251->link_freq_idx,
   1570						   link_freq);
   1571	if (ov7251->link_freq)
   1572		ov7251->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
   1573	if (ov7251->pixel_clock)
   1574		ov7251->pixel_clock->flags |= V4L2_CTRL_FLAG_READ_ONLY;
   1575
   1576	hblank = OV7251_FIXED_PPL - ov7251->current_mode->width;
   1577	ov7251->hblank = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
   1578					   V4L2_CID_HBLANK, hblank, hblank, 1,
   1579					   hblank);
   1580	if (ov7251->hblank)
   1581		ov7251->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
   1582
   1583	vblank_max = OV7251_TIMING_MAX_VTS - ov7251->current_mode->height;
   1584	vblank_def = ov7251->current_mode->vts - ov7251->current_mode->height;
   1585	ov7251->vblank = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
   1586					   V4L2_CID_VBLANK,
   1587					   OV7251_TIMING_MIN_VTS, vblank_max, 1,
   1588					   vblank_def);
   1589
   1590	ov7251->sd.ctrl_handler = &ov7251->ctrls;
   1591
   1592	if (ov7251->ctrls.error) {
   1593		v4l2_ctrl_handler_free(&ov7251->ctrls);
   1594		return ov7251->ctrls.error;
   1595	}
   1596
   1597	return 0;
   1598}
   1599
   1600static int ov7251_probe(struct i2c_client *client)
   1601{
   1602	struct device *dev = &client->dev;
   1603	struct ov7251 *ov7251;
   1604	unsigned int rate = 0, clk_rate = 0;
   1605	int ret;
   1606	int i;
   1607
   1608	ov7251 = devm_kzalloc(dev, sizeof(struct ov7251), GFP_KERNEL);
   1609	if (!ov7251)
   1610		return -ENOMEM;
   1611
   1612	ov7251->i2c_client = client;
   1613	ov7251->dev = dev;
   1614
   1615	ret = ov7251_check_hwcfg(ov7251);
   1616	if (ret)
   1617		return ret;
   1618
   1619	/* get system clock (xclk) */
   1620	ov7251->xclk = devm_clk_get_optional(dev, NULL);
   1621	if (IS_ERR(ov7251->xclk))
   1622		return dev_err_probe(dev, PTR_ERR(ov7251->xclk),
   1623				     "could not get xclk");
   1624
   1625	/*
   1626	 * We could have either a 24MHz or 19.2MHz clock rate from either DT or
   1627	 * ACPI. We also need to support the IPU3 case which will have both an
   1628	 * external clock AND a clock-frequency property.
   1629	 */
   1630	ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
   1631				       &rate);
   1632	if (ret && !ov7251->xclk)
   1633		return dev_err_probe(dev, ret, "invalid clock config\n");
   1634
   1635	clk_rate = clk_get_rate(ov7251->xclk);
   1636	ov7251->xclk_freq = clk_rate ? clk_rate : rate;
   1637
   1638	if (ov7251->xclk_freq == 0)
   1639		return dev_err_probe(dev, -EINVAL, "invalid clock frequency\n");
   1640
   1641	if (!ret && ov7251->xclk) {
   1642		ret = clk_set_rate(ov7251->xclk, rate);
   1643		if (ret)
   1644			return dev_err_probe(dev, ret,
   1645					     "failed to set clock rate\n");
   1646	}
   1647
   1648	for (i = 0; i < ARRAY_SIZE(supported_xclk_rates); i++)
   1649		if (ov7251->xclk_freq == supported_xclk_rates[i])
   1650			break;
   1651
   1652	if (i == ARRAY_SIZE(supported_xclk_rates))
   1653		return dev_err_probe(dev, -EINVAL,
   1654				     "clock rate %u Hz is unsupported\n",
   1655				     ov7251->xclk_freq);
   1656
   1657	ov7251->pll_cfgs = ov7251_pll_cfgs[i];
   1658
   1659	ov7251->io_regulator = devm_regulator_get(dev, "vdddo");
   1660	if (IS_ERR(ov7251->io_regulator)) {
   1661		dev_err(dev, "cannot get io regulator\n");
   1662		return PTR_ERR(ov7251->io_regulator);
   1663	}
   1664
   1665	ov7251->core_regulator = devm_regulator_get(dev, "vddd");
   1666	if (IS_ERR(ov7251->core_regulator)) {
   1667		dev_err(dev, "cannot get core regulator\n");
   1668		return PTR_ERR(ov7251->core_regulator);
   1669	}
   1670
   1671	ov7251->analog_regulator = devm_regulator_get(dev, "vdda");
   1672	if (IS_ERR(ov7251->analog_regulator)) {
   1673		dev_err(dev, "cannot get analog regulator\n");
   1674		return PTR_ERR(ov7251->analog_regulator);
   1675	}
   1676
   1677	ov7251->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_HIGH);
   1678	if (IS_ERR(ov7251->enable_gpio)) {
   1679		dev_err(dev, "cannot get enable gpio\n");
   1680		return PTR_ERR(ov7251->enable_gpio);
   1681	}
   1682
   1683	mutex_init(&ov7251->lock);
   1684
   1685	ov7251->current_mode = &ov7251_mode_info_data[0];
   1686	ret = ov7251_init_ctrls(ov7251);
   1687	if (ret) {
   1688		dev_err_probe(dev, ret, "error during v4l2 ctrl init\n");
   1689		goto destroy_mutex;
   1690	}
   1691
   1692	v4l2_i2c_subdev_init(&ov7251->sd, client, &ov7251_subdev_ops);
   1693	ov7251->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
   1694	ov7251->pad.flags = MEDIA_PAD_FL_SOURCE;
   1695	ov7251->sd.dev = &client->dev;
   1696	ov7251->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
   1697
   1698	ret = media_entity_pads_init(&ov7251->sd.entity, 1, &ov7251->pad);
   1699	if (ret < 0) {
   1700		dev_err(dev, "could not register media entity\n");
   1701		goto free_ctrl;
   1702	}
   1703
   1704	ret = ov7251_set_power_on(ov7251->dev);
   1705	if (ret)
   1706		goto free_entity;
   1707
   1708	ret = ov7251_detect_chip(ov7251);
   1709	if (ret)
   1710		goto power_down;
   1711
   1712	pm_runtime_set_active(&client->dev);
   1713	pm_runtime_get_noresume(&client->dev);
   1714	pm_runtime_enable(&client->dev);
   1715
   1716	ret = ov7251_read_reg(ov7251, OV7251_PRE_ISP_00,
   1717			      &ov7251->pre_isp_00);
   1718	if (ret < 0) {
   1719		dev_err(dev, "could not read test pattern value\n");
   1720		ret = -ENODEV;
   1721		goto err_pm_runtime;
   1722	}
   1723
   1724	ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT1,
   1725			      &ov7251->timing_format1);
   1726	if (ret < 0) {
   1727		dev_err(dev, "could not read vflip value\n");
   1728		ret = -ENODEV;
   1729		goto err_pm_runtime;
   1730	}
   1731
   1732	ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT2,
   1733			      &ov7251->timing_format2);
   1734	if (ret < 0) {
   1735		dev_err(dev, "could not read hflip value\n");
   1736		ret = -ENODEV;
   1737		goto err_pm_runtime;
   1738	}
   1739
   1740	pm_runtime_set_autosuspend_delay(&client->dev, 1000);
   1741	pm_runtime_use_autosuspend(&client->dev);
   1742	pm_runtime_put_autosuspend(&client->dev);
   1743
   1744	ret = v4l2_async_register_subdev(&ov7251->sd);
   1745	if (ret < 0) {
   1746		dev_err(dev, "could not register v4l2 device\n");
   1747		goto free_entity;
   1748	}
   1749
   1750	ov7251_entity_init_cfg(&ov7251->sd, NULL);
   1751
   1752	return 0;
   1753
   1754err_pm_runtime:
   1755	pm_runtime_disable(ov7251->dev);
   1756	pm_runtime_put_noidle(ov7251->dev);
   1757power_down:
   1758	ov7251_set_power_off(ov7251->dev);
   1759free_entity:
   1760	media_entity_cleanup(&ov7251->sd.entity);
   1761free_ctrl:
   1762	v4l2_ctrl_handler_free(&ov7251->ctrls);
   1763destroy_mutex:
   1764	mutex_destroy(&ov7251->lock);
   1765
   1766	return ret;
   1767}
   1768
   1769static int ov7251_remove(struct i2c_client *client)
   1770{
   1771	struct v4l2_subdev *sd = i2c_get_clientdata(client);
   1772	struct ov7251 *ov7251 = to_ov7251(sd);
   1773
   1774	v4l2_async_unregister_subdev(&ov7251->sd);
   1775	media_entity_cleanup(&ov7251->sd.entity);
   1776	v4l2_ctrl_handler_free(&ov7251->ctrls);
   1777	mutex_destroy(&ov7251->lock);
   1778
   1779	pm_runtime_disable(ov7251->dev);
   1780	if (!pm_runtime_status_suspended(ov7251->dev))
   1781		ov7251_set_power_off(ov7251->dev);
   1782	pm_runtime_set_suspended(ov7251->dev);
   1783
   1784	return 0;
   1785}
   1786
   1787static const struct dev_pm_ops ov7251_pm_ops = {
   1788	SET_RUNTIME_PM_OPS(ov7251_set_power_off, ov7251_set_power_on, NULL)
   1789};
   1790
   1791static const struct of_device_id ov7251_of_match[] = {
   1792	{ .compatible = "ovti,ov7251" },
   1793	{ /* sentinel */ }
   1794};
   1795MODULE_DEVICE_TABLE(of, ov7251_of_match);
   1796
   1797static const struct acpi_device_id ov7251_acpi_match[] = {
   1798	{ "INT347E" },
   1799	{ }
   1800};
   1801MODULE_DEVICE_TABLE(acpi, ov7251_acpi_match);
   1802
   1803static struct i2c_driver ov7251_i2c_driver = {
   1804	.driver = {
   1805		.of_match_table = ov7251_of_match,
   1806		.acpi_match_table = ov7251_acpi_match,
   1807		.name  = "ov7251",
   1808		.pm = &ov7251_pm_ops,
   1809	},
   1810	.probe_new  = ov7251_probe,
   1811	.remove = ov7251_remove,
   1812};
   1813
   1814module_i2c_driver(ov7251_i2c_driver);
   1815
   1816MODULE_DESCRIPTION("Omnivision OV7251 Camera Driver");
   1817MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
   1818MODULE_LICENSE("GPL v2");