tw686x-regs.h (4232B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* DMA controller registers */ 3#define REG8_1(a0) ((const u16[8]) { a0, a0 + 1, a0 + 2, a0 + 3, \ 4 a0 + 4, a0 + 5, a0 + 6, a0 + 7}) 5#define REG8_2(a0) ((const u16[8]) { a0, a0 + 2, a0 + 4, a0 + 6, \ 6 a0 + 8, a0 + 0xa, a0 + 0xc, a0 + 0xe}) 7#define REG8_8(a0) ((const u16[8]) { a0, a0 + 8, a0 + 0x10, a0 + 0x18, \ 8 a0 + 0x20, a0 + 0x28, a0 + 0x30, \ 9 a0 + 0x38}) 10#define INT_STATUS 0x00 11#define PB_STATUS 0x01 12#define DMA_CMD 0x02 13#define VIDEO_FIFO_STATUS 0x03 14#define VIDEO_CHANNEL_ID 0x04 15#define VIDEO_PARSER_STATUS 0x05 16#define SYS_SOFT_RST 0x06 17#define DMA_PAGE_TABLE0_ADDR ((const u16[8]) { 0x08, 0xd0, 0xd2, 0xd4, \ 18 0xd6, 0xd8, 0xda, 0xdc }) 19#define DMA_PAGE_TABLE1_ADDR ((const u16[8]) { 0x09, 0xd1, 0xd3, 0xd5, \ 20 0xd7, 0xd9, 0xdb, 0xdd }) 21#define DMA_CHANNEL_ENABLE 0x0a 22#define DMA_CONFIG 0x0b 23#define DMA_TIMER_INTERVAL 0x0c 24#define DMA_CHANNEL_TIMEOUT 0x0d 25#define VDMA_CHANNEL_CONFIG REG8_1(0x10) 26#define ADMA_P_ADDR REG8_2(0x18) 27#define ADMA_B_ADDR REG8_2(0x19) 28#define DMA10_P_ADDR 0x28 29#define DMA10_B_ADDR 0x29 30#define VIDEO_CONTROL1 0x2a 31#define VIDEO_CONTROL2 0x2b 32#define AUDIO_CONTROL1 0x2c 33#define AUDIO_CONTROL2 0x2d 34#define PHASE_REF 0x2e 35#define GPIO_REG 0x2f 36#define INTL_HBAR_CTRL REG8_1(0x30) 37#define AUDIO_CONTROL3 0x38 38#define VIDEO_FIELD_CTRL REG8_1(0x39) 39#define HSCALER_CTRL REG8_1(0x42) 40#define VIDEO_SIZE REG8_1(0x4A) 41#define VIDEO_SIZE_F2 REG8_1(0x52) 42#define MD_CONF REG8_1(0x60) 43#define MD_INIT REG8_1(0x68) 44#define MD_MAP0 REG8_1(0x70) 45#define VDMA_P_ADDR REG8_8(0x80) /* not used in DMA SG mode */ 46#define VDMA_WHP REG8_8(0x81) 47#define VDMA_B_ADDR REG8_8(0x82) 48#define VDMA_F2_P_ADDR REG8_8(0x84) 49#define VDMA_F2_WHP REG8_8(0x85) 50#define VDMA_F2_B_ADDR REG8_8(0x86) 51#define EP_REG_ADDR 0xfe 52#define EP_REG_DATA 0xff 53 54/* Video decoder registers */ 55#define VDREG8(a0) ((const u16[8]) { \ 56 a0 + 0x000, a0 + 0x010, a0 + 0x020, a0 + 0x030, \ 57 a0 + 0x100, a0 + 0x110, a0 + 0x120, a0 + 0x130}) 58#define VIDSTAT VDREG8(0x100) 59#define BRIGHT VDREG8(0x101) 60#define CONTRAST VDREG8(0x102) 61#define SHARPNESS VDREG8(0x103) 62#define SAT_U VDREG8(0x104) 63#define SAT_V VDREG8(0x105) 64#define HUE VDREG8(0x106) 65#define CROP_HI VDREG8(0x107) 66#define VDELAY_LO VDREG8(0x108) 67#define VACTIVE_LO VDREG8(0x109) 68#define HDELAY_LO VDREG8(0x10a) 69#define HACTIVE_LO VDREG8(0x10b) 70#define MVSN VDREG8(0x10c) 71#define STATUS2 VDREG8(0x10d) 72#define SDT VDREG8(0x10e) 73#define SDT_EN VDREG8(0x10f) 74 75#define VSCALE_LO VDREG8(0x144) 76#define SCALE_HI VDREG8(0x145) 77#define HSCALE_LO VDREG8(0x146) 78#define F2CROP_HI VDREG8(0x147) 79#define F2VDELAY_LO VDREG8(0x148) 80#define F2VACTIVE_LO VDREG8(0x149) 81#define F2HDELAY_LO VDREG8(0x14a) 82#define F2HACTIVE_LO VDREG8(0x14b) 83#define F2VSCALE_LO VDREG8(0x14c) 84#define F2SCALE_HI VDREG8(0x14d) 85#define F2HSCALE_LO VDREG8(0x14e) 86#define F2CNT VDREG8(0x14f) 87 88#define VDREG2(a0) ((const u16[2]) { a0, a0 + 0x100 }) 89#define SRST VDREG2(0x180) 90#define ACNTL VDREG2(0x181) 91#define ACNTL2 VDREG2(0x182) 92#define CNTRL1 VDREG2(0x183) 93#define CKHY VDREG2(0x184) 94#define SHCOR VDREG2(0x185) 95#define CORING VDREG2(0x186) 96#define CLMPG VDREG2(0x187) 97#define IAGC VDREG2(0x188) 98#define VCTRL1 VDREG2(0x18f) 99#define MISC1 VDREG2(0x194) 100#define LOOP VDREG2(0x195) 101#define MISC2 VDREG2(0x196) 102 103#define CLMD VDREG2(0x197) 104#define ANPWRDOWN VDREG2(0x1ce) 105#define AIGAIN ((const u16[8]) { 0x1d0, 0x1d1, 0x1d2, 0x1d3, \ 106 0x2d0, 0x2d1, 0x2d2, 0x2d3 }) 107 108#define SYS_MODE_DMA_SHIFT 13 109#define AUDIO_DMA_SIZE_SHIFT 19 110#define AUDIO_DMA_SIZE_MIN SZ_512 111#define AUDIO_DMA_SIZE_MAX SZ_4K 112#define AUDIO_DMA_SIZE_MASK (SZ_8K - 1) 113 114#define DMA_CMD_ENABLE BIT(31) 115#define INT_STATUS_DMA_TOUT BIT(17) 116#define TW686X_VIDSTAT_HLOCK BIT(6) 117#define TW686X_VIDSTAT_VDLOSS BIT(7) 118 119#define TW686X_STD_NTSC_M 0 120#define TW686X_STD_PAL 1 121#define TW686X_STD_SECAM 2 122#define TW686X_STD_NTSC_443 3 123#define TW686X_STD_PAL_M 4 124#define TW686X_STD_PAL_CN 5 125#define TW686X_STD_PAL_60 6 126 127#define TW686X_FIELD_MODE 0x3 128#define TW686X_FRAME_MODE 0x2 129/* 0x1 is reserved */ 130#define TW686X_SG_MODE 0x0 131 132#define TW686X_FIFO_ERROR(x) (x & ~(0xff))