vde.h (6062B)
1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * NVIDIA Tegra Video decoder driver 4 * 5 * Copyright (C) 2016-2019 GRATE-DRIVER project 6 */ 7 8#ifndef TEGRA_VDE_H 9#define TEGRA_VDE_H 10 11#include <linux/completion.h> 12#include <linux/dma-direction.h> 13#include <linux/iova.h> 14#include <linux/list.h> 15#include <linux/mutex.h> 16#include <linux/types.h> 17#include <linux/workqueue.h> 18 19#include <media/media-device.h> 20#include <media/videobuf2-dma-contig.h> 21#include <media/videobuf2-dma-sg.h> 22#include <media/v4l2-ctrls.h> 23#include <media/v4l2-device.h> 24#include <media/v4l2-event.h> 25#include <media/v4l2-ioctl.h> 26#include <media/v4l2-mem2mem.h> 27 28#define ICMDQUE_WR 0x00 29#define CMDQUE_CONTROL 0x08 30#define INTR_STATUS 0x18 31#define BSE_INT_ENB 0x40 32#define BSE_CONFIG 0x44 33 34#define BSE_ICMDQUE_EMPTY BIT(3) 35#define BSE_DMA_BUSY BIT(23) 36 37#define BSEV_ALIGN SZ_1 38#define FRAMEID_ALIGN SZ_256 39#define SXE_BUFFER SZ_32K 40#define VDE_ATOM SZ_16 41 42struct clk; 43struct dma_buf; 44struct gen_pool; 45struct tegra_ctx; 46struct iommu_group; 47struct iommu_domain; 48struct reset_control; 49struct dma_buf_attachment; 50struct tegra_vde_h264_frame; 51struct tegra_vde_h264_decoder_ctx; 52 53struct tegra_video_frame { 54 struct dma_buf_attachment *y_dmabuf_attachment; 55 struct dma_buf_attachment *cb_dmabuf_attachment; 56 struct dma_buf_attachment *cr_dmabuf_attachment; 57 struct dma_buf_attachment *aux_dmabuf_attachment; 58 dma_addr_t y_addr; 59 dma_addr_t cb_addr; 60 dma_addr_t cr_addr; 61 dma_addr_t aux_addr; 62 u32 frame_num; 63 u32 flags; 64 u32 luma_atoms_pitch; 65 u32 chroma_atoms_pitch; 66}; 67 68struct tegra_coded_fmt_desc { 69 u32 fourcc; 70 struct v4l2_frmsize_stepwise frmsize; 71 unsigned int num_decoded_fmts; 72 const u32 *decoded_fmts; 73 int (*decode_run)(struct tegra_ctx *ctx); 74 int (*decode_wait)(struct tegra_ctx *ctx); 75}; 76 77struct tegra_vde_soc { 78 bool supports_ref_pic_marking; 79 const struct tegra_coded_fmt_desc *coded_fmts; 80 u32 num_coded_fmts; 81}; 82 83struct tegra_vde_bo { 84 struct iova *iova; 85 struct sg_table sgt; 86 struct tegra_vde *vde; 87 enum dma_data_direction dma_dir; 88 unsigned long dma_attrs; 89 dma_addr_t dma_handle; 90 dma_addr_t dma_addr; 91 void *dma_cookie; 92 size_t size; 93}; 94 95struct tegra_vde { 96 void __iomem *sxe; 97 void __iomem *bsev; 98 void __iomem *mbe; 99 void __iomem *ppe; 100 void __iomem *mce; 101 void __iomem *tfe; 102 void __iomem *ppb; 103 void __iomem *vdma; 104 void __iomem *frameid; 105 struct device *dev; 106 struct mutex lock; 107 struct mutex map_lock; 108 struct list_head map_list; 109 struct reset_control *rst; 110 struct reset_control *rst_mc; 111 struct gen_pool *iram_pool; 112 struct completion decode_completion; 113 struct clk *clk; 114 struct iommu_domain *domain; 115 struct iommu_group *group; 116 struct iova_domain iova; 117 struct iova *iova_resv_static_addresses; 118 struct iova *iova_resv_last_page; 119 const struct tegra_vde_soc *soc; 120 struct tegra_vde_bo *secure_bo; 121 dma_addr_t bitstream_data_addr; 122 dma_addr_t iram_lists_addr; 123 u32 *iram; 124 struct v4l2_device v4l2_dev; 125 struct v4l2_m2m_dev *m2m; 126 struct media_device mdev; 127 struct video_device vdev; 128 struct mutex v4l2_lock; 129 struct workqueue_struct *wq; 130 struct tegra_video_frame frames[V4L2_H264_NUM_DPB_ENTRIES + 1]; 131}; 132 133int tegra_vde_alloc_bo(struct tegra_vde *vde, 134 struct tegra_vde_bo **ret_bo, 135 enum dma_data_direction dma_dir, 136 size_t size); 137void tegra_vde_free_bo(struct tegra_vde_bo *bo); 138 139struct tegra_ctx_h264 { 140 const struct v4l2_ctrl_h264_decode_params *decode_params; 141 const struct v4l2_ctrl_h264_sps *sps; 142 const struct v4l2_ctrl_h264_pps *pps; 143}; 144 145struct tegra_ctx { 146 struct tegra_vde *vde; 147 struct tegra_ctx_h264 h264; 148 struct work_struct work; 149 struct v4l2_fh fh; 150 struct v4l2_ctrl_handler hdl; 151 struct v4l2_format coded_fmt; 152 struct v4l2_format decoded_fmt; 153 const struct tegra_coded_fmt_desc *coded_fmt_desc; 154 struct v4l2_ctrl *ctrls[]; 155}; 156 157struct tegra_m2m_buffer { 158 struct v4l2_m2m_buffer m2m; 159 struct dma_buf_attachment *a[VB2_MAX_PLANES]; 160 dma_addr_t dma_base[VB2_MAX_PLANES]; 161 dma_addr_t dma_addr[VB2_MAX_PLANES]; 162 struct iova *iova[VB2_MAX_PLANES]; 163 struct tegra_vde_bo *aux; 164 bool b_frame; 165}; 166 167static inline struct tegra_m2m_buffer * 168vb_to_tegra_buf(struct vb2_buffer *vb) 169{ 170 struct v4l2_m2m_buffer *m2m = container_of(vb, struct v4l2_m2m_buffer, 171 vb.vb2_buf); 172 173 return container_of(m2m, struct tegra_m2m_buffer, m2m); 174} 175 176void tegra_vde_prepare_control_data(struct tegra_ctx *ctx, u32 id); 177 178void tegra_vde_writel(struct tegra_vde *vde, u32 value, void __iomem *base, 179 u32 offset); 180u32 tegra_vde_readl(struct tegra_vde *vde, void __iomem *base, u32 offset); 181void tegra_vde_set_bits(struct tegra_vde *vde, u32 mask, void __iomem *base, 182 u32 offset); 183 184int tegra_vde_h264_decode_run(struct tegra_ctx *ctx); 185int tegra_vde_h264_decode_wait(struct tegra_ctx *ctx); 186 187int tegra_vde_iommu_init(struct tegra_vde *vde); 188void tegra_vde_iommu_deinit(struct tegra_vde *vde); 189int tegra_vde_iommu_map(struct tegra_vde *vde, 190 struct sg_table *sgt, 191 struct iova **iovap, 192 size_t size); 193void tegra_vde_iommu_unmap(struct tegra_vde *vde, struct iova *iova); 194 195int tegra_vde_dmabuf_cache_map(struct tegra_vde *vde, 196 struct dma_buf *dmabuf, 197 enum dma_data_direction dma_dir, 198 struct dma_buf_attachment **ap, 199 dma_addr_t *addrp); 200void tegra_vde_dmabuf_cache_unmap(struct tegra_vde *vde, 201 struct dma_buf_attachment *a, 202 bool release); 203void tegra_vde_dmabuf_cache_unmap_sync(struct tegra_vde *vde); 204void tegra_vde_dmabuf_cache_unmap_all(struct tegra_vde *vde); 205 206static __maybe_unused char const * 207tegra_vde_reg_base_name(struct tegra_vde *vde, void __iomem *base) 208{ 209 if (vde->sxe == base) 210 return "SXE"; 211 212 if (vde->bsev == base) 213 return "BSEV"; 214 215 if (vde->mbe == base) 216 return "MBE"; 217 218 if (vde->ppe == base) 219 return "PPE"; 220 221 if (vde->mce == base) 222 return "MCE"; 223 224 if (vde->tfe == base) 225 return "TFE"; 226 227 if (vde->ppb == base) 228 return "PPB"; 229 230 if (vde->vdma == base) 231 return "VDMA"; 232 233 if (vde->frameid == base) 234 return "FRAMEID"; 235 236 return "???"; 237} 238 239int tegra_vde_v4l2_init(struct tegra_vde *vde); 240void tegra_vde_v4l2_deinit(struct tegra_vde *vde); 241 242#endif /* TEGRA_VDE_H */