cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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camss-csiphy.h (2416B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * camss-csiphy.h
      4 *
      5 * Qualcomm MSM Camera Subsystem - CSIPHY Module
      6 *
      7 * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
      8 * Copyright (C) 2016-2018 Linaro Ltd.
      9 */
     10#ifndef QC_MSM_CAMSS_CSIPHY_H
     11#define QC_MSM_CAMSS_CSIPHY_H
     12
     13#include <linux/clk.h>
     14#include <linux/interrupt.h>
     15#include <media/media-entity.h>
     16#include <media/v4l2-device.h>
     17#include <media/v4l2-mediabus.h>
     18#include <media/v4l2-subdev.h>
     19
     20#define MSM_CSIPHY_PAD_SINK 0
     21#define MSM_CSIPHY_PAD_SRC 1
     22#define MSM_CSIPHY_PADS_NUM 2
     23
     24struct csiphy_lane {
     25	u8 pos;
     26	u8 pol;
     27};
     28
     29struct csiphy_lanes_cfg {
     30	int num_data;
     31	struct csiphy_lane *data;
     32	struct csiphy_lane clk;
     33};
     34
     35struct csiphy_csi2_cfg {
     36	struct csiphy_lanes_cfg lane_cfg;
     37};
     38
     39struct csiphy_config {
     40	u8 combo_mode;
     41	u8 csid_id;
     42	struct csiphy_csi2_cfg *csi2;
     43};
     44
     45struct csiphy_device;
     46
     47struct csiphy_hw_ops {
     48	/*
     49	 * csiphy_get_lane_mask - Calculate CSI2 lane mask configuration parameter
     50	 * @lane_cfg - CSI2 lane configuration
     51	 *
     52	 * Return lane mask
     53	 */
     54	u8 (*get_lane_mask)(struct csiphy_lanes_cfg *lane_cfg);
     55	void (*hw_version_read)(struct csiphy_device *csiphy,
     56				struct device *dev);
     57	void (*reset)(struct csiphy_device *csiphy);
     58	void (*lanes_enable)(struct csiphy_device *csiphy,
     59			     struct csiphy_config *cfg,
     60			     s64 link_freq, u8 lane_mask);
     61	void (*lanes_disable)(struct csiphy_device *csiphy,
     62			      struct csiphy_config *cfg);
     63	irqreturn_t (*isr)(int irq, void *dev);
     64};
     65
     66struct csiphy_device {
     67	struct camss *camss;
     68	u8 id;
     69	struct v4l2_subdev subdev;
     70	struct media_pad pads[MSM_CSIPHY_PADS_NUM];
     71	void __iomem *base;
     72	void __iomem *base_clk_mux;
     73	u32 irq;
     74	char irq_name[30];
     75	struct camss_clock *clock;
     76	bool *rate_set;
     77	int nclocks;
     78	u32 timer_clk_rate;
     79	struct csiphy_config cfg;
     80	struct v4l2_mbus_framefmt fmt[MSM_CSIPHY_PADS_NUM];
     81	const struct csiphy_hw_ops *ops;
     82	const struct csiphy_format *formats;
     83	unsigned int nformats;
     84};
     85
     86struct resources;
     87
     88int msm_csiphy_subdev_init(struct camss *camss,
     89			   struct csiphy_device *csiphy,
     90			   const struct resources *res, u8 id);
     91
     92int msm_csiphy_register_entity(struct csiphy_device *csiphy,
     93			       struct v4l2_device *v4l2_dev);
     94
     95void msm_csiphy_unregister_entity(struct csiphy_device *csiphy);
     96
     97extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0;
     98extern const struct csiphy_hw_ops csiphy_ops_3ph_1_0;
     99
    100#endif /* QC_MSM_CAMSS_CSIPHY_H */